JPH088405A - DC test facilitating circuit, DC test control circuit, and semiconductor integrated circuit including them - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object of the present invention to reduce the number of test pattern inputs for performing a DC test and to reduce the test time by reducing the number of test patterns. [Configuration] An output buffer DC test facilitation circuit 5, a tri-state output buffer DC test facilitation circuit 6, and a bidirectional buffer DC test facilitation circuit 6a in which an output of an internal circuit 18 is a DC test facilitation circuit. It is connected. Also, the output buffer DC test facilitation circuit 5,
The DC test facilitation circuit 6 for the tri-state output buffer and the DC test facilitation circuit 6a for the bidirectional buffer are
Each is connected to the C test control circuit 7. [Effect] Since the DC test of the output means is performed based on the control signal provided without passing through the internal circuit, the number of times of inputting the signal for the DC test is higher than that when the DC test is performed through the internal circuit. It can be reduced and the test time can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC testability design for an output buffer used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 11 shows a circuit configuration of a semiconductor integrated circuit (LSI) 100 using an input / output buffer. Figure 11
, The six input buffers 1 are combined circuit 1
4a, and the output of the combinational circuit 14a is connected to the data input terminals D of the five flip-flops 13. A timing signal is applied to the timing signal input terminal T of the flip-flop 13 from the combinational circuit 14a. The output terminal Q of the flip-flop 13 is connected to the combinational circuit 14b, and the output of the combinational circuit 14b is connected to the data input terminals D of the five flip-flops 13. A timing signal is applied to the timing signal input terminal T of the flip-flop 13 from the combinational circuit 14b. The output terminal Q of the flip-flop 13 is output via the combinational circuit 14b to the output buffer 2, the tri-state output buffer 3,
It is applied to the bidirectional buffer 4 including the tri-state output buffer 41 and the buffer 42. Further, the LSI external input terminal 9 is individually connected to the input buffer 1, the LSI external output terminal 10 is connected to the output buffer 2, and the LSI external output terminal 11 is connected to the tri-state output buffer.
, And an LSI external bidirectional terminal is connected to the bidirectional buffer. Note that the numbers of the input buffers 1 and the flip-flops 13 are numbers for convenience and do not include a special meaning, and a larger number is required in an actual LSI.

Next, a conventional DC test (direct current test) method will be described with reference to FIG. In FIG. 11, when measuring the output voltages of the output buffer 2, the tri-state output buffer 3, and the bidirectional buffer 4 in the output mode,
Input buffer 1 and bidirectional buffer 4 in input mode
The output voltage of the output buffer 2, the tri-state output buffer 3 and the bidirectional buffer 4 in the output mode is fixed to a constant output level by the signal input from the device, and the voltage measuring circuit or the current measuring circuit in the tester is connected. It was judged whether it was normal or not.

In the conventional LSI, there are many circuit configurations using a memory element such as the flip-flop 13 used in FIG. 11, and input signals are input from the LSI external input terminal 9 to the input buffer 1 and the combinational circuits 14a, 14b, 14c. Since it is output via the flip-flop 13 and the like, it is difficult to obtain a desired output voltage level from the LSI external output terminals 10 and 11 and the LSI external bidirectional terminal 12 within the period in which the input signal is given.

In the LSI 100 shown in FIG. 11, the flip-flop 13 is combined with the combinational circuits 14a and 14a.
Since it is used to hold the operation result of b, the output state of the LSI external output terminals 10 and 11 and the LSI external bidirectional terminal 12 can be determined by applying the test pattern for at least two cycles. It will be possible. At this time, all of the output buffer 2, the tri-state output buffer 3, and the bidirectional buffer 4 in the output mode, which are the measurement targets, output the high- or low-level voltage output within the same cycle. , 14b, 14c, it was usually difficult because of the circuit configuration.

Most of the mass-produced testers have the output buffer 2 or the output buffer 2 having the same output voltage value.
It has only the function of simultaneously testing the tri-state output buffer 3 or the bidirectional buffer 4 in the output mode. However, it is almost impossible for all the output buffers of the LSI to output the same voltage all at once, and it is difficult to simultaneously perform the DC test on all the output buffers to be measured. In addition, AS with about 512 signal pins
Since many ICs have been developed, it is almost impossible to simultaneously perform the DC test of all the measurement target output buffers, and at present, the DC test cannot be realized except to increase the number of test patterns.

Moreover, in the conventional LSI, since the test pattern of the DC test is applied to the output buffer through the internal circuit of the LSI including the combinational circuit, the voltage applied from the tester at the time of measurement by the tester connected to the output buffer. The current may change the logical state of the internal circuit of the LSI.

For example, in the DC test of the bidirectional buffer 4, a dynamic load circuit composed of a diode bridge in a tester as shown in FIG. 12 is connected and measured. The dynamic load circuit shown in FIG. 12 includes a diode bridge DB, a diode D1 and a diode D2 provided on the positive electrode side and the negative electrode side thereof, and a diode D1.
Current source I1 connected between the power source V3 and the power source V3, the current source I2 connected between the diode D2 and the power source V1, and the power source V connected to one end of the diode bridge DB.
2 and a terminal to be measured is connected to the other end P of the diode bridge DB.

In this circuit, if a potential difference occurs between the power supply V3 and the measurement terminal, a current corresponding to the potential difference is applied to the measurement terminal, and conversely, a potential difference occurs between the power supply V3 and the measurement terminal. Then, the current corresponding to the potential difference is extracted from the measurement terminal.

The bidirectional buffer 4 outputs a signal output by itself as L
Since the configuration is such that the signal is input to the internal circuit of S1100, if a current is extracted and the voltage drops during measurement, for example, a signal of High should be input to the internal circuit of LS1100, but a signal of Low should be input. Therefore, the logic state of the internal circuit of the LS1100 changes.

In order to reset such an unexpected change in the logic state of the internal circuit, it is necessary to re-input all the test patterns, and it is unavoidable that the DC test time becomes long.

As a method of facilitating the creation of a test pattern for a sequential circuit, there is a method of designing a sequential circuit by a scan method (hereinafter referred to as scan design). FIG. 13 shows an LSI 200 in which the circuit of the conventional LSI 100 shown in FIG. 11 is designed by scan design. The LSI 200 shown in FIG. 13 is basically the same as the LSI 100 shown in FIG. 11, and the same reference numerals are given to the same components, but the flip-flop 2 connected in series instead of the flip-flop 13 in the LSI 100.
3 is used, and the input side of the shift flip-flop 23 is SI (scan-in) via the input buffer 1.
The terminal is connected to the output side, and the SO (scan out) terminal is connected to the output side through the output buffer.

The scan design is a design method for facilitating the creation of a test pattern by arranging the memory elements inside the sequential circuit so that the memory elements can be easily controlled and observed from the outside of the circuit. It is configured as a shift register, and the test pattern is easily created by reading and writing the test pattern through this scan path (shift path) during the DC test.

However, for example, in this LSI 200, the minimum required test pattern is one pattern, and since data is serially input from the SI terminal to the scan path, a pattern for DC test is provided in the ten flip-flops 23. It takes 10 cycles for one state test to set. A large-scale circuit may require tens of thousands of cycles for one state test, which does not reduce the test time. Therefore, when the scan path design is used, the test pattern creation time is shortened, but it takes time in the test stage.
That is, there is a problem that a test of a mass-produced LSI requires a long time and the cost is increased.

[0015]

As described above,
It takes a long time in the DC test of the LSI using the normal input / output buffer.

The present invention has been made to solve the above problems, and it is possible to realize a reduction in the number of test pattern inputs for performing a DC test and a reduction in test time by reducing the number of test patterns. Has an aim.

[0017]

A semiconductor integrated circuit according to a first aspect of the present invention is an internal circuit having a logic circuit,
A semiconductor integrated circuit comprising: at least one input means for applying an input signal to the internal circuit; and at least one output means for outputting an output signal from the internal circuit,
The output means is connected to a DC test facilitation circuit that outputs a signal for performing a DC test of the output means, and the DC test facilitation circuit receives a control signal provided without passing through the internal circuit. , Is connected to a DC test control circuit for supplying a test signal for DC test to the DC test facilitation circuit.

According to a second aspect of the present invention, there is provided a DC test facilitation circuit for use in a semiconductor integrated circuit according to the first aspect.
A C test facilitation circuit, which receives first and second test signals as the test signal and outputs the first test signal when the second test signal is at a first potential level. And outputting the output signal from the internal circuit to the output means when the second test signal is at the second potential level.

According to a third aspect of the present invention, in the DC test facilitation circuit, the DC test facilitation circuit includes first and second transmission gates and an inverter, and the first test signal is: The second test signal is applied to the input terminal of the second transmission gate, and the second test signal is supplied to the P-channel transistor side control electrode of the first transmission gate, the N-channel transistor side control electrode of the second transmission gate, and Via the inverter, applied to control electrodes on the N-channel transistor side and the P-channel transistor side of the first and second transmission gates, respectively, and the output signal is applied to an input terminal of the first transmission gate, The first and second transmission games The output terminal is connected to said output means in common.

The DC test facilitation circuit according to claim 4 is:
The DC test facilitation circuit used in the semiconductor integrated circuit according to claim 1, wherein said output means of said semiconductor integrated circuit is a tri-state buffer to which an output control signal for controlling an output signal is given from said internal circuit. When the DC test facilitation circuit receives the first and second test signals as the test signal and the second test signal is at the first potential level, the DC test facilitation circuit outputs the first test signal. When the first test signal is applied to the tri-state buffer and the first test signal is at the first potential level and the second test signal is at the second potential level, the tri-state buffer is kept in a high impedance state,
When the first and second test signals are both at the second potential level and the output control signal is at the second potential level, the tristate buffer outputs the output signal from the internal circuit. Give to.

The DC test facilitation circuit according to claim 5 is
A first to a fourth transmission gate, first and second inverters, and a NOR gate, wherein the output signal is provided to an input terminal of the first transmission gate, and the output control signal is The first test signal is supplied to the input terminal of a third transmission gate, the first test signal is supplied to the input terminal of the second transmission gate, and the second test signal is supplied to the fourth terminal via the first inverter. And an input terminal of the transmission gate of the NOR gate, and the first and second test signals are applied to the input terminal of the NOR gate.
The output signal of the NOR gate is supplied to the control electrodes on the N-channel transistor side and the P-channel transistor side of the first and second transmission gates, and the third signal.
And a control electrode on the side of the N-channel transistor and the side of the P-channel transistor of the fourth transmission gate, respectively, and via the second inverter, a control electrode on the side of the P-channel transistor of the first transmission gate, The control electrodes on the N-channel transistor side of the fourth transmission gate, the control electrodes on the N-channel transistor side and the P-channel transistor side of the second and third transmission gates, respectively, are applied to the first and second transmission gates, respectively. The output terminals of the gates are commonly connected to the input terminal of the tri-state buffer, and the output terminals of the third and fourth transmission gates are commonly connected to the output control terminal of the tri-state buffer.

According to a sixth aspect of the present invention, there is provided a DC test control circuit for use in the semiconductor integrated circuit according to the first aspect, wherein the control signal includes a first control signal and a clock signal. Receiving a control signal, outputting first and second test signals as the test signal. When the first control signal is at the second potential level, the first control signal is independent of the second control signal, The first and second test signals are maintained at a second potential level, and when the first control signal is at the first potential level, the signal generated by the latch of the second control signal is the first potential level. Output as the first and second test signals.

A DC test control circuit according to claim 7 comprises first and second latch means having a reset terminal, the input terminal of said first latch means being connected to its inverting output terminal, The inverting output terminal of the first latch means is connected to one input terminal of the XOR gate, and one input terminal of the XOR gate is connected to the inverting output terminal of the second latch means, and The output terminal is connected to the input terminal of the second latch means,
The first control signal is applied to respective reset terminals of the first and second latch means, and the second control signal is applied to timing signal terminals of the first and second latch means. , The first and second test signals are provided from the respective output terminals of the first and second latch means.

[0024]

According to the semiconductor integrated circuit of the first aspect of the present invention, the DC test control circuit receives the control signal and applies the test signal to the DC test facilitation circuit, and the DC test facilitation circuit outputs the DC of the output means. Since the signal for the test is output, the DC test of the output means is performed based on the control signal provided without passing through the internal circuit.

According to a second aspect of the DC test facilitation circuit of the present invention, the first and second test signals are received, and the first test signal is supplied when the second test signal is at the first potential level. When the second test signal is applied to the output means and the second test signal is at the second potential level, the output signal from the internal circuit is applied to the output means, so that the second test signal is applied to the first potential. By setting the level, the DC test of the output means can be performed by the first test signal.

According to the DC test facilitation circuit of the third aspect of the present invention, the output signal from the internal circuit is given to the output means by turning on the first transmission gate, and the second transmission is provided. Gate is ON
In this state, the first test signal is given to the output means, and the DC test of the output means can be performed by the first test signal.

According to the DC test facilitation circuit of the fourth aspect of the present invention, when the first and second test signals are received and the second test signal is at the first potential level, the first test signal is generated. When the first test signal is at the first potential level and the second test signal is at the second potential level, the output of the tri-state buffer is in the high impedance state. When both the first and second test signals are at the second potential level and the output control signal is at the second potential level, the output signal from the internal circuit is given to the tristate buffer. The first test signal is set to the first potential level, the second test signal is set to the second potential level, and then the second test signal is set to the first potential level, whereby the tristate buffer is set. D output means constituted by §
C test can be performed.

According to the DC test facilitation circuit of the fifth aspect of the present invention, the output signal from the internal circuit is given to the input terminal of the tri-state buffer by turning on the first transmission gate, When the second transmission gate is turned on, the first test signal is given to the input terminal of the tri-state buffer, and when the fourth transmission gate is turned on, the output of the tri-state buffer becomes high impedance. Therefore, the DC test of the output means composed of the tri-state buffer can be performed.

According to the sixth aspect of the DC test control circuit of the present invention, the first control signal and the second control signal which is the clock signal are received, and the first control signal is set to the second potential level. The first and second test signals are maintained at the second potential level regardless of the second control signal, and the second control signal is maintained at the second potential level when the first control signal is at the first potential level. Since the signal generated by the latch of the control signal is output as the first and second test signals, the DC test facilitation circuit can be subjected to the DC test by setting the first control signal to the first potential level. First and second test signals for performing can be provided.

According to the DC test control circuit of the seventh aspect of the present invention, the first and second control signals are generated by the first control signal.
Since the second control signal is latched in the first and second latch means and is output as the first and second test signals by releasing the reset state of the latch means of the DC test facilitation circuit, First and second test signals for performing a DC test can be obtained.

[0031]

【Example】

<First Embodiment> FIG. 1 shows the configuration of a semiconductor integrated circuit for facilitating a DC test as a first embodiment of the present invention. In FIG. 1, eight input buffers 1 are connected to an internal circuit 18, and the output of the internal circuit 18 is a DC test facilitating circuit. An output buffer DC test facilitating circuit 5 and a tristate output buffer DC test are provided. Facilitation circuit 6, bidirectional buffer DC test facilitation circuit 6a
It is connected to the. The output buffer DC test facilitation circuit 5, the tri-state output buffer DC test facilitation circuit 6, and the bidirectional buffer DC test facilitation circuit 6 a are connected to the DC test control circuit 7. Here, the DC test control circuit 7 is connected to the clock input pin CLK and the reset input pin RST, and the clock input pin CLK is also connected to the internal circuit 8.

DC test facilitation circuit 5 for output buffer,
The output side of the DC test facilitation circuit 6 for the tri-state output buffer and the DC test facilitation circuit 6a for the bidirectional buffer comprises an output buffer 2, a tri-state output buffer 3, a tri-state output buffer 41 and a buffer 42, respectively. The bidirectional buffer 4 is connected, the output buffer 2 is connected to the LSI external output terminal 10, the tristate output buffer is connected to the LSI external output terminal 11, and the bidirectional buffer is connected to the LSI external bidirectional terminal. ing.

Here, the internal circuit 8 is a circuit composed of the combinational circuits 14a, 14b, 14c and the flip-flop 13 in the conventional LSI 100 described with reference to FIG. 11, for example, and its logical operation is not taken into consideration. It means that the shape is irregular.

The semiconductor integrated circuit having the above-mentioned structure is driven by the clock signal and the reset signal supplied from the clock input pin CLK and the reset input pin RST.
The C test control circuit 7 generates a test signal, the output buffer DC test facilitation circuit 5, the tri-state output buffer DC test facilitation circuit 6, and the bidirectional buffer DC.
The test facilitation circuit 6a receives the test signal and gives a test pattern to the output buffer 2, the tri-state output buffer 3, and the bidirectional buffer 4, respectively.

Therefore, according to the semiconductor integrated circuit of the present invention, the test pattern is applied without the intermediary of the internal circuit 8, and compared with the case where the test pattern is applied via the internal circuit 8, the DC test is performed. The number of times of inputting the test pattern for performing is reduced, and the test time can be reduced.

<Second Embodiment> FIG. 2 shows a second embodiment of the present invention.
The configuration of the DC test facilitation output buffer 15 will be shown as an example. In FIG. 2A, an input terminal A and test terminals T1 and T2 are provided on the input side of the DC test facilitation output buffer 15, and an output terminal PA is provided on the output side.
D is provided. As shown in FIG. 2B, the DC test facilitation output buffer 15 has a configuration in which an output buffer DC test facilitation circuit 5 is added to the conventional output buffer 2, and the output buffer DC test facilitation circuit is provided. 5
Is provided with an input terminal A and test terminals T1 and T2, the output thereof is given to the tristate output buffer 3, and the output terminal PAD is provided on the output side of the tristate output buffer 3.

Next, the configuration of the output buffer DC test facilitation circuit 5 will be described with reference to FIG. In FIG. 3, the gate electrodes on the N-channel transistor side and the P-channel transistor side of the transmission gates 18 and 18a configured by connecting the P-channel transistor and the N-channel transistor in parallel are connected, and the transmission gates 18 and 18a are connected. The input terminal A and the test terminal T1 are connected to the respective input terminals of, and the gate electrodes on the N-channel transistor side and the P-channel transistor side of the transmission gates 18 and 18a are the inverter 1
It is connected to the test terminal T2 via 9. The test terminal T2 is connected to P of the transmission gate 18.
The gate electrode on the channel transistor side and the gate electrode on the N channel transistor side of the transmission gate 18a are also connected. The output terminals of the transmission gates 18 and 18a are common to the output buffer 2
Is connected to the input terminal of

Next, the operation of the output buffer DC test facilitation circuit 5 will be described with reference to FIG. FIG. 4 is a timing chart showing the operation of the output buffer DC test facilitation circuit 5, which is divided by a vertical line for each cycle. "X" shown in the figure represents Don't care,
"Z" represents a high impedance state. The high and low of the potential level are displayed as High and Low, and are shown on the right side of the timing chart. The same applies to the timing charts shown in the other figures.

In FIG. 4, during the period when the signal level of the test terminal T2 is Low, the signal input from the input terminal A is output from the output terminal PAD regardless of the signal from the test terminal T1. On the other hand, during the period when the signal level of the test terminal T2 is High, it is shown that the signal input from the test terminal T1 is output from the output terminal PAD regardless of the signal from the input terminal A. There is. That is, the output buffer DC test facilitation circuit 5
Is a circuit that can selectively output only one of the signal from the input terminal A or the test terminal T1 from the output buffer 2 by the signal from the test terminal T2.

By using the output buffer DC test facilitating circuit 5 as described above, the test terminal T is used during the DC test of the output buffer 2 (hereinafter referred to as the test mode).
By keeping the signal level of 2 high and alternately applying the high and low signals to the test terminal T1 every one cycle, the high and low signals are alternately obtained at the output terminal PAD during the two cycles. Become.

When the DC test of the output buffer 2 is not carried out (hereinafter referred to as system operation), the signal level of the test terminal T2 is kept at Low so that the input terminal A
Can be output to the output terminal PAD.

<Third Embodiment> FIG. 5 shows a third embodiment of the present invention.
The configuration of the DC test facilitation tri-state output buffer 16 will be shown as an example. In FIG. 5A, DC
An input terminal A and test terminals T1 and T2 are provided on the input side of the test facilitating tristate output buffer 16, and an output terminal PAD is provided on the output side. An output control terminal C is provided separately from these.

As shown in FIG. 5B, the DC test facilitation tristate output buffer 16 has a structure in which a DC test facilitation circuit 6 for tristate output buffer is added to the conventional tristate output buffer 3. , The output buffer DC test facilitation circuit 5 is provided with an input terminal A, an output control terminal C, and test terminals T1 and T2, the output of which is given to the output buffer 2 and the output terminal PAD is provided on the output side of the output buffer 2. Is provided.

Next, the structure of the DC test facilitation circuit 6 for the tri-state output buffer will be described with reference to FIG. In FIG. 6, gate electrodes on the N-channel transistor side and the P-channel transistor side of transmission gates 18 and 18a configured by connecting a P-channel transistor and an N-channel transistor in parallel are commonly connected, and the transmission is Gate electrodes on the N-channel transistor side and the gate electrodes on the P-channel transistor side of the gates 18b and 18c are commonly connected. Further, an input terminal A, a test terminal T1, an output control terminal C, and an output terminal of the inverter 19 are connected to the respective input terminals of the transmission gates 18, 18a, 18b, 18c. Since the input terminal of the inverter 19 is connected to the test terminal T2, the inverted signal of the test terminal T2 is given to the input terminal of the transmission gate 18c.

The test terminals T1 and T2 are also connected to the NOR gate 20, and the output terminals thereof are the gate electrodes of the transmission gates 18 and 18a on the N-channel transistor side and the P-channel transistor side, respectively, and the transmission gates 18b and 18c.
Of the transmission gate 1 connected to the respective gate electrodes of the N-channel transistor side and the P-channel transistor side of the transmission gate 1 via the inverter 19a.
It is connected to the connection point between 8a and 18b, and the P-channel transistor side gate electrode of the transmission gate 18 and the N-channel transistor side gate electrode of the transmission gate 18c.

The output terminals of transmission gates 18 and 18a are commonly connected to the input terminal of tristate output buffer 3, and the output terminals of transmission gates 18b and 18c are commonly connected to the output control terminal of tristate output buffer 3. Has been done.

Next, the operation of the DC test facilitation circuit 6 for the tri-state output buffer will be described with reference to FIG. FIG. 7 is a timing chart showing the operation of the DC test facilitation circuit 6 for the tri-state output buffer.
Each cycle is divided by a vertical line.

In FIG. 7, test terminals T1 and T
While the two signals are both low and the signal of the output control terminal C is high, the output terminal PAD is in the high impedance state regardless of the signal of the input terminal A. However, when the signal of the output control terminal C becomes Low, the signal of the input terminal A is output to the output terminal PAD.

The signal at the test terminal T1 is High.
When the signal at the test terminal T2 is low, the output terminal PAD is in a high impedance state regardless of the signals at the input terminal A and the output control terminal C.

Further, the signal at the test terminal T2 is High.
If h, the signal at the test terminal T1 is the output terminal P regardless of the signals at the input terminal A and the output control terminal C.
It will be output to AD.

That is, the DC test facilitation circuit 6 for the tri-state output buffer has the test terminals T1 and T1.
It is a circuit that can selectively output only one of the signals from the input terminal A or the test terminal T1 from the tri-state output buffer 3 by combining the two signals.

By using the DC test facilitation circuit 6 for the tri-state output buffer, the signal level of the test terminal T2 is kept high and the test terminal T1 is maintained in the test mode of the tri-state output buffer 3.
By alternately applying a High signal and a Low signal to the output terminal for one cycle, a High signal and a Low signal are alternately obtained at the output terminal PAD for two cycles, and the signal level of the test terminal T2 is kept at the Low level for the test. 1 signal at terminal T1
By setting to High during the cycle, the output terminal PAD becomes 1
Since the high impedance can be maintained during the cycle, the DC test of the tri-state output buffer 3 can be performed in three cycles.

During the system operation of the tri-state output buffer 3, the signals at the test terminals T1 and T2 are both set to Low and the signal at the output control terminal C is kept at Low, so that the signal at the input terminal A is set at the output terminal PAD. Can be output to.

<Fourth Embodiment> FIG. 8 shows a fourth embodiment of the present invention.
As an embodiment of the DC test facilitation bidirectional buffer 17
Shows the configuration of. In FIG. 8A, an input terminal A, test terminals T1 and T2 are provided on the input side of the DC test facilitation bidirectional buffer 17, and an output terminal PAD is provided on the output side. An output control terminal C is provided separately from these.

As shown in FIG. 8B, the DC test facilitation bidirectional buffer 17 includes a conventional bidirectional buffer 4 including a tri-state output buffer 41 and a buffer 42 for facilitating the DC test for the bidirectional buffer. In the configuration in which the circuit 6a is added, the DC test facilitation circuit 6a for the bidirectional buffer is provided with the input terminal A, the output control terminal C, and the test terminals T1 and T2, and the output thereof is given to the tristate output buffer 41. The output terminal PAD is provided on the output side of the tri-state output buffer 41. The output terminal PAD is connected to the output terminal PAD.
A buffer 42 for a signal input using the
Are connected, but since they have little relation to the present invention, description thereof will be omitted hereinafter.

The bidirectional buffer DC test facilitation circuit 6a has the same structure as the tristate output buffer DC test facilitation circuit 6 described with reference to FIG. 6 in the third embodiment. , Figures and description are omitted. Therefore, the timing chart showing the operation is also shown in FIG.
Since it is the same as the timing chart shown in FIG.

By using such a bidirectional buffer DC test facilitating circuit 6a, when the bidirectional buffer 3 is in the test mode, the signal level of the test terminal T2 is set to Hi.
GH, and high and low to the test terminal T1
By alternately applying the signal of 1 cycle for each output terminal PA
High and Low signals are alternately obtained in D during two cycles, the signal level of the test terminal T2 is kept Low, and the signal of the test terminal T1 is set to High for one cycle, so that the output terminal Since the PAD can be kept in high impedance for one cycle, the DC test of the bidirectional buffer 4 can be performed in three cycles.

During the system operation of the bidirectional buffer 4, the signals at the test terminals T1 and T2 are both set to Low.
Then, by keeping the signal of the output control terminal C low, the signal of the input terminal A can be output to the output terminal PAD.

<Fifth Embodiment> FIG. 9 shows a fifth embodiment of the present invention.
The configuration of the DC test control circuit 7 will be shown as an example.
As shown in FIG. 9, the DC test control circuit 7 is a 2-bit counter circuit including flip-flops 22 and 22a with reset terminals and an XOR gate 21.
In FIG. 9, a flip-flop 22 with a reset terminal
The data input terminal D is connected to the inverting output terminal Q ′, and the inverting output terminal Q ′ is connected to one of the input terminals of the XOR gate 21. The output terminal of the XOR gate 21 is the data input terminal D of the flip-flop 22a with the reset terminal.
And the other input terminal of the XOR gate 21 is the inverting output terminal Q ′ of the flip-flop 22a with the reset terminal.
It is connected to the. The output terminals Q of the flip-flops 22 and 22a with reset terminals are connected to the test terminals T1 and T2, respectively.

Here, the clock input pin CLK and the reset input pin RST are connected to the respective timing signal input terminals T and reset terminals R of the flip-flops 22 and 22a with reset terminals.

Next, the DC test control circuit 7 will be described with reference to FIG.
The operation of will be described. FIG. 10 is a timing chart showing the operation of the DC test control circuit 7, which is divided by a vertical line for each cycle.

In FIG. 10, while the signal on the reset input pin RST is Low, the flip-flops 22 and 22a with reset terminals are in the reset state, and the test terminal T is irrespective of the signal on the clock input pin CLK.
The signals of 1 and T2 become Low.

On the other hand, the signal at the reset input pin RST is H level.
When it goes high, the signal at the test terminal T1 changes to Hi at the rising timing of the signal at the clock input pin CLK.
It becomes gh, and becomes Low at the next rising timing of the signal of the clock input pin CLK. This is repeated while the signal at the reset input pin RST is High. The signal at the test terminal T2 becomes High at the falling timing of the signal at the test terminal T1 and becomes Low at the next rising timing of the signal at the test terminal T1. This is repeated while the signal at the reset input pin RST is High.

That is, the DC test control circuit 7 can output a periodic signal to the test terminals T1 and T2 by keeping the signal of the reset input pin RST High and supplying the clock signal to the clock input pin CLK. Is.

By using the DC test control circuit 7 as described above, in the test mode, the signal of the reset input pin RST of the DC test control circuit 7 is kept high and the clock signal is supplied to the clock input pin CLK.
DC for output buffer from test terminals T1 and T2
Test facilitation circuit 5, D for tri-state output buffer
C test facilitation circuit 6 and respective test terminals T1 and T2 of the bidirectional buffer DC test facilitation circuit 6a
To the DC test facilitation output buffer 15, the DC test facilitation tri-state output buffer 16, and the DC test facilitation bidirectional buffer 17 by applying a cyclic signal to the test terminals T1 and T2. A desired signal can be output to the terminal PAD.

Further, during system operation, the signal at the reset input pin RST is set to Low, so that the DC test facilitation output buffer 15, the DC test facilitation tri-state output buffer 16, and the DC test facilitation bidirectional buffer 17 are respectively performed. Input terminal A signal is output terminal PA
Can be output to D.

Incidentally, without using the DC test control circuit 7,
By individually providing a test pattern to each test terminal of the output buffer DC test facilitation circuit 5, the tri-state output buffer DC test facilitation circuit 6, and the bidirectional buffer DC test facilitation circuit 6a,
Although it is possible to perform a DC test, an overall DC test control circuit 7 can be used to provide a test pattern to enable an efficient DC test even in a semiconductor integrated circuit having a large number of output means.

[0068]

According to the semiconductor integrated circuit of the first aspect of the present invention, the DC test control circuit receives the control signal and applies the test signal to the DC test facilitation circuit, and the DC test facilitation circuit outputs the output means. By outputting the signal for the DC test of, the DC test of the output means is performed based on the control signal given without passing through the internal circuit. Therefore, compared with the case where the DC test is performed through the internal circuit, The number of signal inputs for the DC test is reduced, and the test time can be reduced.

According to the DC test facilitation circuit of the second aspect of the present invention, by setting the second test signal to the first potential level, the D of the output means is driven by the first test signal.
Since the C test can be performed, the DC test of the output means can be easily performed in a short time.

According to the DC test facilitation circuit of the third aspect of the present invention, the DC test of the output means can be performed in a short time.
A practical DC test facilitation circuit for ease of implementation is obtained.

According to the fourth aspect of the DC test facilitation circuit of the present invention, the first test signal is set to the first potential level, the second test signal is set to the second potential level, and then, By setting the second test signal to the first potential level, the D of the output means constituted by the tri-state buffer is provided.
The C test can be easily performed in a short time.

According to the DC test facilitation circuit of the fifth aspect of the present invention, the practical DC test facilitation for easily performing the DC test of the output means constituted by the tri-state buffer in a short time. The circuit is obtained.

According to the sixth aspect of the DC test control circuit of the present invention, the first control signal is set to the first potential level to make the DC test facilitation circuit perform the DC test. Since the second test signal can be given, the control of the operation of the DC test facilitation circuit can be centralized, and the DC test of the semiconductor integrated circuit having a plurality of output means can be efficiently performed. it can.

According to the DC test control circuit of the seventh aspect of the present invention, the DC test facilitation circuit is supplied with the first and second test signals for performing the DC test, and the DC test facilitation circuit operates. It is possible to obtain a practical DC test control circuit capable of integrally controlling the control of.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit that is a first embodiment according to the present invention.

FIG. 2 is a diagram showing a configuration of a DC test facilitation circuit that is a second embodiment according to the present invention.

FIG. 3 is a circuit diagram of a DC test facilitation circuit that is a second embodiment according to the present invention.

FIG. 4 is a timing chart showing the operation of the DC test facilitation circuit of the second embodiment according to the present invention.

FIG. 5 is a diagram showing a configuration of a DC test facilitation circuit that is a third embodiment according to the present invention.

FIG. 6 is a circuit diagram of a DC test facilitation circuit that is a third embodiment according to the present invention.

FIG. 7 is a timing chart showing the operation of the DC test facilitation circuit of the third embodiment according to the present invention.

FIG. 8 is a diagram showing a configuration of a DC test facilitation circuit that is a fourth embodiment according to the present invention.

FIG. 9 is a circuit diagram of a DC test control circuit according to a fifth embodiment of the present invention.

FIG. 10 is a timing chart showing the operation of the DC test control circuit according to the fifth embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a conventional semiconductor integrated circuit.

FIG. 12 is a diagram showing a configuration of a dynamic load circuit in a tester for performing a DC test on a semiconductor integrated circuit.

FIG. 13 is a diagram showing a configuration of a conventional semiconductor integrated circuit designed by scan design.

[Explanation of symbols]

5 Output buffer DC test facilitation circuit, 6 Tri-state output buffer DC test facilitation circuit, 6a
DC test facilitation circuit for bidirectional buffer, 7 DC test control circuit, 8 internal circuit, 15 DC test facilitation output buffer, 16 DC test facilitation tri-state output buffer, 17 DC test facilitation bidirectional buffer, 1
8, 18a, 18b, 18c tri-state buffer, 19, 19a inverter, 20 NOR gate,
21 XOR gate, 22 Flip-flop with reset terminal, A input terminal, PAD output terminal, T1, T
2 Test terminal, CLK clock input pin, RST
Reset input pin.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/66 F 7514-4M

Claims (7)

[Claims] 1. A semiconductor integrated circuit comprising an internal circuit having a logic circuit, at least one input means for applying an input signal to the internal circuit, and at least one output means for outputting an output signal from the internal circuit. In the above, the output means is connected to a DC test facilitation circuit that outputs a signal for performing a DC test of the output means, and the DC test facilitation circuit outputs a control signal provided without passing through the internal circuit. A semiconductor integrated circuit, wherein the semiconductor integrated circuit is connected to a DC test control circuit for receiving a test signal for DC test to the DC test facilitation circuit. 2. The DC test facilitating circuit for a semiconductor integrated circuit according to claim 1, wherein the first and second test signals are received as the test signal, and the second test signal has a first potential level. The first test signal is applied to the output means, and the second test signal is applied to the second potential level, the output signal from the internal circuit is applied to the output means. DC test facilitation circuit characterized by: 3. The DC test facilitation circuit comprises first and second transmission gates and an inverter, wherein the first test signal is applied to an input terminal of the second transmission gate, The second test signal is passed through the control electrode on the P-channel transistor side of the first transmission gate, the control electrode on the N-channel transistor side of the second transmission gate, and the inverter to the first and second transmissions. Control signals on the N-channel transistor side and the P-channel transistor side of the gate, respectively, the output signal is applied to an input terminal of the first transmission gate, and output terminals of the first and second transmission gates are: Commonly connected to the output means DC test circuit according to claim 2, wherein Rukoto. 4. The DC test facilitation circuit for a semiconductor integrated circuit according to claim 1, wherein said output means of said semiconductor integrated circuit is provided with an output control signal for controlling an output signal from said internal circuit. When the DC test facilitation circuit receives first and second test signals as the test signal and the second test signal is at a first potential level, the first test signal is formed of a tri-state buffer. Is applied to the tri-state buffer, and when the first test signal is at the first potential level and the second test signal is at the second potential level, the tri-state buffer is set to high impedance. State, the first and second test signals are both at the second potential level, and the output control signal is at the second potential level. Huang, DC test circuit, characterized in that providing said output signal from said internal circuit to the tri-state buffer. 5. The DC test facilitation circuit includes first to fourth transmission gates and first and second transmission gates.
An inverter and a NOR gate, the output signal is applied to an input terminal of the first transmission gate, the output control signal is applied to an input terminal of the third transmission gate, and Is applied to the input terminal of the second transmission gate, the second test signal is applied to the input terminal of the fourth transmission gate via the first inverter, and And a second test signal is applied to an input terminal of the NOR gate, and an output signal of the NOR gate is supplied to the control electrodes on the N-channel transistor side and the P-channel transistor side of the first and second transmission gates and the first and second transmission gates. Three
And a control electrode on the side of the N-channel transistor and the side of the P-channel transistor of the fourth transmission gate, respectively, and via the second inverter, a control electrode on the side of the P-channel transistor of the first transmission gate, The control electrode on the N-channel transistor side of the fourth transmission gate, the control electrode on the N-channel transistor side and the control electrode on the P-channel transistor side of the second and third transmission gates, respectively, and the first and second transmissions. The output terminals of the gates are commonly connected to the input terminal of the tri-state buffer, and the output terminals of the third and fourth transmission gates are commonly connected to the output control terminal of the tri-state buffer. DC test circuit according to claim 4, wherein the door. 6. A DC test control circuit for a semiconductor integrated circuit according to claim 1, wherein the control signal receives a first control signal and a second control signal which is a clock signal, and the test signal is used as the test signal. Outputting the first and second test signals, and when the first control signal is at the second potential level,
Irrespective of the second control signal, the first and second test signals are kept at a second potential level, and when the first control signal is at a first potential level,
A DC test control circuit, which outputs a signal generated by a latch of the second control signal as the first and second test signals. 7. The DC test control circuit comprises first and second latch means having a reset terminal, wherein an input terminal of the first latch means is connected to its own inverting output terminal, The inverting output terminal of the latch means is connected to one input terminal of the XOR gate, one input terminal of the XOR gate is connected to the inverting output terminal of the second latch means, and the output terminal of the XOR gate Is connected to an input terminal of the second latch means, the first control signal is given to respective reset terminals of the first and second latch means, and the second control signal is The timing signal terminals of the first and second latch means are provided, and the first and second test signals are provided from the respective output terminals of the first and second latch means. DC test control circuit according to claim 6, wherein.