JPH088419A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH088419A
JPH088419A JP16263594A JP16263594A JPH088419A JP H088419 A JPH088419 A JP H088419A JP 16263594 A JP16263594 A JP 16263594A JP 16263594 A JP16263594 A JP 16263594A JP H088419 A JPH088419 A JP H088419A
Authority
JP
Japan
Prior art keywords
semiconductor layer
semiconductor
layer
conductivity type
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16263594A
Other languages
Japanese (ja)
Inventor
Atsuya Uekawa
淳哉 植川
Takeshi Yamamoto
武 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansha Electric Manufacturing Co Ltd
Original Assignee
Sansha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansha Electric Manufacturing Co Ltd filed Critical Sansha Electric Manufacturing Co Ltd
Priority to JP16263594A priority Critical patent/JPH088419A/en
Publication of JPH088419A publication Critical patent/JPH088419A/en
Pending legal-status Critical Current

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  • Thyristors (AREA)

Abstract

(57)【要約】 【目的】 降伏時の耐電圧を向上させ許容電流を向上す
る半導体装置を提供する。 【構成】 基板ウェーハとなる第1の半導体層1の表面
からカソードを形成する第4の半導体層4とウェーハを
分離する第2の半導体層2との間に第1の半導体層と同
じ導電型で第1の半導体層の不純物濃度より高い不純物
濃度の第6の半導体層13を設けた。
(57) [Abstract] [Purpose] To provide a semiconductor device that improves withstand voltage during breakdown and improves allowable current. The same conductivity type as that of the first semiconductor layer is provided between a fourth semiconductor layer 4 forming a cathode and a second semiconductor layer 2 separating the wafer from the surface of the first semiconductor layer 1 serving as a substrate wafer. Thus, the sixth semiconductor layer 13 having an impurity concentration higher than that of the first semiconductor layer was provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、サイリスタ,トライア
ック等の半導体装置に関するものであり、特に過電圧耐
量の高い半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a thyristor and a triac, and more particularly to a semiconductor device having high withstand voltage.

【0002】[0002]

【従来の技術】サイリスタ,トライアック等の半導体装
置には図6に示すものが知られている。同図(a)はこ
の種の半導体装置の断面図で、同図(b)は電極と酸化
膜を除いた平面を模式的に示した平面図である。1は例
えばN型の第1の半導体層であり、2は第1の半導体層
1の両表面間を選択的に貫通する様に設けた例えばP型
の第2の半導体層である。この第2の半導体層2により
分離拡散された第1の半導体層1の一方の面を全面に、
また他方の面を選択的に例えばP型の第3の半導体層3
と第4の半導体層4を形成する。第4の半導体層4内に
例えばN型の第5の半導体層5を形成し、第1の半導体
層1と第2の半導体層2,第1の半導体層1と第4の半
導体層4,第4の半導体層4と第5の半導体層5のそれ
ぞれ接合面を含めて酸化膜6を形成し、酸化膜6の形成
後第5の半導体層5にカソード電極7,第3の半導体層
3にアノード電極8,第4の半導体層4にゲート電極9
を形成し、半導体装置(サイリスタ)を形成する。
2. Description of the Related Art Semiconductor devices such as thyristors and triacs are known as shown in FIG. FIG. 1A is a sectional view of this type of semiconductor device, and FIG. 1B is a plan view schematically showing a plane excluding electrodes and an oxide film. Reference numeral 1 is, for example, an N-type first semiconductor layer, and 2 is, for example, a P-type second semiconductor layer provided so as to selectively penetrate between both surfaces of the first semiconductor layer 1. One surface of the first semiconductor layer 1 separated and diffused by the second semiconductor layer 2 is entirely covered,
Further, the other surface is selectively formed, for example, in the P-type third semiconductor layer 3
And the fourth semiconductor layer 4 is formed. For example, an N-type fifth semiconductor layer 5 is formed in the fourth semiconductor layer 4, and the first semiconductor layer 1 and the second semiconductor layer 2, the first semiconductor layer 1 and the fourth semiconductor layer 4, An oxide film 6 is formed including the bonding surfaces of the fourth semiconductor layer 4 and the fifth semiconductor layer 5, and after the oxide film 6 is formed, the cathode electrode 7 and the third semiconductor layer 3 are formed on the fifth semiconductor layer 5. On the anode electrode 8 and the fourth semiconductor layer 4 on the gate electrode 9
To form a semiconductor device (thyristor).

【0003】今アノード電極8に正,カソード電極7に
負の電圧を印加すると、第1半導体層1と第4の半導体
層4の接合J2の両側に空乏層が生じる。一般的に第4
の半導体層4の濃度が第1の半導体層1の濃度より高く
設計されるため、空乏層のほとんどが第1の半導体層1
側に生じる。そして印加する電圧を増加させると空乏層
は第1の半導体層1と第3の半導体層3との接合J1及
び第1の半導体層1と第2の半導体層2の接合J1方向
に拡がって行くとともに、接合J2の電界強度が高くな
る。この状態では半導体装置はしゃ断特性を示してい
る。このとき、ゲート電極9に正,カソード電極7に負
の電圧を印加すると、ゲート電極9,第4の半導体層
4,第5の半導体層5,カソード電極7にゲート電流が
流れ、第4の半導体層4に注入された電子がアノード電
極8方向に引かれ、アノード電極8,第3の半導体層
3,第1の半導体層1,第4の半導体層4,第5の半導
体層5,カソード電極7に電流が流れ、半導体装置は導
通状態となる。
When a positive voltage is applied to the anode electrode 8 and a negative voltage is applied to the cathode electrode 7, depletion layers are formed on both sides of the junction J2 between the first semiconductor layer 1 and the fourth semiconductor layer 4. Generally fourth
Since the concentration of the semiconductor layer 4 is designed to be higher than that of the first semiconductor layer 1, most of the depletion layer is formed in the first semiconductor layer 1.
Occur on the side. When the applied voltage is increased, the depletion layer expands in the direction of the junction J1 between the first semiconductor layer 1 and the third semiconductor layer 3 and the junction J1 between the first semiconductor layer 1 and the second semiconductor layer 2. At the same time, the electric field strength of the junction J2 increases. In this state, the semiconductor device exhibits a cutoff characteristic. At this time, when a positive voltage is applied to the gate electrode 9 and a negative voltage is applied to the cathode electrode 7, a gate current flows through the gate electrode 9, the fourth semiconductor layer 4, the fifth semiconductor layer 5, and the cathode electrode 7, and the fourth voltage is applied. The electrons injected into the semiconductor layer 4 are attracted toward the anode electrode 8, and the anode electrode 8, the third semiconductor layer 3, the first semiconductor layer 1, the fourth semiconductor layer 4, the fifth semiconductor layer 5, and the cathode are formed. A current flows through the electrode 7 and the semiconductor device becomes conductive.

【0004】また、ゲート電極9とカソード電極7との
間に電圧を印加せずにアノード電極8とカソード電極7
に印加する電圧を高くすると、印加する電圧に伴ない空
乏層は拡がり接合J2の電界強度はどんどん高くなる。
そして、空乏層が接合J1に達するか、接合J2の電界
強度がある電界に達したとき、アノード電極8からカソ
ード電極7に電流が流れ降伏現象を起こす。従って、半
導体装置の耐電圧は接合J1と接合J2との距離あるい
は接合J2の電界強度によって決定される。
Further, without applying a voltage between the gate electrode 9 and the cathode electrode 7, the anode electrode 8 and the cathode electrode 7
When the voltage applied to the junction is increased, the depletion layer expands with the applied voltage, and the electric field strength of the junction J2 becomes higher and higher.
When the depletion layer reaches the junction J1 or the electric field strength of the junction J2 reaches a certain electric field, a current flows from the anode electrode 8 to the cathode electrode 7 to cause a breakdown phenomenon. Therefore, the withstand voltage of the semiconductor device is determined by the distance between the junction J1 and the junction J2 or the electric field strength of the junction J2.

【0005】[0005]

【発明が解決しようとする課題】しかし、接合J1と接
合J2との距離で決定するように半導体装置の耐電圧を
設計した場合には、高温時の耐電圧が著しく低下し、高
温時の使用に問題があった。また、接合J2の電界強度
で半導体装置の耐電圧を設計した場合には、接合J2の
位置は熱処理によりばらつきが生じ、降伏現象が電界強
度の最も強い箇所で起こるため、半導体装置を降伏させ
ると局部的な降伏電流の集中により半導体装置が破損す
るという問題点があった。
However, when the withstand voltage of the semiconductor device is designed so as to be determined by the distance between the junction J1 and the junction J2, the withstand voltage at a high temperature is remarkably reduced, and the use at a high temperature is prevented. I had a problem with. Further, when the withstand voltage of the semiconductor device is designed by the electric field strength of the junction J2, the position of the junction J2 varies due to the heat treatment, and the breakdown phenomenon occurs at the place where the electric field strength is the strongest. There is a problem that the semiconductor device is damaged due to local concentration of breakdown current.

【0006】[0006]

【課題を解決するための手段】この発明は、上記の問題
点を解決するためになされたものであり、第1の導電型
の第1半導体層と、上記第1の半導体層の両表面間を選
択的に貫通する第2の導電型の第2の半導体層と、上記
第1の半導体層の片側の表面に設けられた上記第2の導
電型の第3の半導体層と、上記第3の半導体層と対向す
る表面に選択的に設けられた第2の導電型の第4の半導
体層と、上記第4の半導体層内に選択的に設けられた第
1の導電型の第5の半導体層とを有する半導体装置にお
いて、上記第1の半導体層の表面から上記第4の半導体
層と上記第2の半導体層との間に第1の導電型で上記第
1の半導体層の不純物濃度より高い不純物濃度の第6の
半導体層を設けたものである。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is provided between the first conductivity type first semiconductor layer and both surfaces of the first semiconductor layer. A second semiconductor layer of a second conductivity type that selectively penetrates the first semiconductor layer, a third semiconductor layer of the second conductivity type provided on one surface of the first semiconductor layer, and the third semiconductor layer. Second semiconductor layer of the second conductivity type selectively provided on the surface facing the semiconductor layer, and a fifth semiconductor layer of the first conductivity type selectively provided in the fourth semiconductor layer. In a semiconductor device having a semiconductor layer, an impurity concentration of the first semiconductor layer is of a first conductivity type between the surface of the first semiconductor layer and the fourth semiconductor layer and the second semiconductor layer. The sixth semiconductor layer having a higher impurity concentration is provided.

【0007】また、上記第4の半導体層の表面形状及び
上記第2の半導体層の表面形状に曲線部を有する場合、
上記第6の半導体層が上記曲線部に対向する曲線部を除
いた半導体層である。
When the surface shape of the fourth semiconductor layer and the surface shape of the second semiconductor layer have curved portions,
The sixth semiconductor layer is a semiconductor layer excluding a curved portion facing the curved portion.

【0008】また、上記第6の半導体層の表面に低抵抗
の配線層を設けたものである。
A wiring layer having a low resistance is provided on the surface of the sixth semiconductor layer.

【0009】[0009]

【作用】第1の導電型の第1の半導体層の両表面間を貫
通する第2の導電型の第2の半導体層が形成され、第1
の半導体層の片側の表面に上記第2の導電型の第3の半
導体層が形成され、第1の半導体層のもう片側の表面に
選択的に第2の導電型の第4の半導体層が設けられ、第
4の半導体層内に選択的に第1の導電型の第5の半導体
層が形成される。さらに第1の半導体層の表面から上記
第4の半導体層と第2の半導体層間に第1の導電型で第
1の半導体層の不純物濃度より高い不純物濃度の第6の
半導体層が設けられ、第3の半導体層に接続された電極
に正また第5の半導体層に接続された電極に負の電圧を
印加し電圧を上昇させると、空乏層が第1の半導体層と
第6の半導体層との境界部より拡がることができず、こ
の接合の表面近傍の電界が上昇し、ある値に達すると降
伏現象を起こす。
The second semiconductor layer of the second conductivity type is formed so as to penetrate between both surfaces of the first semiconductor layer of the first conductivity type.
The third semiconductor layer of the second conductivity type is formed on one surface of the semiconductor layer, and the fourth semiconductor layer of the second conductivity type is selectively formed on the other surface of the first semiconductor layer. A fifth semiconductor layer of the first conductivity type is selectively formed in the fourth semiconductor layer. Further, a sixth semiconductor layer of a first conductivity type and an impurity concentration higher than that of the first semiconductor layer is provided between the surface of the first semiconductor layer and the fourth semiconductor layer and the second semiconductor layer, When a positive voltage is applied to the electrode connected to the third semiconductor layer and a negative voltage is applied to the electrode connected to the fifth semiconductor layer to increase the voltage, the depletion layer becomes the first semiconductor layer and the sixth semiconductor layer. The electric field near the surface of this junction rises, and when it reaches a certain value, the yield phenomenon occurs.

【0010】また、第4の半導体層の表面形状が曲線を
有する場合、第6の半導体層の曲線部を除いて第6の半
導体層の曲線部に電界集中するのをさける。
When the surface shape of the fourth semiconductor layer has a curved line, the electric field is prevented from concentrating on the curved line portion of the sixth semiconductor layer except for the curved line portion of the sixth semiconductor layer.

【0011】また、第6の半導体層の表面に低抵抗の配
線層を設けることにより第6の半導体層13の表面方向
での電位ばらつきが小さくなる。
Further, by providing the low resistance wiring layer on the surface of the sixth semiconductor layer, the potential variation in the surface direction of the sixth semiconductor layer 13 is reduced.

【0012】[0012]

【実施例】本考案を実施例を示す図1に基づいて説明す
る。図1において、図6と同一符号のものは同じ機能の
ものを示す。図1が図6と異なる点は、第1の半導体層
1の他方の表面であって、第2の半導体層2と第4の半
導体層4との間に第1の半導体層と同導電型の第6の半
導体層13を設けた点にある。この第6の半導体層13
は第1の半導体層1の不純物濃度より高い不純物濃度で
形成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIG. In FIG. 1, the same reference numerals as those in FIG. 6 indicate the same functions. 1 is different from FIG. 6 in that it is the other surface of the first semiconductor layer 1 and has the same conductivity type as the first semiconductor layer between the second semiconductor layer 2 and the fourth semiconductor layer 4. The sixth semiconductor layer 13 is provided. This sixth semiconductor layer 13
Are formed with an impurity concentration higher than that of the first semiconductor layer 1.

【0013】今、アノード電極8に正,カソード電極7
に負の電圧を印加し印加電圧を上昇させると、空乏層は
接合J2から第3の半導体層3側の接合J1の方向と第
6の半導体層13の方向に拡がって行き、空乏層が第1
の半導体層1と第6の半導体層13との接合J4に達す
る。空乏層が接合J4に達した後は、第6の半導体層6
の濃度が第1の半導体層1の濃度より高いため接合J4
付近から拡がらず、以降は接合J4の表面近傍の電界強
度が上昇して行き、ある値に達すると降伏現象を起こ
す。
Now, the anode electrode 8 is positive and the cathode electrode 7 is
When a negative voltage is applied to the depletion layer to increase the applied voltage, the depletion layer spreads from the junction J2 in the direction of the junction J1 on the third semiconductor layer 3 side and in the direction of the sixth semiconductor layer 13, and the depletion layer becomes the first depletion layer. 1
To the junction J4 between the semiconductor layer 1 and the sixth semiconductor layer 13. After the depletion layer reaches the junction J4, the sixth semiconductor layer 6
Is higher than that of the first semiconductor layer 1, the junction J4
It does not spread from the vicinity, and thereafter the electric field strength near the surface of the junction J4 rises, and when it reaches a certain value, a breakdown phenomenon occurs.

【0014】そして、第6の半導体層13と接合J2と
の距離が降伏を支配しているため、降伏のばらつきを第
6の半導体層13のパターンニング精度によって考える
ことができ、パターンの精度を向上させることにより、
従来のスボット的な降伏に対して降伏を起す箇所が接合
線状のとなり(以下接合線状で起る降伏を線降伏とい
う)、そして、降伏時の許容電流が大きくなり、素子降
伏時にも破壊しにくい半導体装置を得ることができる。
Since the distance between the sixth semiconductor layer 13 and the junction J2 governs the breakdown, the variation in the breakdown can be considered by the patterning accuracy of the sixth semiconductor layer 13, and the pattern accuracy can be improved. By improving
In contrast to the conventional Svotte-like breakdown, the part that causes the breakdown becomes a junction line (hereinafter, the breakdown that occurs in the junction line is referred to as a line breakdown), and the allowable current at the time of breakdown becomes large, causing damage even at the time of device breakdown. A semiconductor device that is difficult to manufacture can be obtained.

【0015】図2ないし図5は他の実施例であり、それ
ぞれの図の(a)図は半導体装置のA−Aの断面図で、
(b)図は電極及び酸化膜を除いた平面を模式的に示し
た平面図である。図1に示す上記実施例では、第6の半
導体層6のコーナの曲線部に最も電界強度が高くなる。
このため、図2の実施例ではコーナの曲線部を除いた第
6の半導体層13を設けたものである。従って、降伏現
象は第6の半導体層で線降伏が起こり、降伏時の許容電
流が大きくなり、素子降伏時にも破壊しにくい半導体装
置を得ることができる。
FIGS. 2 to 5 show another embodiment, and FIG. 2 (a) is a sectional view taken along line AA of the semiconductor device.
FIG. 6B is a plan view schematically showing a plane excluding the electrodes and the oxide film. In the embodiment shown in FIG. 1, the electric field strength is highest at the curved portion of the corner of the sixth semiconductor layer 6.
For this reason, in the embodiment of FIG. 2, the sixth semiconductor layer 13 excluding the curved portion of the corner is provided. Therefore, in the breakdown phenomenon, a line breakdown occurs in the sixth semiconductor layer, the permissible current at the time of breakdown becomes large, and a semiconductor device which is not easily broken even at the time of device breakdown can be obtained.

【0016】さらに、図3に示す実施例のものは、第6
の半導体層13の表面に低抵抗の配線層15を設けたも
のである。また、図4に示すものは、第6の半導体層1
3のコーナの曲線部を除き、第6の半導体層13の表面
に低抵抗の配線層15を設けたものである。また、図5
に示すものは第6の半導体層13のコーナ部を除き、第
6の半導体層13の表面と酸化膜6の表面に低抵抗の配
線層15を設けたもので、A−Aの断面は図4のA−A
断面と同じである。これら図3ないし図5に示す実施例
では、第6の半導体層13の表面方向での電位ばらつき
を小さくすることができる。
Further, the sixth embodiment of the invention shown in FIG.
The low resistance wiring layer 15 is provided on the surface of the semiconductor layer 13. Moreover, what is shown in FIG. 4 is the sixth semiconductor layer 1
The wiring layer 15 having a low resistance is provided on the surface of the sixth semiconductor layer 13 except for the curved portion of the third corner. Also, FIG.
What is shown in FIG. 6 is a wiring in which a low resistance wiring layer 15 is provided on the surface of the sixth semiconductor layer 13 and the surface of the oxide film 6 except for the corner portion of the sixth semiconductor layer 13, and the cross section AA is shown 4 A-A
It is the same as the cross section. In the examples shown in FIGS. 3 to 5, the potential variation in the surface direction of the sixth semiconductor layer 13 can be reduced.

【0017】また、上記実施例ではPゲートのサイリス
タの例を示しているが、全ての導電層を反転させたNゲ
ートのサイリスタにも適用でき、トライアックについて
も適用できる。
Further, in the above embodiment, an example of a P-gate thyristor is shown, but it can also be applied to an N-gate thyristor in which all conductive layers are inverted, and can also be applied to a triac.

【0018】[0018]

【発明の効果】以上のように、降伏現象を点から線に拡
張することができ、降伏時の許容電流を増加させること
ができ、半導体装置を破損しにくくなる。また、降伏時
のリーク電流がゲート電流として働きゲート感度を適切
に選ぶことにより、半導体装置を点弧させることがで
き、半導体装置は過電圧を自分自身で保護することがで
きる。
As described above, the breakdown phenomenon can be extended from the point to the line, the allowable current at the breakdown can be increased, and the semiconductor device is less likely to be damaged. In addition, the leak current at breakdown acts as a gate current, and by appropriately selecting the gate sensitivity, the semiconductor device can be ignited, and the semiconductor device can protect itself against overvoltage.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の半導体装置の実施例の断面図と電極
及び酸化膜を除いた平面図である。
FIG. 1 is a cross-sectional view of an embodiment of a semiconductor device of the present invention and a plan view excluding electrodes and oxide films.

【図2】この発明の半導体装置の他の実施例の断面図と
電極及び酸化膜を除いた平面図である。
FIG. 2 is a cross-sectional view of another embodiment of the semiconductor device of the present invention and a plan view excluding electrodes and oxide films.

【図3】この発明の半導体装置の他の実施例の断面図と
電極及び酸化膜を除いた平面図である。
FIG. 3 is a cross-sectional view of another embodiment of the semiconductor device of the present invention and a plan view from which electrodes and oxide films are removed.

【図4】この発明の半導体装置の他の実施例の断面図と
電極及び酸化膜を除いた平面図である。
FIG. 4 is a cross-sectional view of another embodiment of the semiconductor device of the present invention and a plan view excluding electrodes and oxide films.

【図5】この発明の半導体装置の他の実施例の断面図と
電極及び酸化膜を除いた平面図である。
FIG. 5 is a cross-sectional view of another embodiment of the semiconductor device of the present invention and a plan view excluding electrodes and oxide films.

【図6】従来の半導体装置の断面図と電極及び酸化膜を
除いた平面図である。
FIG. 6 is a cross-sectional view of a conventional semiconductor device and a plan view with electrodes and oxide films removed.

【符号の説明】[Explanation of symbols]

1 第1の半導体層 2 第2の半導体層 3 第3の半導体層 4 第4の半導体層 5 第5の半導体層 6 酸化膜 7 カソード電極 8 アノード電極 9 ゲート電極 13 第6の半導体層 15 配線層 J1,J2,J3,J4 接合 1 1st semiconductor layer 2 2nd semiconductor layer 3 3rd semiconductor layer 4 4th semiconductor layer 5 5th semiconductor layer 6 oxide film 7 cathode electrode 8 anode electrode 9 gate electrode 13 6th semiconductor layer 15 wiring Layer J1, J2, J3, J4 Joining

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 第1の導電型の第1半導体層と、上記第
1の半導体層の両表面間を選択的に貫通する第2の導電
型の第2の半導体層と、上記第1の半導体層の片側の表
面に設けられた上記第2の導電型の第3の半導体層と、
上記第3の半導体層と対向する表面に選択的に設けられ
た第2の導電型の第4の半導体層と、上記第4の半導体
層内に選択的に設けられた第1の導電型の第5の半導体
層とを有する半導体装置において、上記第1の半導体層
の表面から上記第4の半導体層と上記第2の半導体層と
の間に第1の導電型で上記第1の半導体層の不純物濃度
より高い不純物濃度の第6の半導体層を設けたことを特
徴とする半導体装置。
1. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type that selectively penetrates between both surfaces of the first semiconductor layer, and the first semiconductor layer. A third semiconductor layer of the second conductivity type provided on the surface of one side of the semiconductor layer;
A fourth semiconductor layer of a second conductivity type selectively provided on the surface facing the third semiconductor layer, and a fourth semiconductor layer of a first conductivity type selectively provided in the fourth semiconductor layer. In a semiconductor device having a fifth semiconductor layer, the first semiconductor layer of the first conductivity type is provided between the surface of the first semiconductor layer and the fourth semiconductor layer and the second semiconductor layer. A semiconductor device having a sixth semiconductor layer having an impurity concentration higher than the impurity concentration of.
【請求項2】 上記第4の半導体層の表面形状及び上記
第2の半導体層の表面形状に曲線部を有する場合、上記
第6の半導体層が上記曲線部に対向する曲線部を除いた
半導体層である請求値1記載の半導体装置。
2. When the surface shape of the fourth semiconductor layer and the surface shape of the second semiconductor layer have a curved portion, the sixth semiconductor layer is a semiconductor excluding a curved portion facing the curved portion. The semiconductor device according to claim 1, which is a layer.
【請求項3】 上記第6の半導体層の表面に低抵抗の配
線層を設けた請求値1又は2記載の半導体装置。
3. The semiconductor device according to claim 1, wherein a wiring layer having a low resistance is provided on the surface of the sixth semiconductor layer.
JP16263594A 1994-06-21 1994-06-21 Semiconductor device Pending JPH088419A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16263594A JPH088419A (en) 1994-06-21 1994-06-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16263594A JPH088419A (en) 1994-06-21 1994-06-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH088419A true JPH088419A (en) 1996-01-12

Family

ID=15758367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16263594A Pending JPH088419A (en) 1994-06-21 1994-06-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH088419A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9268144B2 (en) 2013-06-18 2016-02-23 Teknologian Tutkimuskeskus Vtt Method for producing a mirror plate for Fabry-Perot interferometer, and a mirror plate produced by the method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9268144B2 (en) 2013-06-18 2016-02-23 Teknologian Tutkimuskeskus Vtt Method for producing a mirror plate for Fabry-Perot interferometer, and a mirror plate produced by the method

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