JPH088558B2 - Timing recovery circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a timing recovery circuit for recovering a timing clock of an NRZ signal used in digital communication and the like.

<Prior Art> A conventional timing reproducing circuit of this type is shown in FIG. This timing reproduction circuit is composed of an edge detection circuit 71, a timing tank 72, a limiter 73, and a phase locked loop (PLL) 74.

The edge detection circuit 71 uses the NRZ signal S shown in FIG.
When 1 is input, the sign change point of the NRZ signal S1 is detected, and the signal S2 in response to the sign change point as shown in FIG. 4B is input to the timing tank 72. The timing tank 72 is a resonant circuit whose center frequency is equal to the bit rate of the NRZ signal S1 and responds to the signal S2 while
Damped and oscillates to limit the signal S8 as shown in Fig. 4 (c).
Output to 73. This damped oscillation makes it possible to supplement the clock in the portion of the NRZ signal S1 where there is no sign change point.
The limiter 73 waveform-shapes the signal S8 and is shown in FIG. 4 (d).
The signal S9 shown in is output to the PLL74. The PLL 74 suppresses the jitter of this signal S9 and outputs the timing clock S4 shown in FIG. 4 (e). In this way, the timing clock S4 of the NRZ signal S1 can be regenerated.

<Problems to be Solved by the Invention> By the way, in the frequency band that is open to the private sector for wireless data communication, the transmission spectrum width is becoming narrower from the viewpoint of effective use of radio waves, and several hundreds of seconds per second. Digital data communication is performed at a speed of several tens of kilobits from a bit. Thus, at low bit rates, it is difficult to obtain a timing tank with a high Q. The reasons are as follows.

When the passive element is used, both the inductance and the capacitance have large values, and the shape of the passive element becomes large. Further, the Q of the passive element cannot be set high.

When configured with active elements, the timing tank is equivalent to a bandpass filter (BPF) and the active BPF
Tends to oscillate when trying to obtain a high Q.

Therefore, the above-mentioned conventional timing reproduction circuit using the timing tank has a problem that a high Q cannot be obtained when used for low-speed data transmission.

Therefore, an object of the present invention is to reproduce the timing clock of the NRZ signal without using a timing tank,
It is to provide a timing recovery circuit that can be used for low-speed data transmission.

<Means for Solving the Problems> In order to achieve the above object, the timing recovery circuit according to the present invention has an oscillation circuit whose oscillation frequency is set to be equal to or approximately equal to N times the bit rate of the NRZ signal, and the above NR.
An edge detection circuit that detects a sign change point of the Z signal and outputs a signal in response to the sign change point, and an output signal of the oscillation circuit are input, and have a cycle N times the oscillation cycle of the oscillation circuit, A timing generation circuit for generating N different timing signals having a phase difference equal to the oscillation cycle;
When the N timing signals and the edge signal from the edge detection circuit are inputted, the N timing signals are constituted by N independent storage means corresponding to the N timing signals, and the edge signal changes. , The storage value corresponding to the timing signal that has changed among the N timings is increased by 1, and the storage value of the other N-1 storage means is decreased by 1, and Edge storage accumulation circuit for outputting accumulated value information of the storage means, and an edge occurrence frequency for judging a timing signal having a timing with a high edge occurrence frequency from the timing signals based on the output signal of the edge storage accumulation circuit. Based on the output signals of the determination circuit and the edge occurrence frequency determination circuit, a timing signal having a phase suitable for identification is selected from N timing signals and the timing is selected. It is characterized in that a timing selection circuit which outputs as a lock.

<Operation> The oscillator circuit outputs a signal having an oscillation frequency equal to or substantially equal to N times the bit rate of the NRZ signal. The edge detection circuit
An edge signal is output by detecting the sign change point of the NRZ signal. The timing generation circuit receives the output of the oscillation circuit,
N different timing signals having a period N times the oscillation period and a phase difference equal to the oscillation period are generated. The edge storage / accumulation circuit receives the N timing signals and the edge signal from the edge detection circuit, and when the edge signal changes, the edge storage / accumulation circuit has a 1: 1 ratio to the N timing signals.
Among the N independent storage means corresponding to, the storage value of the storage means in which the timing signal has changed is increased by 1, and the storage value of the other N-1 storage means is decreased by 1 to obtain N A signal representing the accumulated value information in the storage means is output to the edge occurrence frequency judging circuit, and the edge occurrence frequency judging circuit judges a timing signal having a timing with a high edge occurrence frequency based on the signal representing the accumulated value information. The timing selection circuit receives the output of the edge occurrence frequency determination circuit and selects a timing signal having a phase suitable for identification from the N timing signals, that is, a timing signal that is frequently synchronized with the edge signal. , Output as timing clock.

<Embodiment> An embodiment of the present invention will be described below with reference to the circuit configuration diagram of FIG. 1 and the timing chart of FIG.

The edge detection circuit 1 includes two D flip-flops 1-
1, 1-2 and the exclusive OR circuit 1-3, when the NRZ signal S1 is input, the sign change point of the NRZ signal S1 is detected, and the edge signal S5 oscillated in response to the sign change point. It is output in synchronization with the output S2 of the circuit 2.

The oscillation cycle of the oscillation circuit 2 is equal to or approximately equal to 1/8 of the bit interval of the NRZ signal S1,
The timing generation circuit 3 outputs this output S2 to the counter 3-
1 is counted, and the count result is further counted by the decoder 3
By decoding at -2, as shown in FIG.
Timing signals S6 to S with a phase difference of 1/8 of the bit interval
Output 13

The edge storage / storage circuit 4 includes an inverter 4-1, an AND gate 4-2, and a shift register 4 as eight storage means.
-3 to 4-10. The shift registers 4-3-4
-10 is a serial-in and parallel-out bidirectional shift register, each of which has 8 stages. The right shift input of each shift register 4-3 to 4-10 is "H",
The left shift input is "L". The left shift or right shift operation of each shift register 4-3 to 4-10 is controlled by each timing signal S6 to S13. When the timing signal S6 to S13 is "H", right shift and "L" are performed. "When it is, it is designed to shift to the left. Each shift register 4-3 to 4-10 outputs the output of the fifth stage from the right as signals S22, S21, to S15. Shift register 4-
Clock S14 representing shift timing of 3 to 4-10
Is obtained by inverting the output signal S2 of the oscillator circuit 2 by the inverter 4-1 and taking the logical product of it and the edge signal S5 from the edge detection circuit 1 by the AND gate 4-2.
Only when the edge of the Z signal S1 is detected, the shift operation is performed in synchronization with the falling edge of the signal S2. As shown in FIG. 2, since the edge signal S5 corresponding to the sign change point of the NRZ signal S1 always matches the timing with any of the timing signals S6 to S13, only the shift register corresponding to this has a left shift (SL ), And the other shift registers shift right (SR).

That is, immediately before the clock S14-1 shown in FIG. 2 is output, the shift register 4-6 outputs “L” from the right to the fourth stage, and outputs from the right to the fifth stage to the eighth stage. Is "H", the output signal of the fifth stage from the right is output to the outside.
S19 is "H", the shift register 4-7 is also output to the outside from the right to the fourth stage output "L", the right to the fifth to eighth stage output "H". It is assumed that the output signal of the fifth stage from the right is "H". Since only the timing signal S10 is "L" at the rising edge of the clock S14-1, only the shift register 4-6 that receives it shifts to the left and the other shift registers 4-3, 4-4, 4-5. , 4-7, 4-8, 4-9, 4-10 shift right. Therefore, in the shift register 4-6, the output from the fifth stage from the right becomes "L", and the output of the fifth stage, that is, the output signal S19 becomes "L", while the shift register 4-7 shifts to the right. Then, the signal from the right to the third stage is "L", and the output signal S18, which is the output of the fifth stage, remains "H". Next, at the rising edge of the clock S14-2, since only the timing signal S9 is "L", only the shift register 4-7 which receives it performs the left shift, and the others perform the right shift. Therefore, the fourth to right stages of the shift register 4-6 are "L", the output signal S19 which is the fifth stage output is "H", and the shift register 4-7 is 4 from the right.
The level up to the stage becomes "L", and the output signal S18, which is the output of the fifth stage from the right, remains "H". Next, since the timing signal S9 becomes "L" at the rising edge of the clock S14-3, the shift register 4-7 that receives it shifts to the left,
From the right to the fifth stage, it becomes "L", the output signal S18 becomes "L", while the shift register 4-6 shifts to the right,
The signal from the right to the third stage is "L", and its output signal S19 remains "H". In this way, at the rising edge of the clock S14, that is, when the edge signal S5 is output, which timing signal S6 to S13 becomes "L" is stored and accumulated in each shift register 4-3 to 4-10, and the edge signal S5 The shift register 4-3 to 4-10, which receives the timing signals S6 to S13 of "L" at a high frequency, outputs the signal of "L". When the edge signal S5 is detected regularly and continuously five times or more in synchronization with a timing signal, the oscillation cycle of the oscillation circuit 2 is 1 of the bit interval of the NRZ signal S1.
Since it is equal to or substantially equal to / 8, any one of the outputs S15 to S22 of the shift registers 4-3 to 4-10 is
One is "L" and the others are all "H". However, if the oscillation cycle of the oscillator circuit 2 is not equal to 1/8 of the bit interval of the NRZ signal S1, or if the NRZ signal S1 has excessive jitter and the edge signal is not detected to some extent regularly, S15
~ All of S22 becomes "H" or multiple "L" s occur.

On the other hand, the edge occurrence frequency determination circuit 5 includes the encoder 5-1.
The input signal S15 to S22 is converted into a binary code at the "L" position and output as signals S23 to S25. The encoder 5-1 updates the values of S23 to S25 in synchronization with the signal S2 only when one of the signals S15 to S22 is "L", and retains the previous state in other cases. It has become. With this configuration, it is possible to determine which of the timing signals S6 to S13 the timing at which the edges are concentrated corresponds to.

The timing selection circuit 6 is composed of an 8-channel multiplexer 6-1 and inverts the signal selected by the signals S23 to S25 from the encoder 5-1 among the timing signals S6 to S13 and outputs it as a signal S26. At this time, it is convenient for identification to select a timing that is out of phase with half the bit interval with respect to the edge detection timing.

In this way, this timing recovery circuit
The sign change points of the outputs S6 to S13 of the timing generation circuit 3.
It has a function of determining which of the two corresponds to and outputting a timing pulse S26 suitable for identification. Internal timing S6 to S
13 and the code change point of the NRZ signal S1 are compared each time the code change point is detected, and a timing signal suitable for identifying the NRZ signal S1 is promptly selected from the timing signals S6 to S13 while the code change point When it is not available, the NRZ signal timing clock can be regenerated without using the timing tank to maintain the state up to that point, and it can be used for low-speed data transmission, and it can be configured with logic elements, so it is small and inexpensive. Can be

It should be noted that the present invention is not limited to the above-described embodiments, and it goes without saying that various embodiments can be considered without departing from the scope of the claims. For example, in the above embodiment, the edge storage / accumulation circuit 4 is composed of the shift registers 4-3 to 4-10. Instead, an up / down counter is used to perform the right shift and left shift of the shift register. May correspond to. Also,
The edge occurrence frequency determination circuit 5 is composed of a CPU, memory, etc.,
It is also possible to statistically process how the edges are distributed in the timings represented by the timing signals S6 to S13 by a program, and output the signal representing that to the multiplexer 6-1. In this case, in addition to the fact that the above signal can be determined by the average of the distribution,
Since the magnitude of the jitter of the Z signal S1 is known, the superiority or inferiority of the line can be determined. Further, in this embodiment, 1/8 of the 1-bit cycle
Is the basic unit of timing, but not 1/8,
It may be set to another integer.

<Effects of the Invention> As is apparent from the above, the timing recovery circuit of the present invention has the oscillation frequency set to be equal to or substantially equal to N times the bit rate of the NRZ signal, and the NRZ.
An edge detection circuit that detects a sign change point of a signal, a timing generation circuit that has N times the oscillation cycle of the oscillation circuit, and generates N different timing signals that have a phase difference equal to the oscillation cycle, When the N timing signals and the edge signal from the edge detection circuit are inputted, the N timing signals are constituted by N independent storage means corresponding to the N timing signals, and the edge signal changes. , The storage value corresponding to the timing signal that has changed among the N timings is incremented by 1, and the other N
For one storage means, the accumulated value is subtracted by 1 to obtain the above N
Based on the output signal of the edge storage storage circuit that outputs the storage value information of the individual storage means and the edge storage storage circuit,
An edge occurrence frequency determination circuit that determines a timing signal having a timing with a high edge occurrence frequency from the timing signals, and an output signal of the edge occurrence frequency determination circuit, which is suitable for identification from N timing signals. And a timing selection circuit for selecting a timing signal having a phase and outputting it as a timing clock.

Therefore, the timing recovery circuit of the present invention promptly selects a timing signal suitable for identifying an NRZ signal from N timing signals without using a timing tank, and a timing clock that enables error-free identification. Since it can be reproduced, can be used for low-speed data transmission, and can be composed of logic elements, it can be made small and inexpensive.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention,
2 is a timing chart showing the operation of the embodiment of the present invention, FIG. 3 is a block diagram showing the circuit configuration of the conventional example, and FIG.
The figure is a timing chart showing the operation of the conventional example. 1 ... Edge detection circuit, 1-1, 1-2 ... D flip-flop, 1-3 ... Exclusive OR circuit, 2 ... Oscillation circuit, 3 ... Timing generation circuit, 3-1 ... Counter ,
3-2 ... Decoder, 4 ... Edge memory storage circuit, 4-
1 ... Inverter, 4-2 ... AND gate, 4-3 ...
4-10 ... Shift register, 5 ... Edge occurrence frequency determination circuit, 5-1 ... Encoder, 6 ... Timing selection circuit, 6-1 ... 8-channel multiplexer.

Claims (1)

[Claims] 1. An oscillation circuit in which an oscillation frequency is set to be equal to or approximately equal to N times the bit rate of an NRZ signal, and an edge signal which responds to the sign change point by detecting the sign change point of the NRZ signal. Timing for inputting the output edge detection circuit and the output signal of the oscillation circuit, generating N different timing signals having a period N times the oscillation period of the oscillation circuit and having a phase difference equal to the oscillation period. The generation circuit, the N timing signals and the edge signal from the edge detection circuit are input, and the N number of timing signals are constituted by N independent storage means corresponding to the N timing signals. When the change occurs, the accumulated value of the storage means corresponding to the changed timing signal among the N timings is incremented by 1, and the accumulated values of the other N-1 storage means are changed. The edge storage storage circuit that outputs the storage value information of the N storage means, and a timing signal having a timing with a high edge occurrence frequency among the timing signals based on the output signal of the edge storage storage circuit. And a timing selection circuit for selecting a timing signal having a phase suitable for identification from N timing signals based on the output signal of the edge generation frequency determination circuit and outputting the timing signal as a timing clock. And a timing recovery circuit.