JPH088663B2 - Super-impose circuit - Google Patents

Description

The present invention relates to a superimposing circuit that can be used when characters or the like are inserted in a television screen.

[Outline of Invention]

The character signal output from the character signal output terminal and the blanking signal output terminal of the character generator are added to the blanking signal and input to the IC from a single input terminal of the video signal processing IC. A separating circuit having different detection levels is provided, and the separating circuit separates the charactor signal and the edging signal, and the separated edging signal blocks a predetermined period of the video signal processed in the video signal processing IC. By ranking and inserting a charactor signal in this period, it is sufficient to provide the video signal processing IC with one pin for inputting a signal for superimposing.

[Conventional technology]

When inserting a charactor signal that represents characters such as date and time into a video signal obtained from a video camera, etc., if the charactor signal that is a white character is simply inserted into the video signal, the image will be particularly white. Since there is a problem that this character cannot be seen in the background state of, the black framing is generally performed around the character.

FIG. 4 shows a conventional superimposing circuit. This will be explained. (1) is a video camera, and the signal obtained from this is a video signal processing IC (2) in the next stage. Input terminal or pin (3). The processing IC (2) has a clamp circuit (4) connected to the pin (3) and an adder circuit (7) connected to the next stage. (8) is its output terminal. In practice, a synchronizing signal synthesizing circuit, an output circuit, and the like are connected to the output terminal (8) after the output terminal (8).

Reference numeral (11) is a charactor generator, and a charactor signal Sc is obtained at its output terminal (12) and a blanking signal Sb is obtained at its output terminal (13).
The blanking signal Sb is input to the adder circuit (7) through the terminal (2) or the pin (10), and the blanking signal Sb is input to the blanking circuit (5) through the terminal or the pin (9) of the IC (2).

The operation of this configuration will be briefly described for one horizontal period of the video signal in the case of displaying the number "1", for example. In the predetermined period T within this one horizontal scanning period, the charactor generator (11) The obtained blanking signal Sb (FIG. 5A) is supplied to the blanking circuit (5) of the IC (2).
The video signal during Sb is blanked. And the charactor signal obtained in a period shorter than this period T
Since Sc (Fig. 5B) is added to the adder circuit (7) in the IC (2), the signal So shown in Fig. 5C is finally obtained at the output terminal (8). As is also clear, there is a blanking period before and after the charactor signal Sc in time, which results in black edging before and after the displayed character.

[Problems to be solved by the invention]

By the way, according to the configuration described above, as is clear from FIG. 4, the IC (2) requires two pins (9) and (10) for this purpose, which causes a problem in the configuration of the IC (2). There is a point.

To avoid this, it is conceivable to add the blanking signal and the charactor signal to the adder circuit at the same time, but in this case, it is difficult to match the black levels of both signals, so it is stable. There is a problem in that bordering is not possible, in other words, the edge portion is not a complete black component, making the characters difficult to see.

[Means for solving problems]

The present invention provides a character generator (11) having a character signal output terminal and a blanking signal output terminal, and a single input by adding the character signal Sc and the blanking signal Sb output from the character generator (11). A superimposing circuit having a video signal processing IC (2) input from a terminal (15), the video signal processing IC (2) having different detection levels and a single input terminal (15). A separation circuit (6) for separately separating the character signal and the blanking signal input from the above, and a blanking circuit (5) for blanking a predetermined portion of the video signal input by the separated blanking signal. , The blanking circuit (5) for the separated character signal
The superimposing circuit is provided with an adder circuit (7) for inserting a predetermined portion, which is the output of the above, into the blanked video signal.

[Action]

As a result, only one IC (2) pin is needed to display this character.

〔Example〕

In the following, the superimposing circuit according to the present invention will be described with reference to FIGS. 1 to 3, and the portions corresponding to those in FIG.

In the present embodiment, the blanking signal Sb (Fig. 3A) from the charactor generator (11) and the charactor signal
Sc (Fig. 3B) is added in the adder circuit (14),
Do so as to obtain the signal Sa shown in FIG. 3C, while IC (2)
A separation circuit (6) is provided inside the IC to output the signal Sa described above.
It is supplied to the separation circuit (6) through the input terminal of (2), that is, the pin (15), where this signal Sa is separated into the blanking signal Sb and the charactor signal Sc again, and the blanking signal Sb is supplied to the blanking circuit (b). 5), and the charactor signal Sc is supplied to the adder circuit (7).

FIG. 2 shows an example of the separation circuit (6) described above. To explain this, (15) is the IC described above.
Pin (2) and pin (20) are DC power supply terminals. The collectors of the pair of transistors (21a) and (21b) are connected to the power supply terminal (20) through resistors (22a) and (22c), respectively, and the emitters are connected to constant current circuits (27a) and (27), respectively.
It is grounded through b) and is also connected through a resistor (26). The collector (21a) and the collector (emitter) of the transistor (23) are connected in parallel to the transistor (21a), and the base of the transistor (23). And the base of the transistor (21b) are connected to the input terminal (25).
(24a) and (24b) are output terminals connected to the collectors of the transistors (21a) and (21b), respectively.

Further, a pair of transistors (28a) and (28b) are provided, the collectors of which are resistors (29a) and (2b), respectively.
9b) is connected to the power supply terminal (20), the emitters are connected to each other and grounded through the constant current circuit (32), the base of the transistor (28a) is connected to the above-mentioned input terminal (15), and the transistor (28b) is connected. ) Input terminal (3
0) and the collector is connected to the output terminal (31).

In such a configuration, the DC voltage E ₁ (for example, 2.5 V) shown in FIG. 3C is applied to the input terminal (25), and the DC voltage E ₁ shown in FIG. 3C is also applied to the input terminal (30). Voltage E ₂
(For example 2.0V) is applied.

According to this configuration, at all times (time t ₁ earlier), the transistor (21a) is in cut-off state, so that slave connexion transistor (23) to the (21b) constitute a differential amplifier circuit. By the way, in this state, resistors (22a) and (2
2b) have the same value and the transistors (23) and (21b) have the same characteristics (actually, such a condition is selected), the transistor (23) side And (21b) are electrically balanced with each other,
That is, the same amount of current flows through each other and the output terminal (24a)
At (24b) and (24b), as shown in FIGS. 3E and 3F, outputs having constant levels (provisionally E ₀ ) equal to each other are obtained. On the other hand, the transistor (28a) is off,
(28b) is on, and therefore the output terminal (31) has a third
As shown in Fig. D, low level output signal (output "0")
Is obtained.

In this state, when the signal shown in Figure 3 C is supplied to the input terminal (15), the transistor at time t ₁ ~t ₄ (28
a) turns on and (28b) turns off. Output terminal (3
In 1), the potential of the current terminal (20) (output “1”) is almost obtained. This is shown as signal Sb in FIG. 3D.

In addition, since the potential of the input terminal (15) becomes higher than the base potential E ₁ of the transistor (21b) at the times t _{2 to} t ₃ , the transistor (21a) has a potential E ₁ higher than the potential of the input terminal (15). The transistor (23) turns off and the transistor (21
Since b) forms a differential amplifier with the transistor (21a), the transistor (21b) is in the non-conducting state accordingly, so that the output terminals (24a) and (24b) are shown in FIGS. As shown, signals Se and Sf of opposite polarities are obtained.

Therefore, the above-mentioned signal Sd is supplied to the blanking circuit (5) to blank the video signal, and the signal Sf (or Se) is supplied to the adding circuit (7), which causes the charactor. Display can be performed (see signal Sg in FIG. 3G).

In this embodiment, the output terminals (24a) and (24
The reason that b) is configured as a pair is to cope with the case where the subsequent stage of this output terminal is configured as a differential amplifier circuit.

〔The invention's effect〕

According to the present invention connected as described above, it is of course possible to insert a reliable black level signal, that is, a blanking signal around the charactor signal at the time of superimposing, but in this case, the video signal processing IC (2) has the feature that the purpose can be achieved by adding only one pin (15), as well as the blanking signal,
Since the charactor signal is detected at different levels, the charactor character has a feature that a black border can be stably added.

[Brief description of drawings]

1 is a block diagram showing an example of a circuit according to the present invention, FIG. 2 is a concrete connection diagram of the separation circuit, FIG. 3 is a waveform diagram of its operation, FIG. 4 is a block diagram showing a conventional circuit, Fifth
The figure is a waveform diagram for explaining the operation. (2) is a video signal processing IC, (11) is a charactor generator, and (6) is a separation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Iizuka 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) References JP-A-58-79381 (JP, A) JPB 39-8869 (JP, B1)

Claims (1)

[Claims] 1. A character generator having a character signal output terminal and a blanking signal output terminal, and a video in which a character signal and a blanking signal outputted from the character generator are added and inputted from a single input terminal. A separation circuit for separating a character signal and a blanking signal, which have different detection levels and are inputted from the single input terminal, into a superimposing circuit having a signal processing IC. A circuit, a blanking circuit for blanking a predetermined part of the input video signal by the separated blanking signal, and a predetermined part which is the output of the blanking circuit for the separated character signal. A super-import system characterized by including an adder circuit to be inserted into a video signal. Circuit.