JPH088722A - 3-state circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Providing a 3-state circuit that speeds up a circuit section with a heavy load. [Structure] A three-state circuit is composed of a composite circuit of a MOS transistor and a bipolar transistor. [Effect] A high-speed logic circuit and arithmetic circuit using a 3-state circuit can be achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit and an arithmetic circuit, and more particularly to an arithmetic unit and an arithmetic circuit suitable for an ultra high speed microcomputer.

[0002]

2. Description of the Related Art In a logic (V) LSI requiring a high degree of integration, such as a microcomputer, a field effect transistor, particularly a MOS transistor technology, has become mainstream. However, MOS
Since the transistor is a voltage drive type, a signal is turned on / off between the power supply potential and the ground potential. Such a principle causes a critical bus at various places in the field of ultra-high speed. On the other hand, since the bipolar transistor is of a current drive type, it is possible to turn on / off a signal by a voltage operation with a small amplitude. However, since a bipolar transistor must supply a base current, a highly integrated logic LSI is difficult in terms of power consumption.

[0003]

SUMMARY OF THE INVENTION It is a first object of the present invention to provide a carry propagation circuit of high speed, high integration and low power consumption, and an arithmetic unit using the same, by eliminating the above drawbacks.

A second object of the present invention is to provide a high speed and low power consumption 3-state circuit.

[0005]

SUMMARY OF THE INVENTION A first feature of the arithmetic unit of the present invention is that in a kN bit arithmetic circuit having a carry propagation circuit, the carry propagation circuit is composed of bipolar transistors and field effect transistors. To be composed.

In a preferred embodiment of the arithmetic circuit of the present invention,
The carry propagation circuit has k N-bit carry propagation circuits in which bipolar transistors and field effect transistors are mixed.

Furthermore, in a preferred embodiment of the arithmetic circuit of the present invention, the k N-bit carry propagation circuits are provided with bipolar transistors at their connecting portions.

Further, in a preferred embodiment of the arithmetic circuit of the present invention, the carry propagation circuit has an N-bit carry propagation circuit constituted by a field effect transistor for carrying carry in (N-1) bits.

Further, in a preferred embodiment of the arithmetic circuit of the present invention, the field effect transistor is a MOS transistor.

The features of the three-state circuit of the present invention are (1) an input terminal and an output terminal, (2) first and second control terminals for complementary inputs, and (3) first and second potential terminals. (4) A first bipolar transistor in which one conductivity type collector is connected to the first potential terminal and one conductivity type emitter is connected to the output terminal, and (5) one conductivity type collector is connected to the output terminal. A second bipolar transistor whose one conductivity type emitter is connected to the second potential terminal, (6) one gate is connected to the input terminal, and the other gate is connected to the first control terminal, And,
First and second other conductivity type field effect transistors whose sources and drains are connected in series to the first potential terminal and the other conductivity type base of the first bipolar transistor, and (7) one gate Is connected to the input terminal, the other gate is connected to the second control terminal, and the drain and source are connected in series to the output terminal and the other conductivity type base of the second bipolar transistor. (1) a first and second one conductivity type field effect transistor, a source and a drain for the base and the output terminal of the first bipolar transistor, and a gate for the first control terminal or the second control. A third field effect transistor connected to the terminal, (9) the source and drain being the base of the second bipolar transistor and the second potential end. And a fourth field effect transistor whose gate is connected to the first control terminal or the second control terminal, and (10) is provided between the base of the first bipolar transistor and the output terminal. A first resistive element, (11) a second provided between the base of the second bipolar transistor and the second potential terminal
And a resistive element.

In the preferred embodiment of the tri-state circuit of the present invention, the field effect transistor is a MOS transistor.

Further, in a preferred embodiment of the tri-state circuit of the present invention, the resistive element is a resistor.

[0013]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a highly integrated processor 100 integrated on one semiconductor substrate according to an embodiment of the present invention. The microprogram control unit 101 has a microprogram ROM (Read Only Memory) as a main element.
Micro instruction decoder unit 102, arithmetic unit 1
03, a data input / output buffer 104, an address output buffer 105, and a clock supply buffer 106. The operation from instruction fetch to execution will be described with reference to FIG.

(1) Instruction fetch The contents of the program counter in the arithmetic unit 103 are output to the address output buffer 105 by the bus 115 and supplied to the bus 107 outside the processor 100. An instruction word corresponding to this address is supplied to the micro program control unit 101 via the bus 108, the data input / output buffer 104, and the internal bus 109.

(2) Micro instruction reading The instruction word applied to the micro program control unit 101 is decoded and output to the bus 110 as a micro instruction sequence.

(3) Decoding and execution of micro-instruction
The microinstruction is applied to the microinstruction decoder unit 102 via the. And decoded, and a signal group 111, 112, 113 for directly controlling the arithmetic unit 103 is output.

On the other hand, the original clock 114 input to the clock supply buffer 106 is the units 101, 102, 1
03 to the clock signal lines 114a, 114b, 11 respectively
4c.

FIG. 2 is a block diagram of the microprogram control unit 101 shown in FIG. 1, and includes an instruction register 200, an instruction decoder 201, a micro address selector 202,
OM address decoder 203, ROM memory unit 20
4, a microinstruction register 205, a register number register 206, and a control circuit 207 in the microprogram control unit 101. The instruction word input to the micro program unit 101 via the bus 109 is controlled by the control signal 219 of the control circuit 207 in the instruction register 200. The contents of the instruction register 200 is the bus 210
It is applied to the instruction decoder 201 via the, and decoded, and outputs the head address signal 211 and the register number signal 212 of the corresponding microprogram. The former selects the micro address selector 202 on the side of the head address signal 211 by the output signal 218 of the control circuit 207, and applies the output signal 213 of the micro address selector 202 to the address decoder 203 of the ROM. On the other hand, the latter is set in the register 206 for the register number by the output signal 220 of the control circuit 207.

In the ROM address decoder 203, the word corresponding to the input address signal 213 is determined and RO
One word stored in the M memory unit 204 is read out by driving at least one of the word signal groups 214. The read word is set in the micro instruction register 205 via the bus 215. Part of the contents of the microinstruction register 205 is connected to the microinstruction decoder unit 102 by a signal line 110a. Further, the signal line 216 of the other part is connected to the control circuit 207, and the instruction register 200 and the micro address selector 20 described above are connected.
2, applied to control of the register number register 206. Further, the signal line 217 in the other part indicates the address of the microinstruction to be read next to the currently executed microinstruction, and the signal line 218 controls the microaddress selector 202 to send the address signal 217 to the signal line 213.
Put on.

The output signal 110b of the register number register 206 is connected to the micro instruction decoder unit 102 at the next stage, similarly to the signal line 110a.

FIG. 3 shows a micro instruction decoder unit 10.
2 shows a configuration of the multiplexers 300, 301 and 302 for selecting the source of the register number, a register decoder 305 for selecting one of the registers to be operated,
A register decoder 306 for selecting the other one, a register decoder 307 for selecting a register for storing the operation result, a sub-microinstruction register 303 for delaying the operation timing of the register decoder 307 with the register decoders 305, 306 by one clock cycle, Arithmetic circuit
It comprises the register decoders 305 and 306 and a sub-micro instruction register 304 for delaying half a clock cycle. A part of the signal line 110a of the micro instruction register 205 of the micro program control unit 101 is a signal 110a indicating a register number for reading.
-1, 110a-2, a signal 110a-3 indicating a write register number, multiplexers 300, 301, 302
Control signals 110a-a, 110a-b, 11 for controlling
0a-c and a signal 110 for controlling an arithmetic circuit and the like to be described later
a-4. Multiplexers 300, 301, 30
2 is the instruction stored in the micro instruction register 205 as the source of the register number and the instruction decoder 201 described above.
, And stored in the register number register 206 as control signals 110a-a, 11a.
0a-b, 110a-c. The selection of the register to be read is based on the output signal 3 of the multiplexers 300 and 301.
Register decoders 305 and 30 respectively
6 and output signals 314 and 31 of the decoded result.
It is performed as 5. The register to be written is selected by temporarily storing the output signal 310 of the multiplexer 302 in the sub-micro instruction register 303, delaying it by one clock cycle from the register reading, inputting the signal 313 to the register decoder 307, and outputting the decoding result. Signal 316
Done as. Here, two registers are not always selected as the read registers. In the case of a one-operand operation (for example, increment / decrement, etc.) or a zero-operand operation (clear, etc.), there may be situations in which one register is read or no register is read. Further, the number of write registers is not limited to one. The operation result may be written to a plurality of registers.

The control of the arithmetic circuit is performed between the read and write timings of the register. This operation timing shift is caused by the sub-micro instruction register 30.
It is 4. The control signal 317 delayed by half a clock is applied to the arithmetic circuit.

FIG. 4 is a block diagram of the arithmetic unit 103, which is the center of this embodiment.
01, 402, an arithmetic circuit 403, a data read register 404 for reading data on the internal bus 109, a data write register 405 for outputting data to the internal bus 109, and an address for outputting an address to the internal bus 115. The address register 406 comprises a parallel shifter 407 for shifting data input from the write bus 412 by multi-bit.

The basic operation of the arithmetic unit 103 will be described in detail in four types.

(1) Register-to-register operation [Read two registers in the register group 400 and perform an operation by the operation circuit 403, and the result is again registered in the register group 40.
When writing to one register in 0. ] Register group 40
Two registers in 0 are assigned to the register decoder 305,
The contents of the selected register are selected by the outputs 314a and 315 of 306, and loaded on the register read buses 411 and 410 via the two ports 413 and 414, respectively. These data are detected at high speed by precharge and sense circuits 402 and 401 described later, and their output signals 415 and 416 are input to the arithmetic circuit 403. The operation result output signal 417 of the operation circuit 403 is loaded on the write bus 412 and written via the port 421 to the register of the register group 400 specified by the output signal 316a of the register decoder 307.

(2) Program counter update [Update (increment) of the program counter in the register group 400 and register number in the address register 406. The program counter in the register group 400 is selected by the control signal 315 which is the output signal of the register decoder 315, and the contents are loaded on the register read bus 410 via the port 414. Register read bus 410
The above data is detected by the precharge & sense circuit 401, and is input to the arithmetic circuit 403 as an output signal 416. No data is loaded on the register read bus 411 side, and the control signal 317 is set to the increment mode, whereby the output signal 41 of the operation result of the operation circuit 403 is output.
7 is [(program counter) +1]. This value is written via the write bus 412 by the control signal 316a.
The updated value is written from the port 421 to the program counter.

On the other hand, the contents of the program counter loaded on the register read bus 410 via the port 414 are stored in the address register 406 by the control signal 316d and sent to the internal bus 115 via the bus 422.

(3) Calculation of input data and data output The data input from the internal bus 109 to the data read register 404 is loaded on the register read bus 411 via the port 418. On the other hand, the content of one register in the register group 400 is loaded on the read bus 410 via the port 414 by the control signal 315. The output signal 417 of the calculation result of the calculation circuit 403 is the write bus 41.
2, the data is written to one register or the data write register 405 in the register group 400. The output signal 417 of the arithmetic circuit is output from the data write register 40
When written to 5, the control signal 112 causes port 41
9 to the internal bus 109. In this example, one register and memory
This is a case where the calculation result of data is stored again in the memory.

(4) Parel shift The arithmetic result output signal 417 of the arithmetic circuit 403 is sent to the parrel shifter 407 via the write bus 412 to the control signal 316.
It is set by e. In the next cycle, the control signal 31
The result shifted according to the shift amount designated by 4c is loaded on the register read bus 411 via the port 420. This situation is exactly the same as when reading the registers in the register group 400, and is omitted here.

The detailed circuit of each component in the arithmetic unit 103 and its operation will be described below with reference to the drawings.

FIG. 5 is a detailed circuit diagram of the sense circuits 401 and 402 for precharging the register group 400 and the read bus. Each configuration and operation principle will be described.

(1) 1-bit configuration of the register group 400 The register group 400 is, as described above, connected to the two read buses and one write bus in the "multiport RAM".
(Random Access Memory) ”. The 1-bit configuration is, in terms of the least significant bit, an NMOS transistor 500 forming a port 421-0 connected to a write bus 412-0, CMOS inverters 501 and 502 forming a 1-bit memory, and a read bus 410. -0,41
NMOS transistor 5 for loading data on 1-0
03-506. The write operation to the RAM 1 bit is performed by setting the control signal 316a-0 to "High" to apply the contents of the write bus 412-0 to the CMOS inverters 501 and 502 which form the memory through the NMOS transistor 500. Be seen. In the read operation, the output of the CMOS inverter 501 is set to “Hig” by setting the control signals 315-0 and 314a-0 to “High”.
Only when "h", the charges on the read buses 410-0 and 411-0 are discharged (discharged). If the output of the CMOS inverter 501 is "Low", no discharge occurs on each read bus. The read operation of the register group 400 is performed after precharging the read buses 410 and 411.

(2) Read buses 410-0, 411-0
1 bit of the precharge & sense circuit 401 corresponding to the read bus 410-0 is an NPN bipolar transistor (hereinafter simply referred to as an NPN transistor) for precharging the read bus 410-0. 512, CMOS inverters 507, 508, 509, NM for controlling the same
OS transistor 510, PMOS transistor 511
Consists of The operation of this circuit can be considered separately for the precharge period and the discharge period.

(I) Precharge Period During the precharge period, the clock signal 520 is "Low" and the NMOS transistor 510 is "OFF". Now, assuming that the read bus 410-1 is at "Low" level, the output of the CMOS inverter 507 is "Hig."
The output of the CMOS inverter 509 connected in series with the CMOS inverter 508 is at the "Low" level.
Since the output of 9 is connected to the gate of the PMOS transistor 511, the PMOS transistor 511 is turned on. In the above situation, a sufficient base current is supplied to the base 521 of the NPN bipolar transistor 512 by the CMOS inverter 507 and the PMOS transistor 511, and the NPN transistor 512 is supplied.
Collector current is injected from the emitter into the read bus 410-0 and begins precharging the read bus 410-0. As the read bus 410-0, which was at the "Low" level, approaches the "High" level, the CMOS inverter 507 first goes to the "Low" level, and the inverter 507
Current supply to the base of the NPN transistor 512 is suppressed. Next, the final outputs 416-0 of the CMOS inverters 508 and 509 connected in series approach "High" level, the PMOS transistor 511 is also turned "OFF", and the base current of the NPN transistor 512 is cut off. By the above operation, the read bus 410-0 in the precharge period (the period when the clock signal 520 is "Low")
Is precharged to a certain voltage. Since this precharge voltage is determined by the threshold voltages (V _TH ) of the NMOS and PMOS transistors constituting the CMOS inverters 507, 508, 509, the V
Even if there is a variation in _TH, the precharge voltage is determined according to that variation, and stable precharge operation can be performed. Similarly, the precharge & sense circuit 402 also precharges the read bus 411-0. Outputs 416- of the two precharge & sense circuits 401 and 402-
0, 415-0 surely goes to the "High" level after the precharge.

The precharge & sense circuits 401, 4
02 are arranged symmetrically with respect to the center point of the clock signal line 520, so that the clock signal line 520 can be shared, and the read buses 410 and 411 are provided on both sides of the precharge & sense circuits 401 and 402. It is possible to install them side by side.

(Ii) Discharge Period A register read (discharge) cycle from the register group 400 is performed by setting the clock signal 520 to "High" level. When the clock signal 520 is set to the “High” level, the NMOS transistor 510 connected to the base of the NPN transistor 512 is turned on, the base potential of the NPN transistor 512 is maintained at “Low”, and the read bus 410-0. Can be prevented from being affected by the current supply from the CMOS inverter 507 and the PMOS transistor 511 due to the fluctuation in the potential. Now, RAM
The output of the CMOS inverter 501 forming one bit is at "High" level, and the control signal 315-0 is "Hig".
At the time of the “h” level, the NMOS transistors 503 and 505
Is turned on, the read bus 410-0 is connected to the two NMOS transistors 503 and 5 connected in series.
05 is discharged. Due to the discharge, a slight change in the read bus 410-0 is amplified by the gain of the CMOS inverters 508 and 509 connected in series and reflected on the read signal 416-0. Therefore,
Even if the read bus 410-0 has a considerably large capacitive load, the read signal 416-0 changes from the "High" level to the "Low" level when the discharge of about 0.1 V occurs.

FIG. 6 shows the clock signal 5 in the above operation.
20, base potential 521 of NPN transistor 512,
It shows operation waveforms of the read bus 410-0 and the read signal 416-0. As can be seen from this figure, a CMOS inverter 50 that controls the NPN transistor 512.
7. Read bus 410 by PMOS transistor 511
−0 is precharged in two stages and reaches a certain precharge voltage. On the other hand, in the discharge period, the read signal 416 is generated due to the very slight discharge of electric charge from the read bus 410-0.
-0 determines the output. This is an effect that the precharge voltage is set to a voltage slightly higher than that of setting the level of the read signal 416-0 to "Low". As described above, the precharge voltage is the NMOS transistor, PMO
Since it is determined by the threshold voltage (V _TH ) of the S transistor, it is not affected by variations in the MOS process.

FIG. 25 is an explanatory diagram showing the necessity of the sense circuit in the read bus between the register and the arithmetic circuit. Flip-flops 2500-0 to 2500- constituting a 1-bit storage section of an (n + 1) word register
n, a read bus 522, two sets of NMOS transistors 2501-0 to 2501-n forming a logical product for sending data to the read bus 522, and a precharge & sense circuit 401. In such a configuration, if any one of the read control signal groups 315 becomes "High", one of the two sets of NMOS transistors connected to the signal turns "on" and the other according to the contents of the flip-flop. It will be in the "on" state or the "off" state. As a result, the contents of the register (flip-flop) corresponding to the read signal that has become “High” are reflected on the read bus 522. At this time, the following problem occurs. That is, the read bus 522 has many registers (flip
Since the flop) is connected via two sets of NMOS transistors, the wiring capacitance of the bus itself and the drain capacitance of the NMOS transistor are added. Therefore, if a buffer having a high driving capability is added to each flip-flop in order to reflect the contents of each flip-flop on the read bus 522, the size of the register section is extremely increased, and high integration is achieved. This is not possible with processors. Therefore, the precharge & sense circuit 401 of the read bus 522 according to the present embodiment precharges the read bus 522 in advance and senses a very slight potential change only when the charge of the read bus 522 is extracted. By detecting with a circuit, high speed and high integration can be achieved.

The write bus, on the other hand, has exactly the opposite meaning. FIG. 26 illustrates the need for high drive capability buffers on write bus 524.

Data is written to one bit of the n + 1 word register via the write bus 524. In this case, 1-bit data must be sent to the write bus 524 having a large capacitive load for the same reason as the read bus 522 described above. That is, data is written to one (or a plurality) of an unspecified number of registers (flip-flops) via the write bus 524. Therefore, the buffer 960 having high driving capability is indispensable.

FIG. 7 shows the structure of the address register 406, which is a C connected to the read bus 410-0.
MOS inverters 700 and 701, write MOS transistor 710, CMOS inverters 720 and 721 forming a memory (flip flop), internal bus 211
5 is connected to the bus driver 730. As described above, the read bus 410-0 is precharged when the clock signal 520 is "Low", and discharged when the clock signal 520 is "High". The CMOS inverters 700 and 701 connected in series are the CMOS inverters 50 in the precharge & sense circuit 401 of FIG.
Like 8, 509, it acts as an amplifier circuit that amplifies a very small fluctuation of the read bus 410-0. This result is NM
The write signal 316d input to the gate of the OS transistor 710 is stored in the flip-flop (configuration of the CMOS inverters 720 and 721). CMOS
The output of the inverter 720 is a bipolar transistor and C
It is mounted on the internal bus 115 via the bus 422 by a bus driver 730 composed of a composite gate circuit with a MOS transistor.

FIG. 8 shows a bipolar transistor and CMOS
This shows the internal configuration of a bus driver 730 composed of a composite gate circuit with a transistor.
OS transistor 800, NMOS transistor 80
1, output stage NPN transistors 804, 805, the N
Consisting of resistive elements 802 and 803 inserted between the base and emitter of the PN transistor. Output signal 810 of CMOS inverter 720 constituting flip-flop
Is input to the gates of the PMOS transistor 800 and the NMOS transistor 801, and if the output signal 810 is “Low”, the PMOS transistor 800 is N, and if the output signal 810 is “High”,
The MOS transistor 801 turns "ON". Therefore, when the input signal 810 of the bus driver 730 is "Low", the base current is supplied to the NPN transistor 804 by the PMOS transistor 800, the collector current flows through the NPN transistor 804, and the output 422-0 is rapidly charged. And becomes the “High” level. When the input signal 810 is “High”, the NMOS transistor 80
5, the electric charge of the output 422-0 is rapidly discharged, and the output 422-0 becomes the "Low" level. Here, the resistive elements 802 and 803 are NPN transistors 804 and 805
Has the effect of biasing the base of.

FIG. 9 shows the configuration of the arithmetic circuit 403 in FIG. 4, showing the least significant four bits.
In this drawing, only the adder circuit which is the largest critical bus of the arithmetic circuit 403 is shown. Arithmetic circuits such as a subtraction circuit, a multiplication circuit, and a division circuit are applications of an addition circuit, and therefore, an explanation will be given of the addition circuit as an example. Generally, in addition to these arithmetic circuits, a logical operation circuit is also included, but it is omitted here. The least significant bit of the 4-bit addition circuit is the above-mentioned precharge & sense circuit 401, 402.
Is a latch 910, 911 for temporarily storing the contents of the read signal 416-0, 415-0, a gate 920 for taking the logical product of the output signals 970, 971 of these latches, the output signal of the gate 920 and the signals 970, 971. And a gate 930 that takes an exclusive OR with these gates 920 and 93.
A 4-bit carry propagation circuit 900 for carrying a carry [carry (although it is a borrow in subtraction, hereinafter these carry information is defined as a carry)] by an output signal 972-0, 973-0 of 0, The least significant bit output signal 974-0 of the circuit 900 and the output signal 9 of the gate 930
A gate 940 for exclusive-ORing with the gate 73-0, a latch 950 for temporarily storing the gate output signal 975, and a bus driver 960 for placing the output signal 976 of the latch on the write bus 412-0. . In this adder circuit, output signals 973 from the gates 920 and 930
Are 2-bit data signals 970 and 9 input to the adder circuit.
71, and the output signal 975 of the gate 940.
Is the addition result of the 2-bit input to the addition circuit and the carry. Also, the output signal 9 of the gate 920
Reference numeral 72-0 indicates to the carry propagation circuit 900 that carry-up to the higher-order bit necessarily occurs when two bits input to the adder circuit are at logic levels "1" and "1".
Output signal 973-0 indicates that when the two bits input to the adder circuit are at the logical level "1", "0" or "0", "1", the carry from the lower bit should be propagated to the upper bit. Notify the propagation circuit 900. The clock signal 1044 in FIG. 9 is supplied to the carry propagation circuit 900, the latch 950, and the inverter 980. The output signal 990 of the inverter 980 is supplied to the latches 910 and 911. The clock signals applied to the latches 910, 911 and 950 are in the opposite phase because data is temporarily stored in the latches 910 and 911 in the first half of one clock cycle, and the addition result is temporarily stored in the latch 950 in the second half. That is because

The application of the clock signal 1044 to the 4-bit carry propagation circuit 900 is to carry out a dynamic operation in carry propagation, which will be described later. Also, other input / output signals 1040, 1040 to carry propagation circuit 900
Reference numeral 42 denotes a carry input signal from a lower position and a carry output signal to a higher position. Still another input signal to carry propagation circuit 900 is AND output signal 972 at each bit.
−0 to 972-3, Exclusive OR output signal 973-0 to 9
There is 73-3. Further, another output signal from carry propagation circuit 900 is carry signal 974-0 in each bit.
There is ~ 974-3. The usage of these input / output signals will be described in detail below.

FIG. 10 shows a bipolar transistor and a MOS.
This shows a configuration of a 4-bit carry propagation circuit 900 in which transistors are mixed, and k carry propagation circuits 90 between 4 bits that propagate only carry between 4 bits.
1 and a 4-bit carry propagation circuit 902 that propagates 4-bit carry. The k 4-bit carry propagation circuit 901 includes an NMOS transistor 100 that operates in response to a carry input signal 1040 from the lower order.
4, AND output signal 972-0 to 97 for each bit
NMOS transistor 100 operating corresponding to 2-3
5 to 1008, exclusive OR output signal 9 for each bit
NMOS transistors 1000 to 1003 operating corresponding to 73-0 to 973-3, N provided at a connection portion for detecting carry propagation from the lower side and propagating to the next stage
PN transistor 1011, NPN transistor 10
11 includes a PMOS transistor 1009 for supplying a base current to 11 and a PMOS transistor 1010 for pulling up the collector side of the NPN bipolar transistor 1011 to the power supply. The operation of the 4-bit carry propagation circuit 901 will be described below.

The logical product level of the logical product output signals 972-0 to 972-3 and the exclusive OR output signals 973-0 to 973-3 of the input 2 bits corresponding to each bit may not be simultaneously "0". However, at the same time, the logic level is "1".
It never becomes. Next, three examples of the operation of the circuit 901 with respect to two sets of 4-bit input data patterns will be described.

The condition here is that the PMSO transistor 10
09 and 1010 gate input signals 1043 are grounded,
Set to “ON” state.

(1) Input data "0000" and "00"
00 "When the carry input signal 1040 from the lower order is either" 0 "or" 1 ", the signals 972-0 to 972-
3 and 973-0 to 973-3 are all "0" and NM
Since the OS transistors 1000 to 1008 are all in the “off” state, the PMOS transistor 1009 is
Since the current is continuously supplied to the base of the bipolar transistor 1011, the NPN transistor 1011 is turned on. Therefore, even if the pre-up PMOS transistor 1010 is in the “on” state, the collector potential of the NPN transistor 1011 is “0”, and the carry output signal 1042 is “0”. This example shows the case where there is no carry propagation.

(2) Input data "0000" and "11"
11 "signals 973-0 to 973-3 are all" 1 ", and signal 972
Since -0-972-3 are all "0", there is no carry propagation when the carry input signal 1040 from the lower order is "0", but carry carry is carried when the carry input signal 1040 is "1". There is. If the carry input signal 1040 from the lower bit is “0”, the NMOS transistor 10
04 to 1008 are in the "off" state. On the other hand, NMOS
Although the transistors 1000 to 1003 are turned off, the current supplied to the base of the NPN bipolar transistor 1011 by the PMOS transistor 1009 is NP.
Only the N bipolar transistor 1011 flows (transitionally, the NMOS transistors 1000 to 1003).
The NPN bipolar transistor 1011 continues to be in the “ON” state. Therefore, carry output signal 1042 is "0".
Becomes

On the other hand, carry input signal 1040 is "1".
In the case of, all the NMOS transistors 1000 to 1004 are in the “ON” state, so the PMOS transistors 1009
Is supplied to the ground potential GND via NMOS transistors 1000 to 1004 connected in series.
Since it is pulled out to the side, the injection of current into the base of the NPN transistor 1011 is suppressed. Therefore, the NPN transistor 1011 is turned off, and the carry output signal 1042 is charged to "1" by the pull-up PMOS transistor 1010. That is, carry propagation to the next stage occurs.

(3) Input data "0011" and "11"
10 "At this time, the signals 973-0, 973-2, 973-3
Is "1", the signal 972-1 is "1", and the other signals are "0". Therefore, the NMOS transistor 100
Only 0, 1006, 1002, and 1003 are in the "on" state, and the others are in the "off" state. Under such a condition, even if the carry input signal 1040 is "0" or "1", an NMOS equivalent to being connected in series toward the ground side is provided.
Transistors 1003, 1002, 1006 are PMOS
Since the current supplied by the transistor 1009 is extracted, it serves to suppress the current supply to the base of the NPN transistor 1011. Therefore, NPN bipolar transistor 1011 is turned off, so that carry output signal 1042 becomes "1" and the carry is propagated to the next stage.

In the above description, the state in which the carry input signal 1040 from the lower order is "1" and all the NMOS transistors 1000 to 1003 are "on" is the most critical path 1 for carry propagation. Subsequently, NMOS transistors 1003, 1002, 10
01, 1005 path 2, NMOS transistor 100
3, 1002, 1006 path 3, NMOS transistors 1003, 1007 path 4, NMOS transistor 10
08, the current supplied from the PMOS transistor 1009 can be easily extracted in the order of the path 5.

Accordingly, the NMOS transistors 1000 to 1000
When the gate 1044 has a gate length L and a gate width W, the path 1 corresponds to a single NMOS transistor having a gate width of W / 5, so that the gate width of each of the NMOS transistors 1005 to 1008 in the paths 2 to 5 is W / 2, W respectively
/ 3, W / 4, W / 5, and the 4-bit carry propagation circuit 901 can be compactly configured. The same can be applied to the 4-bit carry propagation circuit 902 described later.

The PMOS transistors 1009 and 101 in the carry propagation circuit 901 between 4 bits described above.
An example in which the gate input signal 1043 of 0 is grounded and the PMOS transistors 1009 and 1010 are always in the "on" state has been shown. 1009,
Even if the signal 1043 is set so that the signal 1010 is turned on, the same carry propagation speed can be obtained.

According to this circuit system, the current flowing into the base of the NPN transistor 1011 is extracted through the above-mentioned five kinds of paths of the NMOS transistors 1000 to 1008, whereby the NPN transistor 1011 is turned "on".
Since the operation is a complete current operation for controlling the state and the "off" state, a very small amplitude voltage operation is achieved and high speed operation can be obtained. That is, the current amplification of the bipolar transistor and the MO
This is a circuit system that skillfully utilizes the switch characteristics of the S transistor.

On the other hand, since the 4-bit carry propagation circuit 901 uses a substantially complete current operation, NM
The potentials at the sources and drains of the OS transistors 1000 to 1003 have small amplitudes. Therefore, it is difficult to extract the carry signal corresponding to each bit in the 4 bits at the MOS level. Therefore, it is desirable to use the above-described 4-bit carry propagation circuit 902 together. The embodiment of the 4-bit carry propagation circuit 902 is configured by a precharge method, and the PMOS transistor 1 for precharge is used.
020 to 1023, NMOS transistors 1031 to 1034 for inhibiting a logic operation during precharge, carry propagation NMOS transistors 1024 to 1026, carry input NMOS transistor 1027, and NMOSs receiving AND signals 972-0 to 972-2 It comprises transistors 1028 to 1030. The operation of the carry propagation circuit 902 within 4 bits is as follows.

(1) Precharge While the clock signal 1044 is "Low", the precharge PMOS transistors 1020 to 1023 are "ON".
Then, the capacitive loads of the sources and drains of the NMOS transistors 1024 to 1026 are charged up to the power supply voltage Vcc. At this time, the logical product signals 972-0 to 972
-2 in order to complete the precharge regardless of the state ("0" or "1"), the NMOS transistor 10
31 to 1034 prevent the charge from being extracted by the clock signal 1044 ("Low" state).

(2) Discharge While the clock signal 1044 is "High", the precharge PMOS transistors 1020 to 1023 are in the "off" state, and the NMOS transistors 1031 to 1023.
34 is turned on. In this state, according to the input data of the adder circuit, the NMOS transistors 1024-10
30 "on" state or "off" state, and N
The source and drain potentials of the MOS transistors 1024 to 1026 are determined. The combination of the two sets of 4-bit input data to the adder circuit will be described by taking the three combinations used in the 4-bit carry propagation circuit described above as an example.

(1) Input data "0000" and "00"
00 ”In this case, if the carry input signal 1040 from the lower order is either“ 0 ”or“ 1 ”, the signal 973
−0 to 973-2 and 973-0 to 972-2 are all “0”, and the carry propagation NMOS transistor 1
The source and drain potentials of 024 to 1026 remain at the precharge voltage, and no charge is extracted. Therefore, carry signal 974-0,9 within 4 bits
74-3 are all "1" (negative logic), indicating that there is no carry propagation.

(2) Input data "0000" and "11"
11 "In this case, the logical product signals 972-0 to 972-2 are all" 0 ", and the exclusive OR signals 973-0 to 973-2 are all" 1 ". Therefore, carry propagation NMOS transistors 1024 to 1026. Turns on and NMO
S transistors 1028 to 1030 are turned off. Here, if the carry input signal 1040 from the lower order is “0”, no carry propagation occurs, and the sources of the carry propagation NMOS transistors 1024 to 1026 are
The drain potential remains the precharge voltage. Therefore, carry signals 974-0 to 974-3 within 4 bits are provided.
Remains "1" (negative logic), indicating that there is no carry propagation.

On the other hand, the lower carry input signal 104
When 0 is “1”, carry propagation NMOS transistors 1026, 1025, 1024 and carry input NM
Since the OS transistor 1027 and the NMOS transistor 1031 are connected in series and are in the “ON” state, the sources of the NMOS transistors 1024 to 1026 are
The charge of the drain is drawn to the ground potential GND. Therefore, each potential becomes “0” (negative logic) and 4
The carry signal in bit 974-0 to 974-3 indicates that there is carry.

(3) Input data "0011" and "11"
At this time, the carry propagation NMSO transistor 10
24, 1026, NMOS transistor 1029 is "ON"
It becomes a state. In this state, if the carry input signal 1040 from the lower level is “0”, the NMOS transistor 102
The charge is extracted along the path 6,1029, and the carry signals 974-2 and 974-3 within 4 bits become "0" (negative logic), indicating that there is carry. Further, the other carry signals 974-0 and 974-1 become "1" (negative logic),
Indicates no carry.

On the other hand, carry input signal 104 from the lower order
When “0” is “1”, the NMOS transistor 1027 is also turned “on”, and therefore, there are two paths for extracting electric charge: a path for the NMOS transistors 1024 and 1027 and a bus for the NMOS transistors 1026 and 1029. In this case, since charges are extracted from the sources and drains of the NMOS transistors 1024 to 1026,
Carry signals 974-0 to 3 within 4 bits are all "0"
(Negative logic), indicating that carry is present.

The 4-bit carry propagation circuit 902
The reason why the most significant bit is unnecessary is that the 4-bit carry propagation circuit 901 performs this.

FIG. 11 shows operation waveforms of the 4-bit carry propagation circuit 901 described above. When the carry input signal 1040 is “Low”, the base current PMO is applied to the base electrode 1041 of the NPN transistor 1011.
It is supplied from the S transistor 1009, the NPN transistor 1011 is turned on, the collector potential is "0", and the carry output signal line 1042 is "Low".
Becomes When the carry input signal 1040 becomes “High”, the base current injected by the PMOS transistor 1009 is suppressed, and
1 moves to the “off” state, and carry output signal line 1042
Shifts to “High”.

FIG. 27 shows a 4-bit (N = 4) adder circuit 1.
8 (k = 8) from 100-0 to 1100-7 are connected, and 3
1 shows an embodiment in which a 2-bit addition circuit is configured. The carry propagation circuits 900-0 to 900-7 in the adder circuits 1100-0 to 1100-7 are connected in series, and the carry input 1040-0 from the lowest order is the carry propagation circuits 900-0 to 900-. Propagate to 7 one after another. In this embodiment, eight sets of 4-bit unit carry propagation circuits are connected in series to form 32 bits, but they may be connected in series in arbitrary bit units.

FIG. 12 shows the state of carry output signals 1042-0 to 1042-7 of carry propagation circuits 900-0 to 900-7 for each bit in the configuration of FIG. As shown in the figure, the carry propagation of every 4 bits is transmitted to the higher order one after another.

FIG. 13 is a diagram in which only the 4-bit carry propagation circuit 901 shown in FIG. 10 is extracted and shown.
As described above, the operating principle of this circuit is NP beforehand.
The current is supplied to the base of the N-transistor 1011 and the NP
The N-channel transistor 1011 is turned "ON", and the current supplied from the PMOS transistor 1009 is extracted by the combination of the NMOS transistors 1000 to 1008 to suppress the base current only when the carry is propagated to the higher order. It is.

FIG. 14 is a circuit diagram showing an embodiment of the 4-bit carry propagation circuit 901 based on a concept opposite to that of the circuit of FIG. 13. The NPN transistor 1411 is turned "OFF" in advance by an NMOS transistor 1409. With the combination of PMOS transistors 1400 to 1408, N
A base current is injected into the PN bipolar transistor 1411. The circuit in FIG. 13 has a relationship with the positive logic and the circuit in FIG. 14 has a relationship with the negative logic.

13 and 14 described above, the principle is the same, and it can be said that the carry propagation method uses the current amplification property of the bipolar transistor by utilizing the carry propagation logic and switching characteristics of the MOS transistor. That is, this is a circuit system that makes use of the small amplitude operation of the base potential of the bipolar transistor, in other words, the g _m of the bipolar transistor.

FIG. 15 shows a PMOS transistor 1009 in the carry propagation circuit 901 between 4 bits of FIG.
In the embodiment of the circuit in which the resistive elements 1509 and 1510 are substituted for 1010, it is possible to obtain the same carry propagation speed as the circuit of FIG. However, in the case of FIG. 13, the PMOS transistors 1009 and 1010 can be kept in the “off” state when it is not necessary to operate the carry propagation circuit 901. Therefore, the circuit of FIG. 13 is superior in terms of power consumption. ing.

In FIG. 16, the PMOS transistor 1410 and the NMOS transistor 1409 in the 4-bit carry propagation circuit 901 shown in FIG.
This is a modified circuit replaced with 10, 1609. In this case as well, a carry propagation speed similar to that of the circuit of FIG. 14 is obtained,
For the same reason as described with reference to FIG. 15, power consumption is inferior. However, there is an advantage that the resistive element 1609 allows static operation. That is, in FIG. 14, the base potential of the NPN transistor 1411 must be dynamically lowered by the NMOS transistor 1409.
In FIG. 16, such a dynamic operation is not required.

FIG. 17 shows a modification of the NPN transistor 1011 and its connection elements in FIG. FIG. 17A is the same as that of FIG.
The transistor 1011 has a Schottky barrier diode. The reason for this is to avoid a “saturation phenomenon” that occurs when the base potential of the bipolar transistor 1011 rises above the collector potential.
FIGS. 17B, 17C, and 17D show examples in which diodes 1700 to 1702 are added to a normal NPN transistor 1711 to avoid the above-described “saturation phenomenon”. Note that FIG.
The diode 1703 shown in FIG. 9D is added to lower the collector potential of the NPN bipolar transistor 1711 and transmit it to the next stage.

FIG. 18 shows a modification of the connection element of the NPN transistor 1411 in FIG. FIG. 18A is the same as that of FIG. 16 and the NPN transistor has a Schottky barrier diode, in order to avoid the "saturation phenomenon" of the bipolar transistor as in the case of FIG. . FIG.
(B) shows an ordinary NPN transistor 181 for the same reason.
1 and diodes 1800 and 1801 to add NPN
The circuit configuration is such that the transistor 1811 is not saturated.

FIG. 19 is a circuit diagram showing a detailed circuit configuration of the data read register 404 and the data write register 405 shown in FIG.

The data read register 404 transfers data from the internal bus 109 to the memory (flip-flop) formed by the CMOS inverters 1902 and 1903 through the NMOS transistors 1904 via the data lines 423-0 to 423-3. take in. Data is read from read bus 411-0 to precharge and sense circuit 402 in the same manner as in register group 400 described above.
This is performed by the NMOS transistors 1900 and 1901 in combination.

The data write register 405
Through the data NMOS transistors 1905 mounted on the write buses 412-0 to 412-3.
It is temporarily stored in the memory (flip-flop) composed of the S inverters 1906 and 1907, and the content is 3
The state buffer 1908 sends the data to the internal bus 109 via the bus 419-0. The three-state buffer 1908 for transmitting the contents of the data write register 405 to the internal bus 109 must be in a high impedance state when data is input from the internal bus 109 to the data read register 404. Next, this 3
The configuration of the state buffer 1908 will be described with reference to the drawings.

FIG. 20 is a circuit diagram showing a three-state buffer circuit 1908 as one embodiment of the three-state circuit.

Reference numeral 2010 is an input terminal, 2011 is an output terminal, 2020 and 2021 are first and second control terminals to which complementary signals are input, Vcc is a power supply potential terminal, and G is
ND is a ground potential terminal. Reference numeral 2006 denotes a first NPN bipolar transistor in which the N-type collector is connected to the power supply potential terminal Vcc and the N-type emitter is connected to the output terminal 2011. In 2008, the N-type collector is output terminal 2
Reference numeral 011 is a second NPN bipolar transistor whose N-type emitter is connected to the ground potential terminal GND. Two
Reference numerals 000 and 2001 denote first and second PMOS transistors whose sources and drains are connected in series to the power supply potential terminal Vcc and the base of the first bipolar transistor 2006. The gate of the first PMOS transistor 2000 is connected to the first control terminal 2020, and the second PM is connected to the second PM.
The gate of the OS transistor 2001 is connected to the input terminal 2010
Respectively connected to. Reference numerals 2003 and 2004 denote first and second NMOS transistors whose drain and source are connected in series with the output terminal 2011 and the base of the second NPN bipolar transistor 2008. The gate of the first NMOS transistor 2003 is connected to the input terminal 20.
10 and the gate of the second NMOS transistor 2004 is connected to the second control terminal 2021.

In 2007, the source and the drain are connected to the source and the output terminal 2011 of the first NPN bipolar transistor 2006, and the gate is connected to the first control terminal 2020.
A third NMOS transistor connected to
Reference numeral 09 denotes a fourth NMOS transistor whose source and drain are connected to the base of the second NPN bipolar transistor 2008 and the ground potential terminal GND, and whose gate is connected to the first control terminal 2020.

Reference numeral 2002 denotes a resistor serving as a first resistive element provided between the base of the first NPN bipolar transistor 2006 and the output terminal 2011;
This is a resistor that serves as a second resistive element provided between the base of the second NPN bipolar transistor 2008 and the ground potential terminal GND.

(1) Operation as a normal buffer By setting the control signals applied to the control terminals 2020 and 2021 to “0” and “1”, respectively, the PMOS transistor 2000 and the NMOS transistor 2004 are turned “ON”.
Then, the NMOS transistors 2007 and 2009 are turned off. In this case, this circuit is equivalent to the bus driver in FIG. 8, and an output signal obtained by inverting the level of the input terminal 2010 is obtained at the output terminal 2011. Since the output signal is driven by NPN bipolar transistors 2006 and 2008, a bus having a heavy capacitive load can be charged or discharged strongly.

(2) High Impedance Operation By setting the control signals applied to the control terminals 2020 and 2021 to “1” and “0”, respectively, the PMOS transistor 2000 and the NMOS transistor 2004 are “off”.
State and the NMOS transistors 2007 and 2009
Is in the “on” state. As a result, the base-emitter potentials of the NPN bipolar transistors 2006 and 2008 become "0", so that the two NPN bipolar transistors 2006 and 2008 are turned off. Therefore, the first NPN bipolar transistor 20
06 or the discharge by the second NPN bipolar transistor 2008 cannot occur, and the output signal 2011 is in a high impedance state.

FIG. 21 is a configuration diagram of the barrel shifter 407 in the arithmetic unit 103 of FIG. In this embodiment,
As an example, a 3-bit upper-level parallel shift function is shown. The configuration for one bit is a memory (flip-flop) composed of a write NMOS transistor 2100 and CMOS inverters 2110, 2120, and NMOS transistors 2140, 215 for performing parallel shift.
0, 2160, 2170, N to determine whether to load the contents of the flip-flop on the read bus 411-0
It comprises a MOS transistor 2130. Write bus 41
The control signal 316e of the data loaded on 7-0 is "1".
Is passed through the NMOS transistor 2100 and is temporarily stored in the flip-flop. When the output of the flip-flop, that is, the output signal of the CMOS inverter 2110 is "0", the NMOS transistor 2130 is in the "OFF" state, and thus the NMOS transistor 2130 is in the "OFF" state.
NMO connected by drain 2180 to the drain of
Whichever bus of the S-transistors 2140, 2151, 2162, 2173 is selected by the control signals 314c-0 to 314c-3, the read buses 411-0 to 411-41.
In any of 1-3, the extraction of the charge does not occur. On the other hand, when the output of the above flip-flop, that is, the output signal of the CMOS inverter 2110 is "1", the following five operations are performed under the control of the control signals 314c-0 to 314c-3.

(1) Control signals 314c-0 to 314c-
When all 3 are "0", the output of the flip-flop corresponding to each bit, that is, CM
The output of OS inverters 2110 to 2113 is read bus 41
Not listed in 1-0 to 411-3.

(2) Only control signal 314c-0 is "1"
In this case, since the NMOS transistors 2140 to 2143 are turned on, the charges on the read buses 411-0 to 411-3 are stored in the NMOS transistors 2140, 2130;
1,2131; 2142, 2132; 2143, 213
It is pulled out by each bus of 3. That is, the case without the barrel shift is shown.

(3) Only the control signal 314c-1 is "1".
In the case of, since the NMOS transistors 2150 to 2153 are in the “on” state, the NMOS transistors 2151 and 213
0; 2152, 2131; 2153, 2132, the charges on the read buses 411-1 to 411-3 are extracted. That is, the case of shifting to one bit higher is shown.

(4) Only control signal 314c-2 is "1"
In the case of, the NMOSs 2160 to 2163 are turned on, so that the NMOS transistors 2162, 2130; 2163.
Read buses 411-2 to 411-3 in each bus 2131
Is extracted. That is, the shift to the upper 2 bits is performed. (5) When only the control signal 314c-3 is "1" Since the NMOS transistors 2170 to 2173 are turned on, the NMOS transistors 2173 and 2130 are turned on.
The charge of the read bus 411-3 is extracted by the bus.
That is, the shift to the upper 3 bits is performed.

In the above-described circuit configuration for realizing the barrel shift function, for example, an NMOS
Transistors 2140, 2151, 1162, 2173
Is connected, the sum of the capacitance of the wiring 2180 and the drain capacitance of each NMOS transistor becomes large.
If the L / W of the OS transistor 2130 is increased, the charge extraction speed does not decrease. Also, NMO
S-transistor 2130 provides the output of the flip-flop, ie, C
Since it is gate-controlled by the output of the MOS inverter 2110, when it is "1", the electric charge attached to the wiring 2180 is discharged before the parel shift is executed. On the other hand, the respective sources of the NMOS transistors 2140, 2150, 2160, and 2170 are connected to the read bus 411-0, which is extremely small in view of the capacity of the entire read bus 411-0.

By the way, by extracting charges from the read buses 411-0 to 411-3 at the time of the barrel shift,
The shift data is pre-charged & described in detail in FIG.
It is read at high speed by the sense circuit 402. This read speed is almost the same as the read speed of the register group 400 described above.

FIG. 22 shows another application of the carry propagation circuit according to the present embodiment shown in FIG. 10, which is an application example to a higher speed arithmetic circuit. Two sets of eight carry propagation circuits 900 shown in FIG. 10 are arranged. That is, carry propagation circuits 2200 to 2207, 2210 to 221
7 are arranged as shown in FIG. Carry propagation circuit 2200-2
207 sets are connected in series in units of two blocks from the bottom, input carry signals (signals 2240 in the lowest block) to each block, and carry propagation circuit 2
The set of 210 to 2217 is also connected in series in units of two blocks from the bottom, and the input carry signal (signal 2250 in the lowest block) to each block is fixed to the power supply side level. The meaning described above indicates the case where the former has no carry from the lower order, and the latter indicates the case where there is a carry from the lower order. That is, carry propagation is performed in parallel with and without carry from the lower order. Carry output signals 2242, 22 processed in parallel in each block of carry propagation circuits 2200-2201 and 2210-2211.
52 is input to carry generation circuit 2230. on the other hand,
Carry signal pairs 2270 and 2280 from the lower order are also input to the carry generation circuit 2230 to generate carry signal pairs 2271 and 281 to the next stage. Also,
The addition of the carry output pair 9740, 9741 and the carry signal pair 2270, 2280 from the lower order within 4 bits is performed by the half adder circuit 2220.

As described above, in the application example of FIG. 22, the critical bus when executing 32-bit addition is the carry propagation circuit 2200, 2201 or 2210, 22.
It is determined by the carry propagation time in the 8-bit block of 11, the carry propagation time of the carry generation circuits 2230, 2231 and 2232, and the addition time of the half adder circuit 2226 or 2227. Also in this application example, the units of the carry propagation circuits 2200 to 2207 and 2210 to 2217 are not fixed to 4 bits as described above, but may be connected in series with an arbitrary bit length. In addition, the carry propagation circuit 220
The block consisting of 0, 2201 or 2210, 2211 does not need to be fixed to 8 bits. Further, carry propagation circuits 2200, 2202, 220 in this application example
4, 2206 and 2210, 2212, 2214, 22
16 carry inputs are either "0" or "1"
Since these propagation circuits are fixed, the MOS transistors can be optimized and a part of the MOS transistors can be omitted, so that the size can be reduced and the speed can be further increased.

FIG. 23A shows a circuit configuration of carry generation circuit 2230 in the application example. The circuit logically functions as follows.

An 8-bit carry propagation block A (carry propagation circuit 2200-2201) and carry propagation block B (carry propagation circuit 2210-2211) carry output signal pair to the next stage according to the state of carry output signals (2242 and 2252). (2271, 281) are generated.

(1) Carry input signal pair (2270,
2280) is "0, 1" (with carry) and the carry output signals (2242, 2252) of blocks A and B are "0, 0" (without carry): The carry occurrence to the higher order is reported as no carry. And the carry output signal pair (2
271 and 281) become “1,0”.

(2) Carry input signal pair (2270,
2280) is "0, 1" (there is a carry from the lower order) and the carry output signals (2242, 222) of blocks A and B
52) is "0, 1" (carry occurs to the next stage if there is a carry from the lower order): Same as the above item (1).

(3) Carry input signal pair (2270,
2280) is "0, 1" (there is a carry from the lower order) and the carry output signals (2242, 222) of blocks A and B
When 52) is "1,0": Such a case does not logically exist.

(4) Carry input signal pair (2270,
2280) is "0, 1" (there is a carry from the lower order) and the carry output signals (2242, 222) of blocks A and B
52) is "1,1" (a carry is present in the higher order irrespective of the carry from the lower order): It is necessary to generate a carry in the upper order, and the carry output signal pair (2271, 228)
1) becomes "0, 1".

As described above, the carry input signal pair (2270,
2280) is "0,1", but "1,0"
In the case of (no carry from the lower order), the explanation will be as follows corresponding to the above four types.

The carry output signal pair (2271, 228)
1) In the case of (1): "1, 0" In the case of (2): "1, 0" In the case of (3): Logically does not exist.

In the case of (4): "0, 1" FIGS. 23 (b) and 23 (c) show an example in which the gates 2240 and 2401 in the carry generation circuit 2230 are constituted by CMOS transistors, and FIGS. ) Shows an example constituted by a composite circuit of gate 2400, 2401 rod NPN bipolar transistors and CMOS transistors in the carry generation circuit. Since the carry output signal pairs 2271 and 2821 of carry generation circuit 2230 have a large capacitive load, higher speed can be achieved in FIGS. 23 (d) and 23 (e) in which the dependency of the capacitance on the delay time is small.

FIG. 24 shows the carry propagation circuit 900 described above.
21 shows a configuration of a half adder circuit 2220 in the adder circuit of the application example of FIG. It is a 4-bit half adder circuit,
The signal 2260 corresponding to the exclusive OR output of the preceding stage from the carry propagation circuit 900 in FIG. 9, the function of performing half addition by the carry outputs 9740 and 9741 from the blocks A and B and the selection of the addition result by the carry input signals 2270 and 2280. Have.

In the embodiment described above, it can be easily considered that the present invention can be applied even if the conductivity type is reversed.

[0105]

As described above, according to the present invention, a high-speed arithmetic unit and arithmetic circuit can be obtained.

Further, according to the present invention, a highly integrated arithmetic unit and arithmetic circuit can be obtained.

Further, according to the present invention, it is possible to obtain a low power consumption arithmetic unit and arithmetic circuit.

Further, according to the present invention, it is possible to obtain a high speed and low power consumption 3-state circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processor showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a micro program control unit.

FIG. 3 is a configuration diagram of a micro instruction decoder unit.

FIG. 4 is a diagram showing a configuration of an arithmetic unit showing one embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of an arithmetic unit showing one embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of an arithmetic unit showing an embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of an arithmetic unit showing an embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 13 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 14 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of an arithmetic unit showing an embodiment of the present invention.

FIG. 16 is a diagram showing a configuration of an arithmetic unit showing one embodiment of the present invention.

FIG. 17 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 18 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 19 is a diagram showing a configuration of an arithmetic unit showing an embodiment of the present invention.

FIG. 20 is a diagram showing a configuration of an arithmetic unit showing an embodiment of the present invention.

FIG. 21 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 22 is a diagram showing a configuration of an arithmetic unit showing one embodiment of the present invention.

FIG. 23 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 24 is a diagram showing a configuration of an arithmetic unit showing one embodiment of the present invention.

FIG. 25 is a diagram showing a configuration of an arithmetic unit showing one embodiment of the present invention.

FIG. 26 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 27 is a diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

[Explanation of symbols]

100 processor, 101 microprogram control unit, 102 microinstruction decoder unit, 1
03: arithmetic unit, 403: arithmetic circuit.

Front page continuation (72) Inventor Masahiro Iwamura 3-1-1 Sachimachi, Hitachi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (3)

[Claims] 1. An input terminal and an output terminal, (2) first and second control terminals having complementary inputs, (3) first and second potential terminals, and (4) one conductivity type collector. A first bipolar transistor having one conductivity type emitter connected to the output terminal at the first potential terminal; (5) one conductivity type collector at the output terminal; and one conductivity type emitter at the second A second bipolar transistor connected to the potential terminal of (6), one gate of which is connected to the input terminal and the other gate of which is connected to the first control terminal,
And a first and second other conductivity type field effect transistor whose source and drain are connected in series to the first potential terminal and the other conductivity type base of the first bipolar transistor, (7) Has a gate connected to the input terminal, the other gate connected to the second control terminal, and a drain and a source connected in series to the output terminal and the other conductivity type base of the second bipolar transistor. (1) the first and second one conductivity type field effect transistors, wherein the source and the drain are the first
A field effect transistor whose gate is connected to the base of the bipolar transistor and the output terminal, the gate being connected to the first control terminal or the second control terminal, and (9) the source and drain being the second bipolar transistor. The gate is connected to the base of the transistor and the second potential terminal, and the gate is connected to the first potential terminal.
A fourth field-effect transistor connected to the control terminal or the second control terminal of the first bipolar transistor, (10) a first resistive element provided between the base of the first bipolar transistor and the output terminal, 11) A three-state circuit comprising: a second resistive element provided between the base of the second bipolar transistor and the second potential terminal. 2. The three-state circuit according to claim 1, wherein the field-effect transistor is a MOS transistor. 3. A three-state circuit according to claim 1, wherein the resistive element is a resistor.