JPH088737A - Frequency synthesizer - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a frequency synthesizer capable of quickly and accurately producing a frequency signal with a simple configuration. A phase comparing means 12 for comparing a phase difference between a reference input frequency signal and an output frequency signal, and a delay means 14 for delaying a comparison output of the phase comparing means 12 for a predetermined time corresponding to the input frequency. The subtraction means 15 for subtracting the output of the delay means 14 from the comparison output, the division means 16 for dividing the subtraction output of the subtraction means 15 by the value corresponding to the predetermined time, and the output of the division means 16 are smoothed. And the output of this low-pass filter is supplied as a control voltage and the output frequency signal is compared with the phase comparison means 12
And a voltage controlled oscillator which supplies the

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer for producing a predetermined frequency signal.

[0002]

2. Description of the Related Art Conventionally, a PLL circuit (phase locked loop circuit) has been generally used as a frequency synthesizer for producing a desired frequency signal. This P
The frequency synthesizer using the LL circuit detects the phase difference between the reference frequency signal and the frequency signal output by the voltage controlled oscillator, and controls the voltage controlled oscillator so that the phase difference disappears.

[0003]

By the way, the PLL circuit has a disadvantage that the loop response of the circuit becomes a secondary response, and in particular, the output frequency cannot be varied at high speed in some cases.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a frequency synthesizer capable of rapidly producing an accurate frequency signal with a simple structure.

[0005]

The present invention is, for example, as shown in FIGS. 1 and 2, phase comparing means 12 for comparing the phase difference between a reference input frequency signal and an output frequency signal,
A delay means 14 for delaying the comparison output of the phase comparison means 12 for a predetermined time corresponding to the input frequency; a subtraction means 15 for subtracting the output of the delay means 14 from the comparison output.
A dividing means 16 for dividing the subtracted output of the subtracting means 15 by a value corresponding to the predetermined time, a low-pass filter 3 for smoothing the output of the dividing means 16, and an output of the low-pass filter 3 are supplied as a control voltage. And a voltage controlled oscillator 4 for supplying the output frequency signal to the phase comparison means 12.

In this case, a digital filter is used as the low pass filter 3.

Further, in the above-mentioned case, as shown in FIG. 4, for example, the analog filter 2 is used as the low-pass filter 3.
Integrating means 3 for integrating the output of the dividing means 16 using 3
0 and subtraction means 21 for subtracting the integrated value output of the integration means 30 from the output of the division means 15 are provided to compensate the integration operation of the low-pass filter 3.

[0008]

According to the present invention, the change in the phase difference is directly performed in the cycle corresponding to the reference frequency, and the voltage controlled oscillator immediately outputs the frequency signal directly locked to the reference frequency.

In this case, by using a digital filter as the low pass filter, the circuit structure of the frequency synthesizer becomes simple.

Further, an analog filter is used as the low-pass filter, and an integrating means for integrating the output of the dividing means and a subtracting means for subtracting the integrated value output of the integrating means from the output of the dividing means are provided, and the voltage control is performed. By performing integral compensation on the control voltage of the oscillator, the integral operation of the low-pass filter is compensated, and high-speed synchronization with the desired frequency is achieved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing the overall configuration of the frequency synthesizer of this embodiment. In the figure, reference numeral 1 denotes a reference frequency signal input terminal, and a reference frequency signal from a reference oscillator (not shown) is provided at this input terminal 1. (hereinafter referred to as the reference frequency signal f _r) are supplied. And provides a reference frequency signal f _r obtained at the input terminal 1, the frequency comparator 2. The frequency comparator 2, the frequency of the reference frequency signal f _r, the comparator for comparing the frequency of the oscillation output f _v of the voltage controlled oscillator 4 to be described later, will be described later that configuration.

The comparison output of the frequency comparator 2 is supplied to a voltage controlled oscillator (VCO) 4 via a low pass filter 3 as a loop filter. Here, for example, a digital filter is used as the low-pass filter 3 to smooth the comparison output. Then, the oscillation output f _v of the voltage controlled oscillator 4 is supplied to the frequency signal output terminal 5 of this frequency synthesizer and to the frequency comparator 2.

Next, the configuration of the frequency comparator 2 of this example will be described. FIG. 2 is a diagram showing the configuration of the frequency comparator 2 of this example,
A reference frequency signal f _r obtained at the input terminal 1, the terminal 13
The oscillation output f _v of the voltage controlled oscillator 4 obtained in the above is supplied to the phase comparator 12. The phase comparator 12 has a phase θ _r (t) of the reference frequency signal _{fr and} a phase θ of the oscillation output f _v .
_The phase difference θ _r (t) −θ _v (t) is detected by comparing with _v (t). Here, this phase difference θ _r (t) −θ _v (t) is _defined as a phase difference signal θ _rv (t).

Then, the detected phase difference signal θ_rv(t)
The signal is supplied to the subtractor 15 via the delay circuit 14 and
It is supplied to the contact subtractor 15 and directly from the phase comparator 12.
Subtract the delayed phase difference signal from the phase difference signal
It Here, the delay time of the delay circuit 14 is the reference frequency signal.
No. f_rOf the reference frequency signal f
_rTime T corresponding to one cycle of_r[Seconds] and this delay time
Time T on road 14_rThe phase difference signal delayed by θ_rv(T
-T_r). Therefore, the subtraction output of the subtractor 15 is θ_rv
(t) − θ_rv(T-T_r).

Then, the subtraction output of the direct subtractor 15 is supplied to the divider 16, and the subtraction output is divided by the delay time _Tr in the delay circuit 14 described above to obtain the frequency difference signal _frv . Therefore, the frequency difference signal _frv is obtained by the calculation of the following equation.

[0017]

## EQU1 ## f _rv = [θ _rv (t) −θ _rv (t−T _r )] / T _r

Then, the frequency difference signal _frv obtained by the divider 16 is supplied to the terminal 17, and is supplied from the terminal 17 to the voltage controlled oscillator 4 (see FIG. 1) via the low pass filter 3 as a control voltage. To do.

With the frequency synthesizer configured as described above, the voltage controlled oscillator 4 is directly synchronized with the frequency signal obtained at the input terminal 1, and the output frequency signal can be satisfactorily obtained. That is, assuming that the characteristic f (s) of the low-pass filter 3 is f (s) = 1 / s, the loop response of this frequency synthesizer is given by the following equation.

[0020]

[Equation 2]

As can be seen from this equation, the loop response of this frequency synthesizer can be obtained as a first-order loop. FIG. 3 is a diagram showing the phase / frequency response of the frequency synthesizer of this example, showing the response waveform when the sampling period is T _r . This figure is a diagram showing an initial phase difference between the reference frequency signal f _r and the oscillation output f _v 0, the phase difference signal detected by the phase comparator 12 in the frequency comparator 2 theta _rv
It can be seen that the oscillation output f _v of the voltage controlled oscillator 4 stabilizes at a predetermined frequency (that is, the reference frequency) as the value converges to 0.

As described above, according to the frequency synthesizer of the present embodiment, the frequency synthesizer is directly synchronized with the reference frequency signal, and the loop response becomes a primary loop, and a secondary loop response circuit like a conventional PLL circuit is obtained. In comparison, it becomes easier to analyze the oscillation conditions of the circuit, and it becomes easier to set the characteristics of each circuit constituting the frequency synthesizer.

Next, another embodiment of the frequency synthesizer of the present invention will be described with reference to FIGS. This Figure 4
In addition, in FIG. 5, parts corresponding to those in FIGS. 1 to 3 described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, an analog filter is used as the loop filter, and an integral compensation circuit is provided to compensate the integral operation of the loop filter. That is, in this example, the frequency difference signal output from the frequency comparator 2 is supplied to the subtractor 21, and the subtractor 21 subtracts the output of the loop filter integration compensation circuit 30 described later from the frequency difference signal, and the subtracted output is sampled. / Hold circuit 22
Supply to.

The sample / hold circuit 22 comprises an operational amplifier 22a, a switch S1 and a capacitor C1, and the switch S1 is closed at the sampling timing,
This is a circuit in which the capacitor C1 is charged and the sampling value is held, and the held voltage signal is supplied to the analog low-pass filter 23 and the loop filter integral compensation circuit 30.

The loop filter integration / compensation circuit 30 is composed of a sample / hold circuit 31 and an integrator 32. The output of the sample / hold circuit 22 is sampled and integrated, and the integrated value of the integrator 32 is sent to the subtractor 21. Supply.

Further, the analog low-pass filter 23
Is composed of an operational amplifier 23a and a resistor R1 and a capacitor C2 connected to the periphery of the operational amplifier 23a. The sample / hold circuit 22 is an analog operation by the capacitor C2.
The output of is smoothed.

The output of the low pass filter 23 is supplied to the voltage controlled oscillator 4 as a control voltage. The other parts are configured similarly to the frequency synthesizer shown in FIGS.

Next, the operation of the circuit shown in FIG. 4 will be described with reference to FIG.
The operation timing chart of FIG. First, the potential of the frequency difference signal f _rv frequency comparator 2 outputs a VΔθ, V∫ the output potential of the loop filter integral compensation circuit 30
Then, the potential of the signal obtained by the subtraction in the subtractor 21 (that is, VΔθ−V∫) is Vf. Then, the output potential Vf of the subtractor 21 is set to Vf _{1 which} is a potential sampled by the sample / hold circuit 22, and V _VCO is the control voltage smoothed by the low pass filter 23.

If the sample / hold circuit 22 performs sampling every period T, when the reference frequency signal and the output signal of the voltage controlled oscillator 4 do not match in frequency, each potential is changed in the state shown in FIG. Change. That is,
When sampled at the period T, it is assumed that VΔθ (T) = V ₁ . Then, if the integral value V∫ (T) = 0 at this time, the subtraction output Vf (T) of the subtractor 21 becomes VΔθ (T), and this potential is Vf _{1 in the} sample / hold circuit 22.
Hold as (T). The loop filter 23 performs an integration operation by the held voltage to obtain the control voltage V _VCO of the voltage controlled oscillator 4.

As shown in FIG. 5, when the output potential VΔθ of the frequency comparator 2 is changing, a predetermined output potential V∫ is generated from the loop filter integral compensation circuit 30,
The subtraction output Vf of the subtractor 21 becomes constant at a predetermined potential V ₁ , and the control voltage V _VCO of the voltage controlled oscillator 4 stabilizes at a constant value.

As in the case of the circuits shown in FIGS. 1 and 2, the circuit shown in FIG. 4 is directly synchronized with the frequency signal obtained at the input terminal 1, and the loop response becomes a primary loop, which is a good characteristic. At the same time, since the integral operation of the loop filter is compensated, the time until the oscillation output of the voltage controlled oscillator stabilizes is very short, and the frequency signal synchronized with the reference input signal can be created at higher speed.

[0033]

According to the present invention, the change of the phase difference is directly performed in the cycle corresponding to the reference frequency, and the voltage controlled oscillator immediately outputs the frequency signal directly locked to the reference frequency.

In this case, using a digital filter as the low-pass filter simplifies the circuit configuration of the frequency synthesizer.

Further, an analog filter is used as the low-pass filter, and an integrating means for integrating the output of the dividing means and a subtracting means for subtracting the integrated value output of the integrating means from the output of the dividing means are provided, and the voltage control is performed. By performing integral compensation on the control voltage of the oscillator, the integral operation of the low-pass filter is compensated, and high-speed synchronization with the desired frequency is achieved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a frequency comparator of one embodiment.

FIG. 3 is a characteristic diagram showing a phase / frequency response of a circuit of an example.

FIG. 4 is a configuration diagram showing another embodiment of the present invention.

FIG. 5 is a characteristic diagram showing the operation timing of another embodiment.

[Explanation of symbols]

 1 Reference Frequency Signal Input Terminal 2 Frequency Comparator 3 Low Pass Filter 4 Voltage Controlled Oscillator (VCO) 5 Frequency Signal Output Terminal 12 Phase Comparator 14 Delay Circuit 15 Subtractor 16 Divider 22 Sample / Hold Circuit 23 Analog Low Pass Filter 30 Loop filter Integral compensation circuit 31 Sample / hold circuit 32 Integrator

Claims (3)

[Claims] 1. A phase comparison means for comparing a phase difference between a reference input frequency signal and an output frequency signal, a delay means for delaying a comparison output of the phase comparison means by a predetermined time corresponding to the input frequency, and Subtraction means for subtracting the output of the delay means from the comparison output, division means for dividing the subtraction output of the subtraction means by a value corresponding to the predetermined time, and a low-pass filter for smoothing the output of the division means, A frequency synthesizer comprising: a voltage controlled oscillator to which an output of the low pass filter is supplied as a control voltage and which supplies an output frequency signal to the phase comparison means. 2. The frequency synthesizer according to claim 1, wherein a digital filter is used as the low-pass filter. 3. An analog filter is used as the low-pass filter, and an integrating means for integrating the output of the dividing means and a subtracting means for subtracting the integrated value output of the integrating means from the output of the dividing means are provided. 2. The frequency synthesizer according to claim 1, wherein the integrating operation of the low-pass filter is compensated.