JPH0887452A - Storage capacity expansion method for storage device - Google Patents

Abstract

(57) [Abstract] [Purpose] The purpose is to maintain the program compatibility on virtual machines without changing the addressing hardware architecture and to expand the capacity of storage devices. [Configuration] In order to select the storage modules 1 to N, a floating address register designating register (hereinafter, designated register) array 660 is provided with a designated register for each area ID assigned to a virtual machine, Floating address registers (hereinafter referred to as registers) 0 to n are associated with a maximum number of addresses that can be specified up to the maximum address specified by the architecture of the actual computer, the specified register is selected by the value of the area ID, and the contents are specified in the specified register. The register is selected by a value obtained by adding the upper address of the storage device address to the register number corresponding to the start address of the storage area of the corresponding virtual computer, the storage module number fetched is sent to the storage device, and selected by the number. Access the storage module at a lower address of the storage device address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus,
In particular, an information processing device in a form in which the storage device of the information processing device is logically divided into a plurality of storage regions, and the divided storage regions are allocated to the logical storage device of the virtual machine operating on the information processing device and used. The present invention relates to a capacity expansion method for storage devices.

[0002]

2. Description of the Related Art Generally, as a method of operating a plurality of operating systems (hereinafter referred to as OS) on a single information processing apparatus, a means called a virtual machine (hereinafter referred to as VM or LPAR) is used. In order to realize LPAR on a single information processing device, a program called a virtual computer control program (hereinafter referred to as hypervisor) is operated on the real information processing device, and a plurality of LPARs are generated under the control of this hypervisor. In addition, an independent OS was operated on each LPAR. Therefore, the hypervisor is provided with a function of allowing each LPAR to share and use the hardware resources of a single real information processing device. As a method of sharing the hardware resources of a single real information processing device among the LPARs,
A method of time-divisionally allocating hardware resources under the control of a hypervisor, a method of logically allocating hardware resources and allocating them exclusively to each LPAR, a method of allocating a mixture of the above two methods, etc. There is.

Next, a conventional technique will be described with reference to FIG.
FIG. 1 shows one real central processing unit (hereinafter referred to as PIP)
And a real storage device (hereinafter referred to as RMS) on a real computer, one logical central processing unit (hereinafter referred to as LIP)
And one logical storage device (hereinafter referred to as LMS)
3 shows an example of a computer system in which three sets of LPARs, which are virtual computers consisting of and, are generated, and each set is configured to operate independently. Such a computer system is called a virtual computer system, and each set as described above is called a virtual computer (VM or LPAR). In the system of FIG. 1, three LPAR systems are constructed on one real computer, a hypervisor runs on the PIP, and each LPAR operates independently under the control of the hypervisor. The processing function of the LIP belonging to each LPAR is controlled by the PIP under the control of the hypervisor.
Is realized by being time-divided with the hardware resources of the LMS, and the storage function of the LMS belonging to each LPAR is logically divided into the real storage area of the RMS under the control of the hypervisor and occupied by each LPAR. It has been realized by allocating each of the LPARs to each LPAR by logically dividing the virtual storage area created by the hypervisor on the RMS.

FIG. 2 shows PIP, LPAR, LIP and LM.
The relationship between S and RMS is shown. In FIG. 2, PIP21
A hypervisor that operates on 0 uses the hardware resources of the PIP 210 in a time-sharing manner, LPARA2 that is a virtual machine.
21, LPARB 222, and LPARC 223 for control, and virtual computers LPARA 221 and LP
The ARB 222 and the LPARC 223 are composed of LIPA 231, LIPB 232, and LIPC 233, respectively, as logical central processing units. LIPA231, LI
The PB 232 and the LIPC 233 operate independently and access the RMS 240 independently. RMS240
Is logically divided into three areas, each of which is LPARA
221, LPPARB 222 and LPARC 223 are used in correspondence with the LPARA area 241 and LP, respectively.
It is composed of an ARB area 242 and an LPARC area 243. When the RMS 240 is logically divided into three areas, the hypervisor gives the starting address of the storage area and the size of the storage area for each LPAR.

In FIG. 2, LIPA 231 is LPAR.
Only area A 241 can be accessed and LIPB 232 is L
Only PARB area 242 can be accessed, and further LIP
The C233 can access only the LPARC area 243. Here, the LPAR to which the LPAR is actually assigned
The R area is accessed by the LPAR being activated by the operator (activating the virtual computer, which is equivalent to powering on the real computer), and any software runs on the LPAR. That is the case. Activation is the actual L
It is to allocate IP and LMS and initialize LPAR so that software can operate on LPAR. A hypervisor operating on the PIP and controlling each LPAR can access the entire area of the RMS 240.

[0006] Next, referring to FIG.
An example of logical division according to AR will be described. Figure 3 shows R
In this example, the MS is logically divided into six LPARs and assigned. 6 LPARs are LPAR1 and LP
AR2, LPAR3, LPAR4, LPAR5 and LP
It is composed of AR6, all LPARs are activated, and LPAR1 region 301 and LPA of RMS are respectively activated.
R2 region 302, LPAR3 region 303, LPAR4 region 304, LPAR5 region 305 and LPAR6 region 3
06 is allocated and used from each LPAR. The LPAR6 area 306 has a storage area starting point (hereinafter referred to as STRORG) having a value of “0”, and its storage range (hereinafter referred to as STREXT) has a value of “α”. That is, the LPAR6 area 306 is an area from the storage address “0” to the storage address “α-1” in the RMS. In the LPAR5 region 305, its STRORG is'α '
Has a value of STREXT has a value of'β ', and L
The PAR5 area 305 is an area from the storage address “α” to the storage address “β-1” in the RMS. Similarly, LP
AR4 region 304, LPAR3 region 303, LPAR2
The area 302 and the LPAR1 area 301 are STRORG
'Α + β', 'α + β + γ', '
has α + β + γ + δ 'and'α + β + γ + δ + ε',
The values of STREXT are'γ ',' δ ','
It has ε'and'ζ '.

As described above, each LPA according to the prior art
In the RMS logical partitioning method for R, the maximum capacity of the RMS can be configured up to the maximum address that can be specified and defined by the hardware architecture of the actual information processing device. For example, if the length of the address data defined by the hardware architecture of the actual information processing device is 31 bits, the maximum storage capacity that can be specified was 2 gigabytes. Therefore, in FIG. 3, from LPAR1 to LPAR
The total storage capacity up to 6 is RMS
Can not exceed the storage capacity installed as
The maximum storage capacity that can be installed as an RMS has a limitation that the maximum address specified by the addressing hardware architecture of the actual information processing device is the upper limit.

As described above, each LPA according to the prior art
In the RMS logical partition allocation method for R, there is a problem that the total storage capacity of the activated LPAR cannot exceed the storage capacity installed as the RMS.
There is a problem in that even if an attempt is made to allocate a storage area having a larger capacity in order to sufficiently bring out the performance of the OS operating on each R, it cannot be allocated due to the above-mentioned restrictions. This has been a non-negligible problem in improving the system performance and expanding the system.

Next, referring to FIG. 4, one storage module of a plurality of storage modules constituting the storage device is selected from the storage device addresses in the prior art, and the storage data is accessed. The procedure and configuration will be described. FIG. 4 is a block diagram of a storage module selection device at the time of accessing a storage device, which is a conventional technique. As shown in this figure, a method using a floating address register is known as a conventional technique for accessing an arbitrary area of a storage device from a storage device address. As a typical means for accessing an arbitrary area of the storage device from the storage device address via the floating address register, there is, for example, the method described in US Pat. No. 4,280,176. In FIG. 4, the storage device address is input from the signal line 4A1, and the signal line 4A1 is connected to the latch A410. The latch A410 is a relay latch that receives the signal line 4A1 as an input and temporarily stores the storage device address sent via the signal line 4A1. The latch A410 stores the selector 420 and the memory via the signal line 4A2 and the signal line 4A3. Module 0
450, storage module 1 451, storage module 2
452 and storage module N 453 and other storage modules. The selector 420 receives a part of the storage device address, which is the output of the latch A410 sent via the signal line 4A2, as an input, and selects a plurality of floating address registers of the floating address register group 430. It is a selector that selects one of the floating address registers. The selector 420 further includes
It is connected to the floating address register group 430 via the signal line 4A4.

The floating address register group 430 is composed of a plurality of floating address registers, and a plurality of floating address register groups 430 are constituted by a floating address register selection instruction signal sent via a signal line 4A4. One of the floating address registers is selected and latched by the latch B4 via the signal line 4A5.
40 sends the contents of the selected floating address register. The latch B440 is a relay latch that temporarily stores the contents of the selected floating address register of the floating address registers of the floating address register group 430 sent via the signal line 4A5. 4A6 is connected to a plurality of storage module groups such as a storage module 0 450, a storage module 1 451, a storage module 2 452, and a storage module N 453. The write instruction and write data to the storage device are connected to a plurality of storage module groups such as the storage module 0 450, the storage module 1 451, the storage module 2452, and the storage module N 453 via the signal line 4A7. The read data from the storage device is sent out via a signal line 4A8 connected to a plurality of storage modules such as the storage module 0 450, the storage module 1 451, the storage module 2 452, and the storage module N 453, respectively. that's all,
A configuration of a storage module selecting device at the time of accessing the storage device when selecting one storage module from a plurality of storage modules configuring the storage device from the storage device address in the prior art and accessing the storage data will be described. did.

Next, details of the contents of the floating address registers forming the floating address register group 430, which is a conventional technique, will be described with reference to FIG. FIG. 5 is a diagram showing the contents of the respective floating address registers constituting the floating address register group 430. Each entry of the floating address register is composed of two fields, a V field indicating whether the entry of the floating address register is valid or invalid and a storage module number field. If the entry of the floating address register is valid, the contents of the storage module number field in the entry of the floating address register of the floating address register group 430 are latched through the signal line 4A5 to the latch B.
To 440. If the entry of the floating address register is valid, it is latched by the latch B 440, and if the entry of the floating address register is invalid, a signal indicating that there is a program interrupt factor of the addressing exception is sent to the central processing unit. To do. The entry of the floating address register of the floating address register group 430 is 1
One entry is provided for each storage module, and the number of storage modules is determined by the storage capacity of one storage module and the maximum storage capacity of the storage device. For example, if the storage capacity of one storage module is 4 megabytes and the maximum storage capacity of the storage device is 2 gigabytes, the number of storage modules is 512, and the number of floating address registers constituting the floating address register group 430 is The number of entries is also composed of 512. The procedure and configuration for selecting one storage module from a plurality of storage modules constituting the storage device based on the storage device address in the prior art and accessing the storage data have been described above.

Details of the storage module selection process will be described below with reference to FIGS. 4 and 5. In Figure 4, PI
A storage device access from P is issued with a storage device address. The memory device address is input to the latch A410 via the signal line 4A1.

The latch A410 is a relay latch which receives the signal line 4A1 as an input and temporarily stores a predetermined storage device address sent via the signal line 4A1.
The upper part of the storage device address value latched in 410 is sent to the selector 420 via the signal line 4A2. At the same time, the lower part of the value of the storage device address latched by the latch A 410 is stored in the storage module 0 45.
0, storage module 1 451, storage module 2 45
2 and a plurality of storage modules such as the storage module N 453 are sent via the signal line 4A3. Selector 4
The reference numeral 20 designates one of a plurality of floating address register entries constituting the floating address register group 430, using the value of the upper part of the storage device address value sent via the signal line 4A2. An instruction to select an entry of the floating address register is issued to the floating address register group 430 via the signal line 4A4. The floating address register group 430 uses the value sent via the signal line 4A4 to select the corresponding one of the floating address register entries, and the contents of the floating address register entry are sent via the signal line 4A5. And sends it to the latch B440. The latch B440 is sent via the signal line 4A5,
Latches the contents of the selected floating address register entry of the floating address register entries of the floating address register group 430 and checks whether the V field of the floating address register entry is valid or invalid. To do. If the V field of the selected floating address register entry is invalid, a program interrupt cause of an addressing exception is generated and this memory access operation is interrupted. The invalid V field of the entry of the floating address register indicates that the corresponding storage area is not allocated to the storage module. V of the selected floating address register entry
When the field is valid, the latch B440 is connected to the signal line 4
Floating address register group 4 sent via A5
Latch the storage module number which is the content of the entry of the selected floating address register among the plurality of 30 floating address registers in the latch B 440. Latch B4
The storage module number latched by 40 is the signal line 4A.
6 is sent to a plurality of storage module groups such as the storage module 0 450, the storage module 1 451, the storage module 2 452, and the storage module N 453. The storage module number sent via the signal line 4A6 is received by a plurality of storage module groups, and only one storage module given the same number as the storage module number is allowed to access the storage device, The storage device access operation is executed.

As described above, using the floating address register from the storage device address according to the prior art, one storage module is selected from a plurality of storage modules constituting the storage device, and the stored data access procedure and In the configuration, the area ID, which is the identifier of the virtual machine, does not participate in the control procedure, and the maximum capacity of the RMS that can be specified is
Up to the maximum address specified by the hardware architecture of the actual information processing device. Therefore, multiple LPARs
The total storage capacity of the allocated storage capacity to the RMS could not exceed the RMS maximum storage capacity limited by the maximum address specified by the hardware architecture of the actual information processing apparatus.

[0015]

Using the floating address register from the storage device address of the prior art, one storage module is selected from a plurality of storage modules constituting the storage device and the storage data is accessed. In the storage module selection device of the procedure and the configuration, the maximum capacity of the RMS that can be specified can be specified only up to the maximum address specified by the addressing hardware architecture of the actual information processing device. Therefore, the total storage capacity of the allocated storage capacities to the plurality of LPARs cannot exceed the maximum storage capacity of the RMS limited by the maximum address specified by the addressing hardware architecture of the real information processing device. The total storage capacity of the activated one or more LPARs is RM specified by the maximum address specified by the addressing hardware architecture of the actual information processing device.
The limitation that the maximum storage capacity of S cannot be exceeded is
This means that if a larger storage area is to be allocated in order to fully bring out the performance of each OS operating on a plurality of LPARs, it may not be possible to allocate due to this limitation. As a result, there is a problem in that the performance of each OS operating on a plurality of LPARs cannot be sufficiently obtained. This problem was a serious problem that cannot be ignored in ensuring the performance of the virtual computer system.

In addition, the maximum address defined by the addressing hardware architecture of the actual information processing device is
R can be specified by increasing the data width of the address
Increased maximum MS capacity, resulting in multiple LPARs
Although it is naturally conceivable to increase the total storage capacity allocated to the real information processing apparatus, this means requires changing the addressing hardware architecture of the real information processing apparatus, However, there is a problem that the program that was running on the addressing hardware architecture of does not work as it is, and there is a big problem from the viewpoint of maintaining the compatibility of the program. In order to widen the data width of the storage device address specified by the hardware architecture, it is necessary to add a signal line for transferring the storage device address by hardware logic. As a result, a huge amount of hardware logic is required. Need to be added, which significantly increases the development and manufacturing costs of information processing equipment. There is an industrial problem in the manufacture of industrial products that pressurized been a major problem which can not be ignored this industrial problem.

An object of the present invention is to solve the above-mentioned problems of the prior art by maintaining the compatibility of programs operating on the LPAR without changing the addressing hardware architecture of the actual information processing device. Realizing the expansion of the capacity of the storage device while suppressing the dramatic increase in the hardware logic of the information processing device without adding the data width of the storage device address specified by the addressing hardware architecture of the actual information processing device. The purpose of the present invention is to provide a capacity expansion method that accompanies logical partitioning of a storage device, while suppressing industrial costs and being flexible in improving system performance.

[0018]

To achieve the above object, the present invention comprises a central processing unit and a storage device, and storage of the storage device in an information processing unit in which a plurality of virtual machines operate on the central processing unit. In the capacity expansion system, the storage device is composed of a plurality of storage modules, and the central processing unit of the virtual computer issues the storage device address by issuing an area ID and a storage device address which are identifiers of the virtual computer. Issued by the central processing unit of the virtual machine which is accessed and comprises a floating address register designation register which is provided corresponding to the area ID and holds a storage capacity of the storage area and a floating address register number corresponding to the start address of the storage area. Receiving the selected area ID, selecting the floating address register designation register corresponding to the area ID, and holding contents of the selected register A floating address register designation register array for outputting, a floating address register group including a plurality of floating address registers provided with the number of the plurality of storage modules and holding storage module numbers, and output from the floating address register designation register array. A floating address register number corresponding to the start address of the storage area and an upper address of the issued storage device address, and a floating address register from the floating address register group based on the output of the adding means. When the storage device access is requested by the central processing unit of the virtual computer and the area ID and the storage device address are issued, the output of the adding unit is provided. Based on the So that access to the storage device by the subordinate address of the issued memory address and memory module number which is the content held in the floating address register. In addition, the storage capacity of the storage area of the contents held in the floating address register designating register selected and output from the floating address register designating register array by the area ID which is the identifier of the virtual machine issued by the central processing unit of the virtual machine. The virtual machine central processing unit is provided with a comparing means for comparing with a higher address of a storage device address, and when the higher address of the storage device address is out of the storage capacity of the storage area, the comparing means is an address. The designated program exception factor is sent to the central processing unit of the virtual computer that accessed the storage device. Further, the floating address register designation register array is
When D is specified and the storage capacity of the storage area or the floating address register number corresponding to the start address of the storage area or both are input, the contents held in the floating address register specification register specified by the area ID are changed. I am trying to change it dynamically.

[0019]

By the above means, a plurality of floating address register designation registers having a function of selecting a plurality of sets of floating address registers for selecting a storage module are LP
The floating address register designation register is provided with each area ID assigned to the AR, and the floating address register designation register is provided with a storage range field and a leading floating address register number field, respectively. By storing as many floating address register groups as can be specified up to the maximum address specified by the hardware architecture, each of the plurality of LPARs stores up to the maximum address specified by the addressing hardware architecture of the actual information processing device. The device is ready for use. As a result, without changing the addressing hardware architecture of the actual information processing device that constitutes the storage device, the entire information processing device has a storage capacity exceeding the maximum storage capacity specified by the basic addressing hardware architecture of the information processing device. It is possible to realize a function that allows a device to be simultaneously and actively accessed from a plurality of LPARs. Further, the compatibility of programs operating on the LPAR is maintained, and it is not necessary to add the data width of the storage device address defined by the addressing hardware architecture of the information processing device, so that the hardware logic of the information processing device is Suppressed the dramatic increase of
It is possible to realize a storage device expansion method, suppress an industrial cost increase, and realize a storage device expansion method that improves the performance of each virtual computer system.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a capacity expansion system for a storage device according to the present invention will be described in detail below with reference to the drawings. FIG. 6 shows that one storage module is selected from a plurality of storage modules constituting the storage device by using the floating address register designation register and the floating address register from the storage device address that is one embodiment of the present invention, and the storage is performed. It is a logic block diagram which shows the hardware details of the memory module selection mechanism which accesses data.

In FIG. 6, each area ID (identifier given to the virtual computer) corresponding to the storage area of each LPAR is input from the signal line 6A1, and the signal line 6A1 is connected to the latch A610. ing. Also, the L
The storage address of PAR is input from the signal line 6A2, and the signal line 6A2 is connected to the latch A610. The latch A610 includes a signal line 6A1 and a signal line 6A2.
Is a relay latch that temporarily stores the area ID corresponding to the storage area of the LPAR and the storage device address of the LPAR that have been sent via the signal line 6A1 and the signal line 6A2. 6A4 and signal line 6A5
Through the floating address register specifying register array 6
60 and storage module 0 650, storage module 1
651, storage module 2 652, storage module N 653, and other storage modules. Further, the latch A 610 is connected to the comparator 670 and the adder 680 via the signal line 6B2.

The floating address register designation register array 660 has a latch A sent through the signal line 6A4.
One of the plurality of floating address register designation registers constituting the floating address register designation register array 660 is inputted with the area ID corresponding to the storage area of the LPAR, which is the output of 610, as an input. A register is selected, the contents of the floating address register designation register are read out, and sent to the signal line 6B0 and the signal line 6B1. At this time, the signal line 6B0 is
The storage range field read from the floating address register designation register is sent, and the leading floating address register number field read from the floating address register designation register is sent to the signal line 6B1.
Floating address register designation register array 660 is connected to comparator 670 via signal line 6B0 and to adder 680 via signal line 6B1.

The comparator 670 receives the storage range field of one floating address register designation register selected from a plurality of floating address register designation registers input via the signal line 6B0 and the signal input via the signal line 6B2. It is a comparator for comparing the upper data of the storage device address of LPAR, and sends the comparison result to the signal line 6B4. The adder 680 receives the leading floating address register number field of one floating address register designating register selected from the plurality of floating address register designating registers inputted via the signal line 6B1 and the signal inputted via the signal line 6B2. It is an adder that adds the upper data of the storage device address of the LPAR, and the addition result is the signal line 6B.
3 to the selector 620.

The selector 620 receives the floating address register number, which is the output of the adder 680 sent through the signal line 6B3, as an input, and selects one of the floating address registers constituting the floating address register group 630. It is a selector that selects one of the floating address registers.

The selector 620 is further connected to the floating address register group 630 via a signal line 6A6. The floating address register group 630 includes a plurality of floating address registers. The floating address register group 630 selects one floating address register of the floating address registers constituting the floating address register group 630 by the floating address register selection instruction signal sent via the signal line 6A6. Select and send the contents of the selected floating address register to latch B 640 via signal line 6A7. The floating address register group 630 further includes a signal line 6A for inputting write data to the selected floating address register.
B is also connected.

The latch B640 is a relay latch which temporarily stores the contents of the selected floating address register of the floating address register group 630, which is sent via the signal line 6A7, and via the signal line 6A8. Storage module 0 650, storage module 1 651, storage module 2 652, and storage module N 653. The write instruction and write data to the storage device are sent via the signal line 6A9.
Storage module 0 650, storage module 1
651, storage module 2652 and storage module N
It is input to a plurality of storage modules such as 653. The read data from the storage device is transmitted via a signal line 6AA connected to a plurality of storage modules such as storage module 0 650, storage module 1 651, storage module 2 652, and storage module N 653, respectively. As described above, one detailed implementation of the hardware of the storage module selection device that selects one storage module from the plurality of storage modules that make up the storage device using the floating address register from the storage device address and accesses the storage data A logical configuration showing an example has been described.

Next, the logical configuration of the floating address register designation register array 660 and its peripheral logic will be described in detail with reference to FIGS. 6 and 7. In FIGS. 6 and 7, the floating address register designation register array 660 is composed of a plurality of floating address register designation registers, and the value of the area ID which is the output of the latch A610 sent through the signal line 6A4. Use to select the corresponding floating address register specification register. Each floating address register designating register is
A storage range field that defines the storage capacity assigned to the AR and a top floating address register number field that defines from which floating address register the start of the storage area assigned to the LPAR is assigned It The contents of the floating address register designation register selected as described above are read out, and the storage range field and the leading floating address register number field are sent to the signal line 6B0 and the signal line 6B1, respectively.

Next, the comparator 670 outputs the value of the storage range field which is the output of the floating address register designation register array 660 sent via the signal line 6B0 (the upper limit given by the virtual computer having the area ID). The address (corresponding to the upper address of the address starting from 0) is compared with the value of the upper portion of the storage device address which is the output of the latch A610 sent through the signal line 6B2.
In this comparison operation, the specified storage device address is the LP
This is for verifying whether or not it is within the range of the storage capacity assigned to the AR, and if the specified storage device address is not within the range of the storage capacity assigned to the LPAR, an addressing exception occurs. A signal indicating that there is a program exception factor is sent to the signal line 6B4, and the LPA
The storage device access operation from R is stopped. If the program exception factor of the addressing exception does not exist, the storage access operation from the LPAR is continued. At the same time, the adder 680 causes the floating address register designation register array 6 sent via the signal line 6B1.
The value of the leading floating address register number field, which is the output of 60, and the latch A sent via the signal line 6B2.
The value of the upper part of the storage device address, which is the output of 610, is added. This addition operation is to add the top floating address register number in the floating address register designating register corresponding to the value of the area ID at the time of issuing the storage device access request to the value of the upper part of the specified storage device address. , The addition result is used as selection instruction data for selecting a floating address register corresponding to the storage device address in the floating address register group associated with the area ID, and this data is sent to the signal line 6B3. It is sent out and input to the selector 620. As described above, by using the floating address register from the storage device address, one storage module is selected from the plurality of storage modules forming the storage device, and the hardware of the storage module selection device for accessing the storage data and its main parts are described. The details of the logical configuration of the floating address register designating register array and its peripheral logic have been described.

The details of the procedure for selecting one storage module from the plurality of storage modules will be described in detail below with reference to FIGS. 6, 7 and 8. In FIG. 8, using the floating address register from the storage device address,
A procedure for selecting one storage module from a plurality of storage modules forming the storage device and accessing the storage data includes steps 801 to 814. Hereinafter, the conversion processing procedure will be described for each step. Step 801: The storage device access from the LIP to the storage region of the LMS allocated to the LPAR is performed by the storage device address (hereinafter referred to as the storage device address corresponding to the predetermined region ID allocated to the LPAR operating at that time and the continuous storage region of the LMS). , LMSADR). The predetermined area ID is supplied via the signal line 6A1 and the LMSADR is supplied via the signal line 6A2 to the latch A61.
Input to 0. At this time, the storage area required by the LPAR is already divided and assigned to the storage area of the RMS. That is, each entry of the floating address register designating register and the floating address register group 630 corresponding to the area ID corresponding to the LPAR has a storage area required by the LPAR as a floating address register group and The leading floating address register number field and the storage module number field are already set in association with the storage areas of the RMS.

Step 802: The predetermined area ID sent via the signal line 6A1 is latched by the portion b of the latch A610, and the LMSADR sent via the signal line 6A2 is the portion of the latch A610. Latched by e. Step 803: The latch A610 uses the signal line 6A1
And the memory device address LMS corresponding to the memory area of the predetermined area ID and continuous LMS sent from the signal line 6A2 and the signal line 6A2 as input.
It is a relay latch that temporarily stores ADR.
The value of the predetermined area ID latched in the portion b of 10 and the LMS latched in the portion e of the latch A610
The upper part of the value of ADR is sent to the floating address register designation register array 660, the comparator 670 and the adder 680 via the signal line 6A4 and the signal line 6B2, respectively. Further, the lower part of the value of LMSADR latched in the part e of the latch A 610 is stored in the storage module 0 65.
0, storage module 1 651, storage module 265
2 and a plurality of storage modules such as the storage module N 653 via the signal line 6A5.

Step 804: The floating address register designation register array 660 uses the value of the predetermined area ID sent via the signal line 6A4 to form a plurality of floating address registers forming the floating address register designation register array 660. Corresponding one of the register specification registers
Select one floating address register specification register. Step 805: The floating address register designation register array 660 outputs the value of the storage range, which is the content of one floating address register designation register selected in step 804, and the value of the leading floating address register number to the signal line 6B0 and the signal line, respectively. 6B1. Step 806: The comparator 670 outputs the value of the storage range field which is the output of the floating address register designation register array 660 sent via the signal line 6B0 and the latch A610 sent via the signal line 6B2. The output is compared with the value of the upper part of the storage device address.
When the value of the upper part of the storage device address to be compared is equal to or larger than the value of the storage range field, a signal indicating that there is a program exception factor of the addressing exception is sent to the signal line 6B4, and the LPAR is sent from The storage device access operation is stopped. If the value of the upper portion of the storage device address that is the comparison target is smaller than the value of the storage range field, the process proceeds to step 807.

Step 807: The adder 630 is sent via the signal line 6B2 and the value of the leading floating address register number field which is the output of the floating address register designation register array 660 sent through the signal line 6B1. The value of the upper part of the memory device address, which is the output of the latch A 610, is added, and the addition result is sent to the selector 620 via the signal line 6B3. Step 808: The selector 620 uses the signal line 6B3
Using the value of the floating address register number, which is the result of addition of the value of the top floating address register number field sent via
An instruction to select one corresponding floating address register is issued via the signal line 6A6 to the floating address register group 6
Send to 30. The floating address register group 630 selects one floating address register from the plurality of floating address registers in the floating address register group, and outputs the contents of the floating address register to the latch B6 via the signal line 6A7.
40.

Step 809: The latch B640 is
Latches the contents of a selected floating address register of the floating address registers of the floating address register group 630 sent via the signal line 6A7, and confirms whether the V field of the floating address register is valid. Test for invalidity. If the V field of the floating address register is valid, go to step 811, and if the V field of the floating address register entry is invalid, go to step 810. Step 810: This step is executed when the V field of the selected floating address register is invalid, and sends a signal to the signal line 6B5 indicating that there is a program exception factor of the addressing exception and stores it from the LPAR. The device access operation is stopped. The invalid V field of the floating address register entry indicates that the storage module corresponding to the corresponding storage area is unallocated or not equipped.

Step 811: This step is executed when the V field of the selected floating address register is valid, and the latch B640 is a plurality of floating address register groups 630 sent through the signal line 6A7. Of the selected floating address register, that is, the storage module number is latched in the latch B640. Step 812: Latch B640 in step 811
The memory module number latched by the memory module 0 650 and the memory module 1 6 are transmitted via the signal line 6A8.
51, storage module 2 652 and storage module N
It is sent to a plurality of storage modules such as 653. Step 813: The storage module numbers sent via the signal line 6A8 are the storage module 0 650 and the storage module 1 65 which are a plurality of storage module groups.
1, storage module 2 652 and storage module N 6
Only one storage module received at 53 or the like and given the same number as the storage module number is permitted to access the storage device, and only the storage module becomes accessible. Step 814: The storage module permitted to access the storage device in step 813 sets the lower part of the value of LMSADR, which is the output of the portion e of the latch A610, which is sent out through the signal line 6A5 in step 803, to the storage module. Is fetched as a storage device address to be accessed, and the access operation of the storage module is executed. That is, if the read operation request is from the storage device, the data read from the storage module is sent to the signal line 6AA, and if the write operation request is to the storage device, the data sent to the signal line 6A9 is sent. To the storage module. As described above, using the floating address register designation register and the floating address register from the storage device address,
The details of one embodiment of the procedure for selecting one storage module from a plurality of storage modules constituting the storage device and accessing the storage data have been described.

Next, a procedure for dynamically changing the contents of the floating address register designation registers in the plurality of floating address register designation registers of the floating address register designation register array 660 and the plurality of floating address register designations of the floating address register group 630. An embodiment of the procedure for dynamically changing the contents of the floating address register of will be described with reference to FIGS. 6 and 7. When the LIP issues a request to dynamically change the contents of the floating address register specification registers in the plurality of floating address register specification registers of the floating address register specification register array 660, the area ID specified in the request is issued to the request. Signal line 6 that is sent together
It is input to the latch A610 via A1. Signal line 6A
The area ID sent via 1 is latched in the portion b of the latch A 610. The latch A610 is connected to the signal line 6A.
Latch the area ID sent via 1 and
The value of the area ID latched in the portion b of 610 is sent to the floating address register designation register array 660 via the signal line 6A4. The floating address register designating register array 660 uses the value of the area ID sent via the signal line 6A4 to select one of the plurality of floating address register designating registers forming the floating address register designating register array 660. One floating address register designating register is selected, and write data sent from the signal line 6A3 is written to the floating address register designating register.

Next, when the LIP issues a request to dynamically change the contents of the floating address registers in the plurality of floating address registers of the floating address register group 630, the area ID and LMS specified in the request are issued. The LMSADR corresponding to the storage area is sent along with the request, the area ID is transmitted via the signal line 6A1, and the LMSADR is
It is input to the latch A610 via the signal line 6A2. The area ID sent via the signal line 6A1 is the latch A
LMSADR latched in the portion b of 610 and sent via the signal line 6A2 is latched in the portion e of the latch A 610. The latch A610 latches the area ID sent via the signal line 6A1 and the signal line 6A2 and the storage device address corresponding to the storage area of the LMS, and the value of the area ID latched in the portion b of the latch A610. Is sent to the floating address register designation register array 660 via the signal line 6A4. The floating address register designating register array 660 uses the value of the predetermined area ID sent via the signal line 6A4 to select one of the plurality of floating address register designating registers constituting the floating address register designating register array 660. Select one corresponding floating address register specification register. The floating address register designation register array 660 sends the value of the storage range and the value of the leading floating address register number, which are the contents of the selected one floating address register designation register, to the signal line 6B0 and the signal line 6B1, respectively. The adder 630 outputs the value of the leading floating address register number field, which is the output of the floating address register designation register array 660 sent via the signal line 6B1, and the latch A610 sent via the signal line 6B2. The value of the upper part of the storage device address, which is the output, is added, and the result of this addition is sent via the signal line 6B3 to the selector 62.
Send to 0. The selector 620 responds by using the value of the floating address register number which is the addition result of the value of the leading floating address register number field sent via the signal line 6B3 and the value of the upper part of the storage device address. One floating address register is selected, and the write data sent from the signal line 6AB is written in the floating address register.

By dynamically performing the above series of floating address register designating registers and the write operation to the floating address register, the position of the floating address register group with respect to an arbitrary area ID and an arbitrary LMS having an arbitrary area ID The storage module number corresponding to the LMSADR of the storage area can be dynamically changed arbitrarily, and the LMSADR area is dynamically separated by rewriting the V field of the floating address register from valid to invalid. By changing the V field of the floating address register from invalid to valid, the LMSADR area can be dynamically connected.

As described above, in the present invention, the LP
A plurality of floating address register designation registers are provided for each area ID assigned to the AR, and floating address register groups including a plurality of floating address registers corresponding to the floating address register designation registers are independently and The addressing hardware architecture has the maximum number of addresses that can be specified. Then, from the floating address register designation register array, one floating address register designation register is selected using the value of the area ID sent by the central processing unit, and a part of the storage device address sent by the central processing unit is selected. Using the value and the value of the top floating address register number, which is the content of the selected floating address register specification register,
A floating address register is selected from a plurality of floating address registers in the floating address register group. The selected floating address register has a storage module number field that indicates to which storage module the storage device address corresponds to the storage device, and when the central processing unit accesses the storage device, the floating address register is selected. Then, the contents are read, the read storage module number, which is the contents of the floating address register, is sent to the plurality of configured storage modules, and the corresponding storage module is selected.

The above-mentioned functions are provided and the floating address register designation register is independently provided for each area ID assigned to each LPAR, and one floating address register designation register is provided with an addressing of an actual information processing device. By having as many floating address registers as can be specified up to the maximum address specified by the hardware architecture, each of the plurality of LPARs has a storage device up to the maximum address specified by the addressing hardware architecture of the actual information processing device. Can be used. As a result, without changing the addressing hardware architecture of the actual information processing device that constitutes the storage device, the entire information processing device has a storage capacity exceeding the maximum storage capacity specified by the basic addressing hardware architecture of the information processing device. The device can be
Access from the AR is possible in parallel.

Furthermore, when RMS is assigned to the LPAR,
When a part of the LMS is disconnected from or connected to the OS operating on the LPAR by using an offline command or an online command, the V field of the floating address register stored in hardware in the floating address register group is valid or By rewriting to invalid, it is possible to realize a dynamic reconfiguration function of a storage device having a function of dynamically changing the position and capacity of one or more storage areas in the RMS area. Furthermore, the capacity of the LMS area and the LMS area are rewritten by rewriting the corresponding storage range field and head floating address register number field of the floating address register specifying register which are stored in the floating address register specifying register array by hardware. It is possible to dynamically change the correspondence with the floating address register group of, and by rewriting the corresponding storage module number field of the floating address register stored in hardware in the floating address register group, It is possible to dynamically change the correspondence between the LMS area and the storage module. As a result, without changing the addressing hardware architecture related to the address of the storage device used in the LPAR, the entire information processing device has a real storage device that exceeds the maximum storage capacity defined by the basic addressing hardware architecture of the information processing device. This enables simultaneous use, and further realizes a capacity expansion method and a logical partitioning method of the storage device, which improves the operability of the system and the usage efficiency of the real storage device. In this example, the capacity expansion method of the storage device using the hardware logic is illustrated, but it may be performed by microprogram control instead of the hardware logic.

[0041]

According to the present invention, the addressing hardware architecture of an actual information processing apparatus is not changed and L
The compatibility of programs operating on PAR is maintained, and further, the hardware logic of the information processing device is dramatically improved without expanding the data width of the storage device address defined by the addressing hardware architecture of the actual information processing device. While suppressing the increase, it is possible to realize a storage device expansion method that enables the maximum storage capacity specified by the addressing hardware architecture of the real information processing device for each of the plurality of LPARs, thereby suppressing industrial costs and reducing the system cost. It is possible to realize an expansion method associated with logical partitioning of a storage device, which has dramatically improved the performance of.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a virtual computer system that operates a plurality of virtual computers on a real computer, which is a conventional technique.

FIG. 2 is a block diagram showing a concept of area allocation of a plurality of virtual computers operating on a real computer and a storage device used by each virtual computer, which is a conventional technique.

FIG. 3 is a diagram showing a correspondence between a plurality of virtual computers operating on a real computer and a real storage device area used by each virtual computer, which is a conventional technique.

FIG. 4 is a block diagram showing a detailed example of hardware of a storage module selection mechanism using a floating address register which is a conventional technique.

FIG. 5 is a diagram showing the contents of a floating address register which is a conventional technique.

FIG. 6 is a logical block diagram showing a detailed hardware example of a storage module selection mechanism using a region ID and a floating address register according to the present invention.

7 is a diagram showing one detailed configuration of a floating address register designating register that constitutes the floating address register designating register array shown in FIG. 6;

FIG. 8 is a diagram showing a flowchart of processing for selecting a storage module using the area ID and the storage device address sent by the central processing unit.

[Explanation of symbols]

 210 Real Central Processing Unit (PIP) 221, 222, 223 Virtual Machine (LPAR) 231, 232, 233 Logical Central Processing Unit (LIP) 240 Real Storage Device (RMS) 410, 440 Latch 420 Selector 430 Floating Address Register Group 450, 451, 452, 453 Storage module 610, 640 Latch 620 Selector 630 Floating address register group 650, 651, 652, 653 Storage module 660 Floating address register designation register array 670 Comparator 680 Adder

Claims (3)

[Claims] 1. A storage capacity expansion method for a storage device in an information processing device comprising a central processing unit and a storage device, wherein a plurality of virtual machines operate on the central processing unit, wherein the storage device comprises a plurality of storage modules. The central processing unit of the virtual computer issues an area ID that is an identifier of the virtual computer and a storage device address to access the storage device, and the central processing unit is provided corresponding to the area ID and stores the storage area. A floating address register designating register that holds a capacity and a floating address register number corresponding to the start address of the storage area, receives the area ID issued by the central processing unit of the virtual machine, and receives the area ID corresponding to the area ID. Floating address register designated register array that selects designated register and outputs contents held in the selected register A floating address register group including a plurality of floating address registers for holding storage module numbers, the number of which is equal to the number of the plurality of storage modules; and a top address of the storage area output from the floating address register designation register array. Addition means for adding the corresponding floating address register number and the upper address of the issued storage device address, and a storage module for selecting a floating address register from the floating address register group based on the output of the addition means A selection unit for outputting a number is provided, and when a storage device access is requested from the central processing unit of the virtual computer and the area ID and the storage device address are issued, the selection unit outputs the output based on the output of the addition unit. Stored in the floating address register A storage capacity expansion method for a storage device, wherein the storage device is accessed by a storage module number and a lower address of the issued storage device address. 2. The storage capacity expansion method for a storage device according to claim 1, wherein the floating address register designation register array is selectively output according to a region ID which is an identifier of the virtual computer issued by the central processing unit of the virtual computer. Comparing means for comparing the storage capacity of the storage area of the stored contents of the floating address register designation register with the upper address of the storage device address issued by the central processing unit of the virtual machine,
When the upper address of the storage device address is out of the storage capacity of the storage area, the comparing means sends the program exception factor of the addressing exception to the central processing unit of the virtual computer that has accessed the storage device. A method for expanding the storage capacity of a storage device. 3. The storage capacity expansion method for a storage device according to claim 1, wherein the floating address register designation register array is designated with the area ID, and the storage capacity of the storage area or the start address of the storage area. A storage capacity expansion method for a storage device, characterized in that when the floating address register number or both of them are input, the contents held in the floating address register designation register designated by the area ID are dynamically changed.