JPH0888331A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a DRAM capable of suppressing a leak current due to a parasitic transistor without affecting characteristics of a transfer gate. [Structure] DRAM in which memory cells including MOS transistors and trench capacitors are arranged in a matrix
In the above, a MOS transistor configured by forming an n ⁺ type source / drain diffusion layer 15 on the surface of a semiconductor substrate having a p well 2 formed on an n type substrate 1 and a substrate adjacent to the source diffusion layer 15 _1. The trench 3 provided in the trench 3, the diffusion layer 8 for the n ⁺ type plate electrode formed on the outer peripheral portion of the trench 3 except for the upper portion of the trench 3, and the trench 3 embedded in the trench 3 via the capacitor insulating film 9. Formed,
Storage electrode 10 connected to _one of the source diffusion layers 15 ₁
And a p ⁺ -type inversion prevention diffusion layer 7 provided between the source diffusion layer 15 _{1 and the} plate electrode diffusion layer 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM), and more particularly to a semiconductor memory device having an improved memory cell structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, a memory cell structure has been proposed in which a storage electrode is formed in a trench provided in a substrate and a MOS capacitor having the substrate as a plate electrode is provided. Figure 7
1 is an n-type silicon substrate, 2 is a p-well, 3 is a trench, 6 is an oxide film, 8 is an n ⁺ type diffusion layer (plate electrode), and 9 is capacitor insulation. A film, 10 is a storage electrode, 12 is a gate electrode, 15 is a source / drain diffusion layer, and 16 is a connection electrode. Since this structure has a smaller junction area than a memory cell structure in which the outer peripheral portion of the trench is used as a storage electrode, a cell having good data retention characteristics and strong soft error resistance can be realized.

However, in this structure, a parasitic transistor structure is formed in which the source diffusion layer 15 ₂ of the MOS transistor and the n ⁺ type diffusion layer 8 serving as a plate electrode are opposed to each other with the oxide film 6 above the trench interposed therebetween. That is, when a high potential is written in the storage electrode 10, this parasitic transistor may be turned on and a leak current as indicated by an arrow in the drawing may flow. When this leak current flows, the data retention characteristic of the memory cell is significantly deteriorated.

Therefore, in order to prevent the leakage current from being generated by the parasitic transistor, a method of controlling the following two parameters has been taken. One is a method of increasing the threshold value of the parasitic transistor by thickening the oxide film 6. However, as the cell size shrinks, the oxide film also has to shrink. Further, if the film is thickened, stress is applied to the upper part of the trench, which may cause a crystal defect.

The second method is to increase the threshold value of the parasitic transistor by increasing the concentration of the p well 2.
However, when the concentration of the p well is increased, the substrate bias effect of the transfer gate becomes remarkable, so that the writing operation to the memory cell becomes difficult.

Further, as the p-well concentration is higher, the junction leakage current from the n ⁺ type diffusion layer 15 ₂ in contact with the p-well is increased, so that the pause characteristic is deteriorated. In order to avoid these problems, a method of forming a channel stopper layer using high-acceleration ion implantation at a position deeper than the junction position is also proposed, but in this case as well, a high-concentration layer is formed under the transfer gate. There was a possibility that the element characteristics would deteriorate.

[0007]

As described above, in the conventional memory cell structure having the substrate plate type trench capacitor, the leakage due to the parasitic transistor is caused between the source / drain diffusion layer of the transfer gate and the plate diffusion layer. There was a problem that current would flow.

The present invention has been made to solve the above problems, and an object of the present invention is to suppress the leak current due to a parasitic transistor without affecting the characteristics of the transfer gate, and to improve reliability. An object is to provide a highly reliable semiconductor memory device.

[0009]

The essence of the present invention is to locally form an impurity layer having a conductivity type opposite to that of the plate diffusion layer on the upper portion of the plate diffusion layer in order to suppress a leak current due to a parasitic transistor. is there.

That is, according to the present invention, in a semiconductor memory device in which memory cells composed of MOS transistors and trench capacitors are arranged in a matrix, a first conductivity type source / drain diffusion layer is formed on the surface of a semiconductor substrate. A MOS transistor, a trench provided in the substrate adjacent to one of the source / drain diffusion layers of the MOS transistor, and a first conductivity type plate electrode formed on the outer peripheral portion of the trench except for the upper portion of the trench. Between the source diffusion layer and one of the source / drain diffusion layers and the plate electrode diffusion layer, and the storage electrode connected to one of the source / drain diffusion layers by being buried in the trench via the capacitor insulating film. And an inversion prevention diffusion layer of the second conductivity type.

Further, according to the present invention, in a method of manufacturing a semiconductor memory device having a memory cell including a MOS transistor and a trench capacitor, when forming the trench capacitor, after forming the trench in the semiconductor substrate, an oxide film is formed on the inner wall of the trench. , A nitride film is sequentially formed, and then a resist is left in the trench halfway, and the resist is used as a mask to remove the nitride film in the upper part of the trench. Of impurities, then remove the resist, then selectively oxidize the upper part of the trench using the nitride film as a mask, and then remove the nitride film under the trench.
After that, the storage electrode is buried in the trench via the capacitor insulating film.

Here, the following are preferred embodiments of the present invention. (1) The semiconductor substrate is a first conductivity type substrate on which a second conductivity type well is formed, and the trench is formed from the surface of the well to the middle of the substrate. (2) The inversion prevention layer is formed on the upper end of the plate electrode diffusion layer. (3) The inversion prevention layer is continuously formed between the plate electrode diffusion layer and one of the source / drain diffusion layers. (4) The inversion prevention layer is formed by ion implantation from an oblique direction. (5) The storage electrode and one of the source / drain diffusion layers are connected by the connection electrode formed on the substrate. (6) The oxide film at the bottom of the trench is removed after the selective oxidation at the top of the trench. (7) As a method of manufacturing a trench capacitor, after forming a first trench in a semiconductor substrate, an oxide film is formed on a side surface of the first trench, and then a source / drain diffusion layer is formed inside the first trench. After doping an impurity of opposite conductivity type and then forming a second trench, this second trench is formed.
The side surface of the trench is doped with an impurity of the same conductivity type as the source / drain diffusion layer, and then the storage electrode is embedded in the trench via the capacitor insulating film.

[0013]

According to the present invention, the second conductivity type inversion prevention layer is formed between one of the first conductivity type source / drain diffusion layers and the first conductivity type plate electrode diffusion layer. Since the inversion prevention layer is present in the channel region of the parasitic transistor formed by each diffusion layer of the first conductivity type and the storage electrode, it is possible to prevent the parasitic transistor from turning on. This makes it possible to suppress the generation of leakage current due to the parasitic transistor. Also,
If the inversion prevention layer is formed only on the plate electrode diffusion layer, the characteristics of the cell transistor are not deteriorated.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a D according to the first embodiment of the present invention.
It is sectional drawing which shows the memory cell structure of RAM.

A p well 2 is formed on an n type silicon substrate 1, n ⁺ type source / drain diffusion layers 15 (15 ₁ , 15 ₂ ) are formed on the surface of the p well 2, and further on the p well 2. A MOS transistor is formed by forming the gate electrode 12 with the gate insulating film 11 interposed therebetween. Adjacent to the source diffusion layer 15 ₁ of the MOS transistor, the trench 3 is formed from the surface of the p well 2 to the middle of the substrate 1.
Are formed. An oxide film 6 is formed on the upper side surface of the trench 3.
Is formed, and the capacitor insulating film 9 is formed on the lower side surface. An n ⁺ type diffusion layer 8 serving as a plate electrode is formed on the outer peripheral portion of the trench 3 below the oxide film 6, and a storage electrode 10 is embedded in the trench 3. Then, the source electrode 15 ₁
And the storage electrode 10 are connected.

The structure up to this point is the same as the conventional one, but in this embodiment, in addition to this, the p ⁺ type inversion prevention layer 7 is formed on the outer peripheral portion of the trench located at the upper end of the n ⁺ type diffusion layer 8. ing. Incidentally, nitride films 13 and 14 in the figure covering the gate electrode 12, 17 is a bit line connected to the drain diffusion layer ₁₅₂ of the MOS transistor, 20 denotes a field oxide film for element isolation.

In such a structure, the p ⁺ type inversion prevention layer 7
Is between the source diffusion layer 15 ₁ and the plate diffusion layer 8 of the MOS transistors, but acts as a parasitic channel stopper in order not directly under the transistor, the risk of degrading the substrate bias effect and junction breakdown voltage or the like small.

Next, the manufacturing process of the device of this embodiment will be described with reference to FIG.
A description will be given using (a) to (d). First, after the element isolation step is completed, as shown in FIG. 2A, a mask material 5 for forming a trench is formed on the p-well 2 with the oxide film 4 formed on the surface of the p-well 2. , RIE or the like to open a first trench 3a having a depth of 1 to 2 μm on the substrate surface. Then, the inner wall of the trench 3a is oxidized by about 10 to 100 nm to form the oxide film 6.

Then, as shown in FIG. 2B, RIE is performed.
Like after removing the bottom of the oxide film 6 by using the trench bottom such as B, the ion implantation 7 'such as BF _2. Next, as shown in FIG. 2C, the impurities are diffused by annealing so that the impurities spread from the outer periphery of the first trench. As a result, the p ⁺ -type inversion prevention layer 7 is formed.

Next, as shown in FIG. 2D, after the second trench 3b is formed by RIE or the like, the same A
s, P, etc. are ion-implanted to form a plate electrode n ⁺
The type diffusion layer 8 is formed. At this time, it is important that the n-type impurities are not injected into the upper portion of the trench because the thick oxide film 6 exists in the upper portion of the trench.

As described above, according to this embodiment, since the p ⁺ type inversion prevention layer 7 is formed on the outer peripheral portion of the trench 3 located at the upper end of the n ⁺ type diffusion layer 8, this inversion prevention layer 7 is formed. It acts as a parasitic channel stopper between the source diffusion layer 15 ₁ and the plate diffusion layer 8. Further, the n ⁺ type diffusion layer 7 is M
Since it is not directly under the OS transistor, the risk of degrading the substrate bias effect, the junction breakdown voltage, etc. is small.
Therefore, the parasitic channel leakage current can be suppressed without deteriorating the transistor characteristics. (Embodiment 2) FIG. 3 shows the D according to the second embodiment of the present invention.
FIG. 9 is a cross-sectional view of the manufacturing process for explaining the RAM. In addition,
The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is a modification of the manufacturing process of the first embodiment. Specifically, after the step shown in FIG. 2A described in the first embodiment, as shown in FIG. 3, after removing the oxide film 6 at the bottom of the trench 3a,
When the trench bottom is dug down to about 100 to 500 nm, p-type ion implantation 7'is performed from an oblique direction. With this method, it is possible to directly implant ions into the lower side surface of the thick oxide film 6, and annealing can be omitted. After this, similarly to the first embodiment, the second trench 3a is formed, and the n ⁺ type diffusion layer 8 serving as the plate electrode is formed by performing ion implantation of n type impurities.

In this embodiment, since ions can be directly implanted into the lower side surface of the oxide film 6, the function as the inversion prevention layer 7 can be more surely provided, and the leakage current due to the parasitic transistor can be prevented. It can be suppressed more reliably. (Embodiment 3) FIG. 4 shows the D according to the third embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of RAM. The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, even in the structure in which the thick oxide film is formed on the upper portion of the trench, only the ion implantation is performed.
This is a method of forming an inversion prevention layer and a plate diffusion layer. In particular, the point is to control the implantation depth by the ion implantation angle.

First, as shown in FIG. 4A, with the thick oxide film 6 formed on the upper portion of the trench 3, p-type impurities are implanted 7 ′ so that the minimum ion implantation angle becomes θ _1. . As a result, the ions irradiated from above the substrate hit only the side surface of the oxide film 6 and the trench inner surface immediately below the oxide film 6 in the trench 3 and do not hit the trench inner surface below it. That is, the ions can be selectively implanted only in the vicinity immediately below the oxide film 6.

Then, as shown in FIG. 4B, the p ⁺ type inversion prevention layer 7 is formed by diffusion by annealing. Then, as shown in FIG. 4C, the n-type impurity is changed to θ1>
Implantation 8'is performed at the lower portion of the trench with an ion implantation angle θ2 such that the angle becomes θ2 to form the diffusion layer 8 for the plate electrode.

Even with such a method, the finally obtained structure is similar to that of the first embodiment, and the same effect as that of the first embodiment can be obtained. (Embodiment 4) FIG. 5 shows a D according to a fourth embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of RAM. The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is a method of performing selective impurity doping on the upper side surface of the trench. First, FIG.
As shown in (a), after forming the first trench 3a, p-type impurities are ion-implanted into the trench side surface and bottom surface 7 '. This ion implantation is performed in an oblique direction as shown in the figure.

Next, as shown in FIG. 5B, the inner wall of the trench is oxidized to form an oxide film 6, and then the oxide film 6 at the bottom of the trench is removed. Then, after forming the second trench 3b, the n ⁺ -type impurity layer 8 to be the plate electrode is formed.

In this embodiment, since the p ⁺ type inversion prevention layer 7 is formed over the entire outer periphery of the oxide film 6 in the upper portion of the trench, it is possible to more reliably prevent the generation of the leak current due to the parasitic transistor. . Further, in this embodiment structure, there is a case where the inversion preventing layer 7 and the source diffusion layer 15 ₁ are in contact, because the contact area is very small, hardly affects the transistor characteristics. (Embodiment 5) FIG. 6 shows the D according to the fifth embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of RAM. The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is also a method of selectively performing impurity doping on the upper side surface of the trench. Further, the trench 3 is characterized by being dug once instead of being dug twice.

First, as shown in FIG. 6A, one R
After forming the trench 3 by IE, the inner wall of the trench is
An oxide film 31 is formed by oxidation of about 20 nm, and a SiN film 32 of about 5 to 50 nm is formed as an oxidation resistant film. Then, the resist 33 is applied and the exposure time is adjusted to leave the resist 33 in the middle of the trench.

Then, using the resist 33 as a mask, C
SiN on the top of the trench by isotropic etching such as DE
The film 32 is removed. Then, p-type impurities are ion-implanted 7'to form the local inversion prevention layer 7 only in the upper portion of the trench. In order to form the inversion prevention layer 7 on the side wall of the trench, the ion implantation is performed in an oblique direction.

Then, after removing the resist 33, the thick oxide film 6 is selectively formed only in the upper part of the trench by performing oxidation while leaving the SiN film 32 in the lower part of the trench. Then, after removing the SiN film 32 and the oxide film 31 thereunder, as shown in FIG. 6B, an n ⁺ type diffusion layer 8 serving as a plate electrode is formed by the ion implantation method using the oxide film 6 as a mask. . The ion implantation at this time is also performed in an oblique direction.

Further, in the above process, it is possible to perform ion implantation through the oxide film 31 without removing the oxide film 31 and leaving the oxide film 31 left. In this case, it is possible to prevent damage to the underlying silicon substrate 1.

Even with such a method, the finally obtained structure is similar to that of the fourth embodiment, and the same effect as that of the fourth embodiment can be obtained. Further, in this embodiment, the trench 3
It is possible to obtain a great advantage that the RIE can be formed by one RIE.

The present invention is not limited to the above embodiments. In the embodiment, an example in which the ion implantation method is used as the impurity doping method has been shown, but a method such as solid phase diffusion or vapor phase diffusion may be used. Also, although an example in which an nMOS is used as the memory cell transistor is shown, a pMOS may be used. In this case, the inversion prevention layer for parasitic channel stop becomes n-type. Further, the thermal oxidation method has been shown as a method for forming the thick oxide film on the upper portion of the trench, but it may be formed by depositing the film by the CVD method or the like. In addition, various modifications can be made without departing from the scope of the present invention.

[0038]

As described in detail above, according to the present invention, the second conductivity type inversion prevention layer is locally formed on the upper part of the first conductivity type plate diffusion layer outside the trench, so that the transistor characteristics can be improved. It is possible to suppress the generation of the leak current due to the parasitic transistor without deteriorating the leakage current. Therefore, it is possible to realize a dynamic semiconductor memory device having excellent data retention characteristics even when miniaturized.

[Brief description of drawings]

FIG. 1 is a sectional view showing a memory cell structure of a DRAM according to a first embodiment.

FIG. 2 is a cross-sectional view showing the manufacturing process of the device of the first example.

FIG. 3 is a cross-sectional view showing the manufacturing process of the DRAM according to the second embodiment.

FIG. 4 is a sectional view showing a manufacturing process of the DRAM according to the third embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the DRAM according to the fourth embodiment.

FIG. 6 is a cross-sectional view showing the manufacturing process of the DRAM according to the fifth embodiment.

FIG. 7 is a sectional view showing a memory cell structure of a conventional DRAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... N type silicon substrate 2 ... P well 3,3a, 3b ... Trench 5 ... Mask material 6 ... Oxide film 7 ... P ⁺ type inversion prevention layer 8 ... N ⁺ type diffusion layer (plate electrode) 9 ... Capacitor insulating film 10 Storage electrode 11 Gate insulating film 12 Gate electrode 15 n ⁺ type source / drain diffusion layer 16 Connection electrode 17 Bit line 31 Oxide film 32 Nitride film 33 Resist

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (2)

[Claims] 1. A source of the first conductivity type on the surface of a semiconductor substrate.
A MOS transistor formed by forming a drain diffusion layer, and a trench provided in the substrate adjacent to one of the source / drain diffusion layers of the MOS transistor,
A diffusion layer for the first conductivity type plate electrode formed on the outer peripheral portion of the trench except for the upper portion of the trench and a diffusion layer for the source / drain diffusion layer which is embedded and formed in the trench via a capacitor insulating film. A storage electrode connected to one side of the source / drain diffusion layer; and a diffusion layer for preventing inversion of the second conductivity type provided between one of the source / drain diffusion layers and the diffusion layer for the plate electrode. A semiconductor memory device, wherein memory cells made of capacitors are arranged in a matrix. 2. A method of manufacturing a semiconductor memory device having a memory cell composed of a MOS transistor and a trench capacitor, wherein when forming the trench capacitor, a step of forming a trench in a semiconductor substrate, an oxide film on an inner wall of the trench, A step of sequentially forming a nitride film, a step of leaving a resist halfway inside the trench, a step of removing the nitride film on the upper part of the trench by using this resist as a mask, and a source / drain diffusion layer of the MOS transistor on the upper part of the trench. Is a step of doping impurities of opposite conductivity type, a step of selectively oxidizing the upper portion of the trench with the nitride film as a mask after removing the resist, a step of removing the nitride film under the trench, And burying the storage electrode via the capacitor insulating film. Method for manufacturing semiconductor memory device.