JPH089337A - Video signal processing circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A video signal processing circuit that can be used for motion analysis and special effects by drawing the image trajectory of a moving image. Sufficient motion analysis even for video signals with large amounts of motion. And aim to get special effects. A motion detection circuit that detects a motion of an input video signal and outputs a control signal, a first image memory circuit that stores at least one screen of the input video signal, and a moving image area of the input video signal are rewritten. A first memory control circuit for controlling the first image memory circuit, a second image memory circuit for storing the input video signal for at least one screen, and a moving image area of the input video signal read at an appropriate position A second memory control circuit for controlling the second image memory circuit so as to form and output a moving image area which is not present, and selectively outputs the output of the first image memory circuit and the output of the second image memory circuit. And a selector circuit for switching and outputting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit which can be used for motion analysis and special effect processing by drawing an image locus of a moving image.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram of a conventional video signal processing circuit for realizing a special effect by drawing a locus of a moving image. This circuit utilizes an image memory having a storage capacity of one field or more and realizes a special effect by rewriting the moving image area according to the movement of the image.

In the figure, an input video signal Si is input in parallel to an image memory circuit 60, a motion detection circuit 61 and a luminance / hue detection circuit 62. The image memory circuit 60 is 1
It has a storage capacity capable of storing video signals in the field or more. The motion detection circuit 61 detects a moving image area in one field (or frame) of the input video signal Si, and outputs a high level control signal for the detected moving image area.

FIG. 14 shows a block diagram of the motion detection circuit 61. This circuit is an image memory circuit 61a having a storage capacity of one field or more, and a subtraction circuit 61b for taking a difference between an input video signal Si and an output signal of the image memory circuit 61a and generating a difference signal between one field (or frame). And a decoder circuit 61c for converting the difference signal and outputting a control signal.

The brightness / hue detection circuit 62 detects an object image in the image based on the brightness or hue and outputs a high level control signal for the object image area. Each control signal output from the motion detection circuit 61 and the luminance / hue detection circuit 62 is input to the memory control circuit 63.

The memory control circuit 63 controls the writing operation of the image memory circuit 60 so that the video signal Si input to the image memory circuit 60 is rewritten only when both control signals are at a high level. This makes it possible to detect a certain object image based on the moving image area of the input video signal Si and the brightness / hue, and reproduce the motion.

[0007]

In the above-mentioned conventional video signal processing circuit, the moving image area and the object area are detected in units of one field or one frame in order to draw the image locus, and then the images of the moving image area and the object area are detected. Writing to the memory circuit is performed in units of one field or one frame.

Therefore, the image locus can be drawn only in units of one field (or frame), and sufficient motion analysis and special effects are applied to an image with fast motion, that is, to an input video signal with a large amount of motion. Couldn't get

Therefore, it is an object of the present invention to provide a video signal processing circuit capable of obtaining sufficient motion analysis and special effects even for a video signal having a large amount of motion.

[0010]

A video signal processing circuit according to the present invention comprises a motion detection circuit for detecting a motion of an input video signal and outputting a plurality of control signals, and a first video signal storage circuit for storing at least one screen of the input video signal. A first image memory circuit and a first image memory circuit for controlling the first image memory circuit to rewrite the moving image area of the input video signal by the control signal from the motion detection circuit.
Memory control circuit, a second image memory circuit for storing the input video signal for at least one screen, and the control signal from the motion detection circuit to read the moving image area of the input video signal at an appropriate position and not to the input video signal. A second memory control circuit for controlling the second image memory circuit so as to form and output a moving image area, and an output of the first image memory circuit and a second image memory circuit by a control signal from the motion detection circuit. And a selector circuit for selectively switching and outputting the output of.

The video signal processing circuit according to the present invention is
A motion detection circuit that detects a motion of an input video signal and outputs a plurality of control signals, a first image memory circuit that stores the input video signal for at least one screen, and a video signal delayed by at least one screen A first memory control circuit that controls the first image memory circuit, a second image memory circuit that stores the input video signal for at least one screen, and a moving image area of the input video signal by the control signal from the motion detection circuit. A second memory control circuit that controls the second image memory circuit so as to form and output a moving image area that is not included in the read input video signal at an appropriate position, and an input video signal according to the control signal from the motion detection circuit. And a selector circuit for selectively switching between the output of the first image memory circuit and the output of the second image memory circuit and outputting to the first image memory circuit.

The video signal processing circuit according to the present invention is
A motion detection circuit that detects a motion of an input video signal and outputs a plurality of control signals, a first image memory circuit that stores at least one screen of the input video signal, and an input video signal according to a control signal from the motion detection circuit. The first memory control circuit for controlling the first image memory circuit so as to rewrite the moving image area of the above, and the moving image area of the input image signal and the moving image area of the input image signal one screen before by the control signal from the motion detection circuit. Motion compensation type interpolation means for moving to the same position and taking an arithmetic mean to form and output a moving image area not included in the input video signal; and output of the first image memory circuit by a control signal from the motion detection circuit. And a selector circuit for selectively switching and outputting the output of the motion compensation type interpolation means.

The video signal processing circuit according to the present invention is
A motion detection circuit that detects a motion of an input video signal and outputs a plurality of control signals, a first image memory circuit that stores the input video signal for at least one screen, and a video signal delayed by at least one screen The first memory control circuit for controlling the first image memory circuit and the control signal from the motion detection circuit move the moving image area of the input video signal and the moving image area of the input video signal one screen before to the same position. A motion compensation type interpolation means for taking an arithmetic mean and forming and outputting a moving image area which is not in the input video signal, and an input video signal, an output of the first image memory circuit and a motion compensation type by a control signal from the motion detection circuit. A selector circuit for selectively switching the output of the interpolating means and outputting to the first image memory circuit.

[0014]

In the structure of the present invention, after the moving image area of the input video signal is detected by the motion detection circuit, the moving image area is accumulated and the moving image between the screens which is not included in the input video signal is interpolated according to the movement. By drawing the image trajectory of a moving image, it is possible to obtain sufficient motion analysis and special effects for an input video signal with a large amount of motion that could not be analyzed up to now.

[0015]

1 is a block diagram showing a first embodiment of a video signal processing circuit according to the present invention. This embodiment has a motion detection circuit 1 to which an input video signal Si is input, a first image memory circuit 2 and a second image memory circuit 3.

As shown in FIG. 2, the motion detection circuit 1 has 1
An image memory circuit 1a having a storage capacity of more than a field,
A subtraction circuit 1b that takes the difference between the input video signal Si and the output signal of the image memory circuit 1b to generate a difference signal for one screen (that is, one field or one frame), and control signals M1, M2, S1 from this difference signal. It is composed of a decoder circuit 1c for outputting.

The motion detection circuit 1 detects the moving image area of the input video signal Si, and outputs a high level control signal M1 for the moving image area to the first memory control circuit 4. The memory control circuit 4 controls the writing operation of the image memory 2 so that the video signal S1 input to the image memory circuit 2 is rewritten only when the control signal M1 is at a high level.

The motion detection circuit 1 detects the motion amount V (vector) of the input video signal Si and outputs a control signal M2 corresponding to the motion amount V to the second memory control circuit 5. The control signal M2 is “M2 = αV” (where α <1)
Is. The memory control circuit 5 controls the image memory circuit 3 so as to read a signal from the image memory circuit 3 according to the control signal M2. As a result, a signal obtained by moving the input video signal Si by αV is obtained in the image memory circuit 3.

The signals output from the image memory circuits 2 and 3 are both input to the selector circuit 6. The selector circuit 6 controls the control signal S1 output from the motion detection circuit 1.
When is high level, the signal from the image memory circuit 3 is output, and when the control signal S1 is low level, the signal from the image memory circuit 2 is output. Here, the control signal S1 output from the motion detection circuit 1 is a signal in which only the signal region read from the image memory circuit 3 according to the control signal M2 becomes high level.

The operation of this embodiment will be further described with reference to FIG. In the motion detection circuit 1, as shown in FIG. 3A, when the area A exists in the previous field (or frame) and the area A moves to the area Aa in the current field (or frame), the moving area Aa and the movement amount V are detected, and the control signal M1 is input to the memory control circuit 4.
The memory control circuit 4 controls the writing operation of the image memory circuit 2 so that the rewriting is performed only in the area Aa of the control signal M1 which becomes high level. Therefore, the image memory circuit 2
As shown in FIG. 3 (b), the output of 1 can have two areas of area A and area Aa on one field (or frame).

On the other hand, the control signal M2 output from the motion detection circuit 1 is input to the memory control circuit 5. The memory control circuit 5 controls the image memory circuit 3 so as to read the signal from the image memory circuit 3 according to the control signal M2.
As a result, the area Ab obtained by moving the area A by αV is obtained from the image memory circuit 3, as shown in FIG.

Image memory circuit 2 including area A and area Aa
Output of the image memory circuit 3 including the area Ab,
The control signal S1 from the motion detection circuit 1 in which only the region Ab becomes high level is input to the selector circuit 6. The selector circuit 6 outputs the signal from the image memory circuit 3 as the output video signal So when the control signal S1 is at the high level, and outputs the signal from the image memory circuit 2 when the control signal S1 is at the low level. Output as So. As a result, as shown in FIG. 3D, the area A, the area Aa, and the area Ab can be present in one field (or frame), and the locus of the moving image area can be drawn.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a second embodiment of the video signal processing circuit according to the present invention. This embodiment has a motion detection circuit 10 to which an input video signal Si is input, an image memory circuit 11 and a selector circuit 12.

The motion detection circuit 10 is composed of an image memory circuit 10a, a subtraction circuit 10b and a decoder circuit 10c, like the motion detection circuit 1 described above.
Control signals M3, S2 and S3 are output from c.

The motion detection circuit 10 detects the motion amount V (vector) of the input video signal and inputs the control signal M3 corresponding to the motion amount V to the memory control circuit 13. The control signal M3 is “M3 = αV (where α <1)”. The memory control circuit 13 reads the signal from the image memory circuit 11 according to the control signal M3.
Control 1 As a result, a signal obtained by moving the input video signal Si by αV is obtained in the image memory circuit 11.

Further, the motion detection circuit 10 detects the moving image area of the input video signal Si, and the signal read out from the image memory circuit 11 according to the control signal M3 and the control signal S2 which becomes a high level with respect to the moving image area. The control signal S3 that brings the region to the high level is output to the selector circuit 12.

In the selector circuit 12, the motion detection circuit 10
When the control signal S2 is at a high level based on the control signals S2 and S3 from
When 3 is high level, the signal from the image memory circuit 11 is output, and when both control signals S2 and S3 are low level, the signal from the image memory circuit 14 is output.

The image memory circuit 14 has a capacity capable of storing a video signal of one field or more, and the memory control circuit 15
Under the control of 1), the video signal is delayed by one field or more and output as the output video signal So, and is also fed back to the selector circuit 12.

The operation of this embodiment will be further described with reference to FIG. In the motion detection circuit 10, as shown in FIG. 6A, when the area A exists on the previous field (or frame) and the area A moves to the area Aa on the current field (or frame), the moving area Aa and the movement amount V are detected, and the control signal M3 is input to the memory control circuit 13.

The memory control circuit 13 controls the image memory circuit 11 so as to read a signal from the image memory circuit 11 according to the control signal M3. Therefore, from the image memory circuit 11, as shown in FIG.
The moved region Ab will be obtained.

Further, the motion detection circuit 10 detects the moving image area of the input video signal Si and reads it out in response to the control signal S2 which becomes a high level for the area Aa and the control signal M3 from the image memory circuit 11. The control signal S3 that makes the region Ab high level is input to the selector circuit 12.

In the selector circuit 12, the control signals S2, S
3, when the control signal S2 is at the high level, the area Aa of the input video signal Si, and when the control signal S3 is at the high level, the area Ab from the image memory circuit 11 and the control signal S2.
When both S3 are low level, the signal So from the image memory circuit 14 is selected and output.

At this time, since the image memory circuit 14 stores the signal of the previous field (or frame), the output of the image memory circuit 14 should be output again when both the control signals S2 and S3 are at the low level. And Fig. 6
As shown in (c), the selector circuit 12 can allow the area A, the area Aa, and the area Ab to exist on one field (or frame), and the signal thereof is sent to the image memory circuit 1.
By outputting to 4, it is possible to draw the trajectory of the moving image area.

Next, a third embodiment of the present invention will be described. FIG. 7 is a block diagram showing a third embodiment of the image processing circuit according to the present invention. In the present embodiment, the motion detection circuit 20 and the image memory circuit 2 to which the input video signal Si is input.
1. It has the image memory circuits 23 and 24 in the motion compensation type interpolation circuit 22.

The motion detection circuit 20 is composed of an image memory circuit 20a, a subtraction circuit 20b and a decoder circuit 20c, like the motion detection circuit 1 described above.
Control signals M4, M5, M6 and S4 are output from 0c, respectively.

In the motion detection circuit 20, the input video signal Si
Of the moving picture area, and a high level control signal M4 for the moving picture area is input to the memory control circuit 24. The memory control circuit 24 controls the writing operation of the image memory circuit 21 so that the input video signal Si input to the image memory circuit 21 is rewritten only when the control signal M4 is at a high level.

The motion detection circuit 20 detects the motion amount V (vector) of the input video signal Si, and the motion amount V
The control signals M5 and M6 according to are input to the memory control circuits 25 and 26 in the motion compensation type interpolation circuit 22. At this time, the control signal M5 is “M5 = {x / (x + y)} V”.
(However, x and y are positive integers), the control signal M6 is "M6
=-{Y / (x + y)} V "(where x and y are positive integers).

In the memory control circuit 25, the image memory circuit 27 outputs a signal delayed by the same amount as the delay amount of the image memory circuit 20a in the motion detection circuit 20 in the image memory circuit 23.
, And the image memory circuit 27 is controlled so that the signal is read according to the control signal M5 from the motion detection circuit 20. As a result, the video signal of the previous field (or frame) is converted into “{x / (x +
y)} V "The moved signal is obtained.

The memory control circuit 26 controls the image memory circuit 24 so as to read a signal from the image memory circuit 24 according to the control signal M6. As a result, in the image memory circuit 24, the input video signal Si is changed to "-{y / (x
+ Y)} V "The moved signal is obtained.

The outputs of the image memory circuits 27 and 24 are input to the coefficient multiplication circuits 28 and 29, respectively, and the outputs of the coefficient multiplication circuits 28 and 29 are added by the addition circuit 30 and input to the selector circuit 31. Coefficient multiplication circuit 28
Is "x / (x + y)", and the coefficient of the coefficient multiplication circuit 29 is "y / (x + y)". The signal output from the image memory circuit 21 is also input to the selector circuit 31.

In the motion detection circuit 20, the image memory circuit 2
The control signal S4 from 7 to the control signal M5 or from the image memory circuit 24 in response to the control signal M6 is inputted to the selector circuit 31. The selector circuit 31 outputs the signal from the image memory circuit 21 when the control signal S4 is at the high level, and outputs the control signal S4.
When 4 is at low level, the signal from the adder circuit 30 is output.

The operation of this embodiment will be further described with reference to FIG. In the motion detection circuit 20, as shown in FIG. 9A, when the area A exists in the previous field (or frame) and the area A moves to the area Aa in the current field or frame, the area Aa is changed to the moving area Aa. The amount of movement V is detected, and the control signal M4 is input to the memory control circuit 24.

The memory control circuit 24 controls the writing operation of the image memory circuit 21 so that the rewriting is performed only in the area Aa of the control signal M4 which becomes high level. Therefore, the output of the image memory circuit 21 is, as shown in FIG.
Two areas, area A and area Aa, can exist on the field (or frame).

The control signal M5 output from the motion detection circuit 20 is input to the memory control circuit 25, and the control signal M6 is input to the memory control circuit 26. In the memory control circuit 25, the image memory circuit 27 is responsive to the control signal M5.
The image memory circuit 27 is controlled so as to read the signal from. Further, the memory control circuit 26 controls the image memory circuit 24 so as to read a signal from the image memory circuit 24 according to the control signal M6.

As a result, the image memory circuits 27 and 2
From 4 onward, as shown in FIG. 9 (c), the area A is changed to "{x /
(X + y)} V ”The moved area P and the area Aa are“-
{Y / (x + y)} V ”The moved area Q is obtained.
Further, for the area P, the coefficient multiplier 28 outputs “x / (x +
y) ”times, and for the area Q,“ y / (x +
y) ”The multiplied signals are added by the adder circuit 30 to obtain the area Ab.

The output of the image memory circuit 21 including the area A and the area Aa, the output of the adder circuit 30 which outputs the area Ab, and the control signal S4 from the motion detection circuit 20 which makes only the area Ab high level are the selector circuit. Entered in 31
The selector circuit 31 outputs the signal from the adder circuit 30 as the output video signal So when the control signal S4 is at the high level, and outputs the signal from the image memory circuit 21 when the control signal S4 is at the low level. Output as So.

As a result, as shown in FIG. 9 (d), 1
Area A, area Aa, on the field (or frame)
The region Ab can be present, and the trajectory of the moving image region can be ideally drawn.

Next, a fourth embodiment of the present invention will be described. FIG. 10 shows a fourth video signal processing circuit according to the present invention.
It is a block diagram showing an example of. In this embodiment, a motion detection circuit 40 to which an input video signal Si is input, a selector circuit 41, and an image memory circuit 43 in a motion compensation type interpolation circuit 42.
And 44.

The motion detection circuit 40 has the same structure as the motion detection circuit 1 described above, and as shown in FIG. 11, the image memory circuit 40a, the subtraction circuit 40b, and the decoder circuit 4 are included.
0c, and the decoder circuit 40c outputs control signals M7, M8, S5 and S6, respectively.

In the motion detection circuit 40, the input video signal Si
Of the motion vector V is detected, and control signals M7 and M8 corresponding to the motion amount V are input to the memory control circuits 45 and 46 in the motion compensation type interpolation circuit 42. At this time, the control signal M7 is "M7 = {x / (x + y)} V" (where x and y are positive integers), and the control signal M8 is "M8 =-."
{Y / (x + y)} V ”(where x and y are positive integers)
Is.

In the memory control circuit 45, the image memory circuit 47 outputs a signal delayed by the same amount as the delay amount of the image memory circuit 40a in the motion detection circuit 40 in the image memory circuit 43.
, And the image memory circuit 47 is controlled so as to read the signal according to the control signal M7 from the motion detection circuit 40. As a result, in the image memory circuit 47, the video signal of the previous field (or frame) is changed to "{x / (x
+ Y)} V "The moved signal is obtained.

The memory control circuit 46 controls the image memory circuit 44 so as to read a signal from the image memory circuit 44 according to the control signal M8. As a result, in the image memory circuit 44, the input video signal Si is changed to "-{y / (x
+ Y)} V "The moved signal is obtained.

The outputs of the image memory circuits 47 and 44 are input to the coefficient multiplying circuits 48 and 49, respectively, and the outputs of the coefficient multiplying circuits 48 and 49 are added by the adding circuit 50 and input to the selector circuit 41. Coefficient multiplication circuit 48
Is “x / (x + y)”, and the coefficient of the coefficient multiplication circuit 49 is “y / (x + y)”.

In the motion detection circuit 40, the input video signal Si
Of the control signal S5 which detects the moving image area of the image memory circuit 47 and becomes a high level for the moving image area, and the control signal M from the image memory circuit 47.
7 or the control signal S6 which becomes high level only in the moving image area read from the image memory circuit 44 in response to the control signal M8 is input to the selector circuit 41.

In the selector circuit 41, the motion detection circuit 40
When the control signal S5 is at a high level, the input video signal Si is output based on the control signals S5 and S6 from
When 6 is at high level, the signal from the adder circuit 50 is output, and when both of the control signals S5 and 6 are at low level, the signal from the image memory circuit 51 is output.

The image memory circuit 51 has a capacity capable of storing a video signal of one field or more, and the memory control circuit 52
The video signal is delayed by one field or more under the control of the output of the selector circuit 4 as the output video signal So.
Return to 1.

The operation of this embodiment will be further described with reference to FIG. In the motion detection circuit 40, FIG.
As shown in (a), when the area A exists on the previous field (or frame) and the area A moves to the area Aa on the current field or frame, the moving area Aa and the movement amount V are detected and control is performed. The signals M7 and M8 are input to the memory control circuits 45 and 46.

The memory control circuit 45 controls the image memory circuit 47 so as to read the signal from the image memory circuit 47 in accordance with the control signal M7. Further, the memory control circuit 46 controls the image memory circuit 44 so that the signal from the image memory circuit 44 is read according to the control signal M8.

As a result, the image memory circuits 47 and 44 are
Then, as shown in FIG. 12 (b), the area A is changed to "{x /
(X + y)} V ”The moved area P and the area Aa are“ {−
y / (x + y)} V ”The moved area Q is obtained. Further, for the area P, the coefficient multiplier 48 calculates “x / (x +
y) ”times, and for the area Q,“ y / (x +
y) ”The respective multiplied signals are added by the adder circuit 50 to obtain the area Ab.

Further, the motion detection circuit 40 detects the moving image area of the input video signal Si, and the control signal S5 which becomes a high level with respect to the area Aa, the control signal M7 from the image memory circuit 47 or the control signal from the image memory circuit 44. The control signal S6 which becomes high level only in the moving image area read according to M8 is input to the selector circuit 41.

In the selector circuit 41, the control signals S5, S
6, when the control signal S5 is at the high level, the area Aa of the input video signal Si, when the control signal S6 is at the high level, the area Ab from the adder circuit 50, the control signals S5, S
When both 6 are at the low level, the signal from the image memory circuit 51 is output.

At this time, since the image memory circuit 51 stores the signal of the previous field (or frame), the output of the image memory circuit 51 should be output again when both the control signals S5 and S6 are at the low level. As shown in FIG. 12 (c), the selector circuit 41 allows the area A, the area Aa, and the area Ab to be present in one field, and the signal is input to the image memory circuit 51 to generate the moving image area. It becomes possible to draw the trajectory of.

In the above embodiment, α, x, y
Are both variable values, and the interpolation data is the variable value α,
The interpolation position is arbitrarily set by x and y. In the first and second embodiments, the decoder circuit is provided with a multiplier (not shown) for the motion vector V and the variable α, and the image memory circuits 3 and 11 are controlled according to the multiplier output αV. Thus, the position of the interpolation area Ab can be set arbitrarily. For example, when α = 0.5, the interpolation area Ab can be located at the center of the areas A and Aa.

In the third and fourth embodiments,
In the decoder circuit, the motion vector V and the variables x and y of "x /
(X + y) ”and“ −y / (x + y) ”are provided in the multiplier (not shown), and the multiplier output“ {x / (x +
y)} V "to control the image memory circuits 27 and 47, and the multiplier output" {-y / (x + y)} V "to control the image memory circuits 24 and 44 to obtain the interpolation area Ab. The position can be set arbitrarily.

For example, if x = 1 and y = 1, then "x /
(X + y) = 0.5 ”,“ −y / (x + y) = − 0.
5 ", the area P is located at the center of the areas A and Aa,
The area Q can be located at the center of each of the areas A and Aa. Furthermore, for the area P, "x / (x + y)"
= 0.5 "is multiplied by the coefficient multipliers 28 and 48 to obtain the area Q
For “y / (x + y) = 0.5”, the coefficient multiplier 29,
It is possible to locate the interpolation area Ab at the center of the area A and the area Aa by performing multiplication at 49 and adding the coefficient multipliers 28 and 48 outputs and the coefficient multipliers 29 and 49 outputs at the adders 30 and 50. it can.

[0066]

According to the present invention, a first image memory circuit for accumulating a moving image area in a field or a frame according to a motion and a moving image area between fields or a frame not included in an input video signal are moved. Second to interpolate according to
Since it has an interpolating means such as an image memory circuit or a motion compensation type interpolating circuit, and properly selects each output signal of the first image memory circuit and the interpolating means, an image having a fast motion, that is, a motion amount An effective or ideal image trajectory of a moving image can be drawn even for a large input video signal, and sufficient motion analysis and special effects can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram of a motion detection circuit shown in FIG.

FIG. 3 is an operation explanatory diagram of the embodiment shown in FIG.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

5 is a block diagram of the motion detection circuit shown in FIG.

FIG. 6 is an operation explanatory diagram of the embodiment shown in FIG.

FIG. 7 is a block diagram showing a third embodiment of the present invention.

8 is a block diagram of the motion detection circuit shown in FIG. 7. FIG.

FIG. 9 is an operation explanatory view of the embodiment shown in FIG.

FIG. 10 is a block diagram showing a fourth embodiment of the present invention.

11 is a block diagram of the motion detection circuit shown in FIG.

12 is an explanatory diagram of the operation of the embodiment shown in FIG.

FIG. 13 is a block diagram of a conventional video signal processing circuit.

14 is a block diagram of the motion detection circuit shown in FIG.

[Explanation of symbols]

 1, 10, 20, 40 Motion detection circuit 2, 14, 21, 51 (first) image memory circuit 3, 11 (second) image memory circuit 4, 15, 24, 52 (first) memory control Circuits 5, 13 (Second) Memory control circuit 6, 12, 31, 41 Selector circuit 22, 42 Motion compensation type interpolation circuit

Claims (4)

[Claims] 1. A motion detection circuit for detecting a motion of an input video signal and outputting a plurality of control signals, a first image memory circuit for storing at least one screen of the input video signal, and the motion detection circuit. A first memory control circuit for controlling the first image memory circuit so as to rewrite the moving image area of the input video signal by the control signal of 1., and a second image memory circuit for storing at least one screen of the input video signal. And a second moving image area of the input video signal is read at an appropriate position according to a control signal from the motion detection circuit to form a moving image area which is not included in the input video signal and output the second moving image area.
A second memory control circuit for controlling the image memory circuit, and the output of the first image memory circuit and the output of the second image memory circuit are selectively switched and output by a control signal from the motion detection circuit. And a selector circuit for controlling the video signal processing circuit. 2. A motion detection circuit that detects a motion of an input video signal and outputs a plurality of control signals, a first image memory circuit that stores the input video signal for at least one screen, and at least the video signal. A first memory control circuit for controlling the first image memory circuit so as to delay by one screen; a second image memory circuit for storing the input video signal for at least one screen; According to a control signal, the moving image area of the input video signal is read at an appropriate position, and the moving image area which is not included in the input video signal is formed and output.
A second memory control circuit for controlling the image memory circuit, and the input video signal, the output of the first image memory circuit, and the output of the second image memory circuit according to the control signal from the motion detection circuit. A video signal processing circuit, comprising: a selector circuit which selectively switches and outputs to the first image memory circuit. 3. A motion detection circuit which detects a motion of an input video signal and outputs a plurality of control signals, a first image memory circuit which stores the input video signal for at least one screen, and the motion detection circuit. A first memory control circuit that controls the first image memory circuit so that the moving image area of the input video signal is rewritten by the control signal of, and a moving image area of the input video signal by the control signal from the motion detection circuit, A motion compensation type interpolating means for moving the moving picture areas of the input video signal one screen before to the same position and taking an arithmetic mean to form and output a moving picture area not present in the input video signal, and the motion detecting circuit. A selector circuit for selectively switching between the output of the first image memory circuit and the output of the motion compensation type interpolating means in response to a control signal from A video signal processing circuit, characterized in that. 4. A motion detection circuit that detects a motion of an input video signal and outputs a plurality of control signals, a first image memory circuit that stores the input video signal for at least one screen, and at least the video signal. A first memory control circuit for controlling the first image memory circuit so as to delay by one screen; and a moving image area of the input video signal and the input video signal one screen before by a control signal from the motion detection circuit. Motion-compensating interpolation means for moving the moving picture areas to the same position and taking an arithmetic mean to form a moving picture area which is not included in the input video signal and outputting the moving picture area, and the input video by the control signal from the motion detecting circuit. A selector circuit for selectively switching a signal, an output of the first image memory circuit and an output of the motion compensation type interpolation means to output to the first image memory circuit. A video signal processing circuit comprising: a.