JPH0894680A - Timing-detecting circuit - Google Patents

Abstract

PURPOSE: To detect the timing when the level of a DC voltage changes by a simplified circuit. CONSTITUTION: An input voltage 3 is guided to a base of the detection circuit via a first differential circuit 11. A first load resistor R4 is connected to a collector which has a first transistor Q1 having a bias set at an A-class operating point. A collector of the first transistor Q1 is connected to the base via a second differential circuit 12. An emitter of the detection circuit is connected to the ground. A second transistor Q2 connected to a second load resistor R7 is set at the collector. Moreover, the detection circuit has a diode D1. One terminal of the diode D1 is connected to a base of the second transistor Q2, while the other terminal is connected to an emitter of the second transistor Q2. A current is thus supplied in a direction opposite to a direction of a base current in the second transistor Q2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing detection circuit for detecting the timing of level change when the level of a DC input voltage changes.

[0002]

2. Description of the Related Art Each of a slave unit and a master unit in an intercom are connected to each other by a pair of signal lines. Then, the audio signal is transmitted via the signal line from the slave unit to the master unit at some times and from the master unit to the slave units at some time. Further, a DC voltage is superimposed on the signal line, and the slave unit is configured so that the DC voltage superimposed on the signal line can be set to an arbitrary voltage of three types of voltages. . The master unit is configured to perform three types of operations corresponding to the three types of DC voltage set by the slave unit. As described above, in the intercom, the audio signal and the DC voltage are superimposed on the signal line. For this reason, when the DC voltage is changed, the change in the DC voltage becomes a noise signal, and this noise signal causes an unpleasant noise sound from the speaker of the parent device and the speaker of the other child device. In order to prevent the generation of this unpleasant noise sound, the intercom is provided with a detection circuit for detecting the timing at which the DC voltage superimposed on the signal line changes. This detection circuit needs to detect the timing at which any given level changes from any given level to any of the three different levels of the DC voltage. Therefore, a plurality of comparators for detecting each of the three levels are provided, and at least one of the outputs of the plurality of comparators is provided.
If one of them changes, it is determined that the DC voltage has changed. When a change in the DC voltage is detected, the operation of the amplifier circuit that amplifies the audio signal is stopped for a certain period of time to prevent noise noise from being generated from the speaker.

[0003]

As described above, the detection circuit is configured to detect the level change of the DC voltage by using the plurality of comparators. However, although the comparator is an IC element and is configured to be easily handled as an element, the equivalent circuit is a complicated circuit using a large number of transistors. It had a complicated circuit configuration.

The present invention was devised to solve the above problems, and an object of the present invention is to detect the timing at which a DC voltage changes from an arbitrary level to a different arbitrary level. The purpose of the present invention is to provide a timing detection circuit that can be implemented by a simplified circuit. The object of the invention according to claim 2 is to detect the timing of the change of the DC voltage superimposed on the signal line connecting the slave unit and the master unit of the intercom with a simplified circuit. An object of the present invention is to provide a timing detection circuit capable of preventing the equivalent circuit configuration of a cam from becoming complicated.

[0005]

In order to solve the above-mentioned problems, in the timing detection circuit according to the invention described in claim 1, an input voltage is introduced to its input terminal through a first differentiating circuit and its output terminal. A first load resistor is connected to the first load resistor, and the bias is set to the class A operating point.
An output terminal of the first transistor is connected to its base via a second differentiating circuit, its emitter is connected to the ground level, and its collector is connected to a second transistor to which a second load resistor is connected. A diode having one terminal connected to the base of the second transistor and the other terminal connected to the emitter of the second transistor, the diode causing a current to flow in a direction opposite to a direction in which the base current of the second transistor flows. It has a structure. Further, in the timing detection circuit according to the invention of claim 2, the audio signal and the DC voltage are superimposed on the signal line connecting the slave unit and the master unit, and the master unit is in a period set by the timer. The DC voltage is applied to an intercom that includes an amplifier circuit that stops the amplification operation of the audio signal and that performs a preset operation for each of a plurality of values of the DC voltage set by the slave unit. As the input voltage
Of the first transistor via the differentiating circuit, and the collector output of the second transistor is used as a trigger signal for starting the operation of the timer.

[0006]

The operation of the invention according to claim 1 will be described below. First
When the transistor is a bipolar transistor, the input terminal and the output terminal become the base and the collector. When the first transistor is a FET, the input terminal and the output terminal are the gate and the drain. Therefore, the case where the input terminal is the base and the output terminal is the collector will be described below. Further, the diode causes a current to flow in a direction opposite to the direction in which the base current of the second transistor flows. Therefore, when the second transistor is an NPN transistor, the cathode of the diode is connected to the base of the second transistor and the anode is connected to the emitter. When the second transistor is a PNP transistor, the diode anode is connected to the base of the second transistor and the cathode is connected to the emitter. In addition, the ground level is also determined by the potential of the second transistor of the NPN type or the PNP type. Therefore, the case where the second transistor is an NPN transistor will be described below.

Since the bias of the first transistor is set to the class A operating point, the collector of the first transistor receives the first differential signal both when the input voltage falls and when it rises. The differentiated waveform by the circuit is inverted and a shaped waveform appears. That is, the first
A pulse appears in the collector of the transistor in the direction in which the voltage rises when the input voltage falls. When the input voltage rises, a pulse appears in the direction in which the voltage drops. Therefore, the pulse in the direction of increasing voltage causes the base current to flow through the second transistor through the second differentiating circuit. As a result, an L level pulse appears at the collector of the second transistor. Further, the pulse in the direction in which the voltage drops causes a current to flow through the diode via the second differentiating circuit. Therefore, a voltage equal to the forward voltage of the diode is generated at the cathode of the diode, and this voltage causes a base current to flow in the second transistor. As a result, an L level pulse appears at the collector of the second transistor. That is, an L-level pulse appears in the collector of the second transistor both when the input voltage falls and when it rises. Further, the L level pulse indicates the timing of the change of the input voltage at the falling edge.

The operation of the invention according to claim 2 will be described below.
When the slave unit changes the set value of the DC voltage, noise generated by the change of the DC voltage is introduced to the amplifier circuit. However, when the DC voltage changes, a pulse indicating the timing of the change appears at the collector of the second transistor. Therefore, the timer stops the amplification operation of the amplification circuit when the DC voltage changes. As a result, the amplifier circuit does not amplify the noise generated by the change in the DC voltage, so that the noise is removed from the output of the amplifier circuit. Then, when the DC voltage noise disappears from the signal line after a lapse of a predetermined period, the amplifier circuit restarts the amplifying operation and returns to the normal operation state.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an electrical configuration of an intercom using an embodiment of the timing detection circuit of the present invention. This embodiment is roughly divided into a master unit 1 and a signal line 3
It is configured by a slave unit 2 connected to the master unit 1 via the master unit 1, and up to nine slave units 2 can be connected to the master unit 1, and a configuration similar to that of the slave unit 2 is provided. One of the doorphones it has is connectable. A voice signal is sent from the master unit 1 to the slave unit 2 at some times and from the slave unit 2 to the master unit 1 via the signal line 3, and a route for sending the voice signal to the signal line 3, An illustration of a path for extracting the audio signal from the signal line 3 is omitted.

The voltage dividing circuit consisting of resistors R11 and R12 is
It is a block for generating a DC voltage to be superimposed on the signal line 3. The timing detection circuit 4 to which the signal line 3 is guided detects the timing at which the level of the DC voltage superimposed on the signal line 3 changes, and the detected timing is
The block is shown by the falling edge of the L level pulse. Then, an L level pulse indicating the timing of the change in the level of the DC voltage is sent to the timer 5 as a trigger signal.

The timer 5 is a block that uses the falling edge of the L level pulse output from the timing detection circuit 4 as a trigger signal to set the output 24 sent to the amplifier circuit 10 to H level for a predetermined period. Specifically, it is a software timer that uses a CPU that operates with a high-speed clock, and is a retriggerable timer that can initialize the time counting period during timer operation. The predetermined period is set to about 300 ms. The control unit 6 to which the signal line 3 is guided via the diode D2 causes the DC voltage superimposed on the signal line 3 to operate at one of three levels by operating a switch (described later) of the slave unit 2. When set to, the base unit 1 according to the set level
Is a block that controls the operation of the. Capacitor C
The amplifier circuit 7 to which the signal line 3 is connected via 3 is a block for amplifying the audio signal from the slave unit 2 guided by the signal line 3 to a predetermined level, and the amplified audio signal is variable resistor. Send to VR1.

The amplifier circuit 10 to which the output of the amplifier circuit 7 is guided through the variable resistor VR1 is a power amplifier circuit that stops the amplification operation when the output of the timer 5 is at the H level, and the four amplifier circuits are provided. The transistors Q3 to Q6, two diodes D3 and D4, and the power amplifier 8 are main components. The output of the amplifier circuit 10 is the variable resistor VR.
2 is connected to the speaker 9 of the base unit 1 via
It is output to each of the signal lines 3, ... Connected to each of the slaves 2 ,. The input 101 led to the base of the transistor Q5 shows the signal path of the audio signal such as music led via a line such as a dedicated line.

The signal line 3 is led to the a contact of the switch 13 via the diode D5. The a contact and the b contact are connected via a capacitor C4 and a resistor R13. The b contact and the c contact are connected via a resistor R14, and
They are connected via a series circuit composed of a capacitor C5 and a resistor R15. Further, the diode D6 is connected to the resistor R15.
Are connected in parallel. A speaker 14 also serving as a microphone is connected to the d-contact of the switch 13. The switch 13 is specifically configured by three switches, and corresponding to the operated switch, the a contact and the d contact, the b contact and the d contact, or the c contact and the d contact are connected. To be done.

As described above, this embodiment has the same construction as the intercom known in the prior art.
The internal structure of the timing detection circuit 4 is only different from that of the prior art.

FIG. 1 is a circuit diagram showing the detailed electrical connection of the timing detection circuit 4 shown in FIG. 2, and shows the timing detection circuit according to the first aspect of the invention.

The first transistor Q1 is an NPN type or PNP type bipolar transistor or FET.
However, in this embodiment, an NPN type transistor is used. Therefore, the input terminal described in claim 1 means the base, and the output terminal means the collector. Therefore, in the following description, the input terminal is referred to as the base and the output terminal is referred to as the collector. The second transistor Q2 can be an NPN type or a PNP type, but in this embodiment, it is an NPN type transistor. Therefore, the ground level described in claim 1 indicates a ground level which is a potential of 0V.

The details of the configuration are shown below. The DC voltage superimposed on the signal line 3 is input as an input voltage through the first differentiating circuit 11 including the capacitor C1 and the resistor R1 to generate the first voltage.
Is led to the base of the transistor Q1. Also the first
A base current is supplied to the base of the transistor Q1 by the resistors R2 and R3 in order to operate the first transistor Q1 in the class A operation. Also, the first transistor Q1
The emitter of is connected to ground and the first transistor Q1
A first load resistor R4 is connected to the collector of the.

The collector of the first transistor Q1 has a second differentiating circuit 12 including a capacitor C2 and a resistor R5.
Is connected to the base of the second transistor Q2. Also, one terminal is connected to the base of the second transistor Q2, and the other terminal is connected to the second transistor Q2.
The diode D1 connected to the emitter of is an element for flowing a current in the direction opposite to the direction in which the base current of the second transistor Q2 flows. Therefore, the cathode of the diode D1 is connected to the base of the second transistor Q2, and the anode is connected to the emitter of the second transistor Q2 (both the anode and the emitter are grounded). In addition, the base of the second transistor Q2,
A resistor R6 is connected to reduce the base impedance when the base current does not flow. The second load resistor R7 is connected to the collector of the second transistor Q2. The collector of the second transistor Q2 is led to the timer 5 as the output 23 of the trigger signal.

The time constant of the first differentiating circuit 11 is several meters.
Although set to s, when the input voltage falls, the time constant between the input (indicated by 3) and the base of the first transistor Q1 is several tens of ms due to the influence of the resistors R2 to R4. However, when the input voltage rises, since the base impedance of the first transistor Q1 is low, the time constant is approximately equal to the time constant of the first differentiating circuit 11 itself, which is several ms. Second differentiating circuit 12
The time constant of is set to several ms. The impedance of the second differentiating circuit 12 is set to a value that is several tens of times the impedance of the first load resistor R4. Therefore, the time constant between the collector of the first transistor Q1 and the base of the second transistor Q2 is substantially equal at both the rising time and the falling time of the collector voltage of the first transistor Q1 and is several ms. Is.

FIG. 3 is a timing chart showing the signal waveforms of the main parts of the embodiment having the above construction. The operation of the embodiment will be described below with reference to FIG.

When the a-contact and the d-contact of the switch 13 of the slave unit 2 are connected, the b-contact and the d-contact are connected, or the c-contact and the d-contact are connected, respectively. Is the signal line 3 depending on the connection of each contact.
The level of the DC voltage superimposed on is changed. Therefore, the control unit 6 detects the type of the switch operated in the slave unit 2 by detecting the level of the DC voltage superimposed on the signal line 3. Then, in order to cause the master device 1 to perform the operation instructed by the detected switch, the operation of the corresponding block inside the master device 1 is controlled. That is, the control unit 6
Corresponds to the type of switch operated, switch 1
Control for transmitting from the handset 2 whose 3 is operated to the base unit 1 and the other handset, control for transmitting only from the handset 2 to the base unit 1, or hands-free. Therefore, the control for stopping the operation of transmitting from the slave 2 to the master 1 is performed.

It is assumed that the switch 13 is operated and the input voltage changes as indicated by 3 in FIG. That is, it is assumed that, for example, the b contact and the d contact are closed at time T1, the contact 32 is opened at time T3 after the pulse 32 is generated due to the chattering at time T2. Therefore, at time T1, a pulse 31 appears in the collector of the first transistor Q1 in the direction of increasing voltage, as indicated by 22. At time T2, a pulse 33 having a width substantially equal to the width of the chattering pulse 32 appears in the voltage decreasing direction. Further, at time T3, the pulse 34 appears in the direction in which the voltage drops.

As a result, when the pulse 31 rises, a current as a differentiated waveform by the second differentiating circuit 12 flows through the base of the second transistor Q2. Therefore, an L level pulse 35 appears at the collector of the second transistor Q2, as indicated by 23. When the pulse 31 falls, a current as a differential waveform by the second differentiating circuit 12 flows through the diode D1 and a forward voltage appears at the cathode of the diode D1. Therefore, a current due to the forward voltage generated at the cathode of the diode D1 flows through the base of the second transistor Q2. As a result, an L-level pulse 36 appears at the collector of the second transistor Q2. Similarly, the second
In the collector of the transistor Q2 of, the L-level pulse 37 appears corresponding to the pulse 33, and the pulses 38 and 39 appear corresponding to the pulse 34.

Therefore, the output 24 of the timer 5 is the time T1.
When it becomes, it is triggered by the pulse 35 and becomes H level. It is then retriggered by pulse 36. Therefore, when approximately 300 ms has elapsed from the re-trigger,
The output 24 returns to the L level. Also, output of timer 5 24
At time T2, the pulse is triggered by the pulse 37 and becomes H level. It is then retriggered by pulses 38, 39. Therefore, when approximately 300 ms has elapsed from the re-triggering by the pulse 39, the output 24 returns to the L level.

On the other hand, in the amplifier circuit 10, when the output 24 of the timer 5 becomes H level, the transistors Q3 and Q4 are turned on and the input of the power amplifier 8 becomes zero. That is, the amplification circuit 10 stops the amplification operation when the output 24 of the timer 5 is at the H level. That is, the periods t1 and t2
Then, the amplification circuit 10 stops the amplification operation. On the other hand, noise occurs due to the level change of the DC voltage superimposed on the signal line 3 at the times within the periods t1 and t2. Therefore, the output of the power amplifier 8 does not show noise generated by operating the switch 13 and changing the DC voltage superimposed on the signal line 3. That is, since the base unit 1 is requested to perform a predetermined operation, even when the switch 13 is operated in the handset 2, noise generated by the operation is prevented from being generated from the speaker 9 of the base unit 1. It Further, it is possible to prevent noise from being generated from the speaker of the other child device.

[0026]

According to the first aspect of the present invention, the input voltage is led to the input terminal through the first differentiating circuit, and the first load resistor is connected to the output terminal. , A first transistor whose bias is set to the class A operating point is provided, and the output terminal of the first transistor is connected to its base via a second differentiating circuit,
The emitter is connected to the ground level, and the collector is provided with the second transistor to which the second load resistor is connected. In addition, one terminal is connected to the base of the second transistor, the other terminal is connected to the emitter of the second transistor, and a diode that allows a current to flow in a direction opposite to the direction in which the base current of the second transistor flows. It has a configuration provided. Therefore, an L-level pulse appears in the collector of the second transistor both when the input voltage falls and when it rises. That is, the detection of the timing when the DC voltage changes from an arbitrary level to a different arbitrary level is detected by two differentiating circuits, two transistors, two load resistors, an element for setting a class A operating point, and 1 It is possible to do this with a simplified circuit of two diodes.

In the timing detection circuit according to the second aspect of the present invention, the voice signal and the DC voltage are superimposed on the signal line connecting the slave unit and the master unit, and the master unit has a period set by a timer. In the above, the present invention is applied to an intercom that includes an amplifier circuit that stops an amplifying operation of an audio signal and performs a preset operation for each of a plurality of DC voltage values set by a slave unit. Then, using the DC voltage as the input voltage, the first voltage is passed through the first differentiating circuit.
Of the second transistor, and the collector output of the second transistor is used as a trigger signal for starting the operation of the timer. Therefore, the timing of the change in the DC voltage superimposed on the signal line connecting the master unit and the slave unit is detected by the simplified circuit, and the intercom equivalent circuit configuration is prevented from becoming complicated. It is possible to do.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an electrical connection of an embodiment of a timing detection circuit according to the present invention.

FIG. 2 is a block diagram showing an electrical configuration of an intercom using an embodiment of a timing detection circuit according to the present invention.

FIG. 3 is a timing chart showing a signal waveform of a main part.

[Explanation of symbols]

 1 Master Unit 2 Slave Unit 3 Signal Line 4 Timing Detection Circuit 5 Timer 10 Amplification Circuit 11 First Differentiation Circuit 12 Second Differentiation Circuit D1 Diode Q1 First Transistor Q2 Second Transistor R4 First Load Resistance R7 Second 2 load resistance

Claims (2)

[Claims] 1. An input voltage is introduced to its input terminal through a first differentiating circuit, a first load resistor is connected to its output terminal, and a bias is set to a class A operating point. Of the first transistor, the base of which is connected to the output terminal of the first transistor through the second differentiating circuit, the emitter of which is connected to the ground level, and the collector of which is connected the second load resistor. Two transistors and one terminal connected to the base of the second transistor,
A timing detection circuit, characterized in that the other terminal is connected to the emitter of the second transistor, and a diode that allows a current to flow in a direction opposite to the direction in which the base current of the second transistor flows. 2. A voice signal and a DC voltage are superimposed on a signal line connecting the slave unit and the master unit, and the master unit stops the amplification operation of the voice signal during a period set by a timer. An intercom that includes an amplifier circuit and performs a preset operation for each of a plurality of values of the DC voltage set by the slave unit, wherein the DC voltage is used as the input voltage, and a first differentiation is performed. 2. The timing detection circuit according to claim 1, wherein the timing detection circuit is led to the input terminal of the first transistor through a circuit and the collector output of the second transistor is used as a trigger signal for starting the operation of the timer.