JPH0895783A - Variable word length type microcomputer - Google Patents

Abstract

PURPOSE: To obtain the microcomputer which varies instruction word length without decreasing the kinds of instructions by specifying the instruction word length not with an instruction code, but in a microcomputer. CONSTITUTION: Data are previously set in a word length specification register 107 with a specific instruction. For example, a 32-bit instruction mode when the data set in the word length specification register 107 is '0' or a 16-bit instruction mode when '1' is set. Then a word length specification signal 108 is outputted from the word length specification register 107 to an instruction decoder 103. Consequently, the need to use the bit field of an instruction code to specify the instruction word length is eliminated, and consequently the word length of the instruction can dynamically be varied without decreasing the kinds of instructions, thereby optimizing the performance and object side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, it relates to a multi-bit microcomputer such as 32-bit.

[0002]

2. Description of the Related Art In recent years, the number of bits of microcomputers has increased, and 32-bit or more microprocessors and single-chip microcomputers have come into general use.

For example, a 32-bit microcomputer generally has an internal register or a data bus with a bit width of 32 bits in many cases.
The bit length per instruction is often 32 bits.

FIG. 3 shows a block diagram of a typical configuration of a conventional microcomputer.

Referring to FIG. 3, the instruction supplied from instruction bus 101 is decoded by instruction decoder 303, and control signal line group 106 is output to execution unit 105.

As shown in FIG. 4, an instruction having a 32-bit format includes, for example, an instruction code, a register designation field (reg2) that designates a second register, and a register designation field (reg2) that designates a first register. reg
1), the field that stores the immediate diet value (im
m), the operation is performed between the contents of the first register specified by reg1 and the sign extension data of the immediate value (imm), and the operation result is the target register specified by reg2 (write register). ) Is stored in the second register.

At this time, the instruction decoder 303 has the execution unit 105.
The control signal line group 106 for outputting the calculation designation, the read register designation, the write register designation, the immediate data (imm), etc. is output.

[0008]

If the number of bits per instruction increases, the object size of the entire program also increases.

Assuming that the number of instructions used in one program is the same, in a 32-bit microcomputer, the object size of the program is twice as large as that of a 16-bit microcomputer in simple calculation. Become.

Therefore, in a microcomputer equipped with a cache, if the size of the cache memory is the same, the hit rate of the 32-bit microcomputer is lower than that of the 16-bit microcomputer.

Further, it has a built-in instruction ROM storing instructions.
In a 2-bit single-chip microcomputer, the built-in ROM capacity must be doubled compared with the case of 16-bit.

By the way, recently, in a 32-bit microcomputer or the like, a microcomputer capable of fixing the instruction word length to 16 bits or a mixed instruction set of 16 bits and 32 bits has also been developed to reduce the object size. Is being promoted.

As one of conventional methods for varying the instruction word length in a microcomputer, as shown in FIG. 4, a bit (16b) for designating the instruction word length in an instruction code.
There is a method of providing. For example, Reference 1 ("16-bit V Series (Instruction Edition)", NEC Corporation, December 1992, page 15)
Discloses a microcomputer in which a bit (W bit) for designating an instruction word length is provided in an instruction code. As a similar configuration, reference 2 (“CYRIX Cx486SLC MIC
ROPROCESSOR Data Sheet ", published by CYRIX, February 1992, 6-
(See pages 2, 6-4, 6-23, etc.) also discloses a microcomputer in which a W field for designating an instruction word length is provided in an instruction code.

However, this method imposes restrictions on the types of instructions.

That is, for example, in FIG. 4, there are 2 ⁶ = 64 types of instructions when the instruction code is 6 bits, but if 1 bit (16b) of the instruction code is used as the designated bit of the instruction word length The number of instruction codes that can be actually used is 5 bits, and the number of instruction types is reduced to 2 ⁵ = 32 types, which is a half.

As described above, some recent 32-bit microcomputers have a fixed instruction word length of 16 bits or an instruction set in which 16 and 32 bits are mixed.

However, although such a microcomputer is effective for an application in which the object size is given the highest priority, a command word length of 32 bits is often desirable in the microcomputer in which the performance is given the highest priority.

Further, if the instruction code length designation bit is included in the operation code, there is a problem that the kinds of instructions that can be used are greatly reduced.

Therefore, an object of the present invention is to solve the above problems and to provide a microcomputer in which the instruction word length is variable without depending on the instruction code, that is, without reducing the type of instruction.

[0020]

According to the present invention, the above-mentioned object is to use an instruction word length designating means for designating an instruction word length and a word length designating signal from the instruction word length designating means as input. And a variable word length microcomputer for varying the instruction word length according to the value of the length designation signal and decoding the instruction.

Further, in the variable word length type microcomputer of the present invention, the command word length designating means comprises a storage means.

In the variable word length type microcomputer of the present invention, preferably, the storage means is set to a value by executing a predetermined instruction.

Further, in the variable word length microcomputer of the present invention, the instruction word length designating means includes an address comparing means.

In the variable word length microcomputer of the present invention, preferably, an instruction buffer in which an instruction and a predetermined high-order bit of an address corresponding to the instruction are stored in a pair form, and a range in which the instruction word length can be changed. An address information storage unit for storing a predetermined high-order bit of an address defining the address, the address comparison unit compares the address of the instruction buffer with the address of the address information storage unit, and the address is within a predetermined range. In this case, the control is performed so that the word length of the instruction code is changed.

[0025]

The variable word length microcomputer according to the present invention is different from the conventional example in that the instruction word length is specified inside the microcomputer regardless of the instruction code.

According to the present invention, it is not necessary to use the bit field of the instruction code for designating the instruction word length. Therefore, the word length of the instruction code can be dynamically changed without reducing the types of instructions. It is possible to optimize the performance and the object size.

Further, according to the present invention, the storage means for designating the instruction word length is configured such that its value is set by the execution of the predetermined instruction, so that by executing the predetermined instruction in advance, It is possible to control the instruction word length dynamically, which facilitates the control.

Furthermore, according to the present invention, in particular, a built-in ROM
When there are many restrictions on the program capacity, the object size can be reduced by changing the instruction word length according to the address area. That is, the internal organs RO
By making the instructions in the M area 16 bits long and the instructions in the other address areas 32 bits long, the program size of the built-in ROM can be reduced and at the same time stored in an address area other than the internal ROM, such as an external memory. The instruction word length of the application program etc. is 32 bits, and the performance such as processing speed can be improved.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

[0030]

First Embodiment A first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, 101 is a 32-bit instruction bus, 102 is an instruction buffer that temporarily holds instructions, 103 is an instruction decoder that decodes instructions, and 104 is an instruction that transfers instructions from the instruction buffer 102 to the instruction decoder 103. A bus, 105 is an execution unit that executes instructions, and 106 is an instruction decoder 103 to an execution unit 10
A control signal line group for outputting a control signal to 5 and a word length designation register 107 for designating an instruction word length.

From the word length designation register 107 to the instruction decoder 103
A word length designation signal 108 is output to.

Data is set in the word length designation register 107 in advance by executing a predetermined instruction. For example, when the data set in the word length designation register 107 is "0", the 32-bit instruction mode is set, and when the data is "1", the 16-bit instruction mode is set.

When "0" is written in the word length designation register 107 and the 32-bit instruction mode is selected, the word length designation signal
It is transmitted to the instruction decoder 103 by 108, and the instruction decoder 10
3 receives the instruction code of 32 bits from the instruction buffer 102 and decodes the instruction. The instruction decoder 103 uses the control signal line group 106 based on the decoded 32-bit instruction,
The execution unit 105 is designated to perform calculation, transfer, and register selection.

On the other hand, when "1" is written in the word length designation register 107 and the 16-bit instruction mode is selected, it is transmitted to the instruction decoder 103 by the word length designation signal 108, and the instruction decoder 103 is instructed by the instruction buffer 102. Receives 16-bit instruction code from and decodes the instruction. The instruction decoder 103 is
Based on the decoded 16-bit instruction, the control signal line group 106 gives an operation designation, a transfer designation, a register selection designation, etc. to the execution unit 105.

[0036]

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG. 2, elements having the same functions as those in FIG. 1 are designated by the same reference numerals.

Referring to FIG. 2, the difference between this embodiment and the first embodiment is that the instruction word length is specified by address comparison. Only the differences from the first embodiment will be described below.

In FIG. 2, 207 is an address comparator, and 209 is a register that holds the upper n bits (n is a predetermined integer) of the address to be compared.

The instruction buffer 202 holds the instruction code and the upper n bits of the address corresponding to the instruction code in a pair format.

The address comparator 207 compares the contents of the register 209 with the upper bits (n bits) of the address of the instruction buffer 202, and if they match, sets the word length designation signal 208 to "1" to the instruction decoder 103. Signals that it is in 16-bit instruction mode. On the other hand, when the contents of the register 209 and the upper bits (n bits) of the address of the instruction buffer 202 do not match, the address comparator 207 determines that the word length designation signal 20
8 is set to "0" and it is transmitted to the instruction decoder 103 that it is in the 32-bit instruction mode.

That is, in this embodiment, the 16-bit instruction mode is set when the address of the instruction is within a certain range. This is a single chip with built-in ROM
Limited built-in ROM for microcomputers
This is effective when you want to embed many instruction codes depending on the area.

The address comparator 207 is provided with, for example, two registers 209 for designating the upper limit and the lower limit of the address in the 16-bit instruction mode, and the upper n bits of the address of the instruction buffer 202 are the upper limit and the lower limit. When it is within the range, the instruction decoder 1 sets the word length designation signal 208 to "1".
Needless to say, the 16-bit instruction mode may be transmitted to 03.

As described above, if the number of bits per instruction increases, the object size of the entire program also increases. Therefore, assuming that the number of instructions used by one program is the same, 16 bits are required for a 32-bit microcomputer.
The object size of the program is doubled by simple calculation compared with the bit microcomputer. Therefore, in a microcomputer equipped with a cache, if the cache size is the same, the hit rate will decrease. In addition, in a single-chip microcomputer that has a built-in instruction ROM, the built-in ROM capacity must be doubled.

If a bit field specifying the 32-bit instruction mode and the 16-bit instruction mode is provided in the bit field in the operation code, the types of instructions are reduced to half.

On the other hand, according to the microcomputer of the above embodiment, it is possible to dynamically change the word length of the instruction code without reducing the types of instructions, so that the performance and the object size are optimized. Can be realized. In particular, when there are many restrictions on the program capacity such as a built-in ROM, the object size can be reduced by changing the word length by the address area, and the effect can be expected more.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments and includes various embodiments according to the principle of the present invention. For example, although the above embodiments have been described in the context of a 32-bit microcomputer, the present invention includes a 64-bit microcomputer (including a 64-bit wide data and address bus and 64-bit instructions). The same applies to the microcomputer of. In this case, the word lengths of the 64-bit instruction mode and the 32-bit instruction mode are selected, but the 16-bit word length may be further selected.

[0047]

As described above, according to the microcomputer of the present invention, it is possible to dynamically change the word length of an instruction without reducing the types of instructions, and to optimize performance and object size. Can be achieved.

Further, according to the present invention, the instruction word length is set by the value held in the storage means, and the instruction word length is changed by executing a predetermined instruction in advance and setting the value appropriately. The instruction word length can be dynamically specified and the instruction word length can be easily controlled.

Furthermore, according to the present invention, in particular, a built-in ROM
When there are many restrictions on the program capacity, etc., the word size can be changed based on the address area, so that the object size stored in the internal ROM can be reduced, and the effect of the present invention can be further expected. It is a thing. That is, according to the present invention, the instruction stored in the internal ROM allocated to the predetermined address area is automatically executed in the 16-bit instruction mode by the address comparison,
Instructions stored in the memory corresponding to other address areas are executed in 32-bit instruction mode, so the internal ROM
It is possible to achieve optimization with high-speed processing in the 32-bit instruction mode while achieving reduction in the object size of.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a typical configuration of a conventional microcomputer.

FIG. 4 is a diagram showing an example of a format of a conventional 32-bit instruction.

[Explanation of symbols]

 101 32-bit instruction bus 102 Instruction buffer 103, 303 Instruction decoder 104 Instruction bus 105 Execution unit 106 Control signal line group 107 Word length designation register 207 Comparator 108, 208 Word length designation signal 209 register

Claims (5)

[Claims] 1. A command word length designating means for designating a command word length,
An instruction decoding means for inputting a word length designating signal from the instruction word length designating means and varying an instruction word length according to a value of the word length designating signal to decode an instruction. Word length type microcomputer. 2. The variable word length type microcomputer according to claim 1, wherein said instruction word length designating means comprises a storage means. 3. The variable word length type microcomputer according to claim 1, wherein said instruction word length designating means includes address comparing means. 4. The variable word length type microcomputer according to claim 2, wherein said storage means has a value set by execution of a predetermined instruction. 5. An instruction buffer in which an instruction and a predetermined high-order bit of an address corresponding to the instruction are stored in a pair form, and an address which stores a predetermined high-order bit of an address defining a range in which a command word length is variable. An information storage unit is provided, and the address comparison unit compares the address of the instruction buffer with the address of the address information storage unit and varies the word length of the instruction code when the address is within a predetermined range. 2. The variable word length type microcomputer according to claim 1, which is controlled.