JPH0895894A - Computer system - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a computer system characterized by a method of selecting a register or a port inside a peripheral circuit when a CPU accesses the peripheral circuit, and relates to an address space occupied by one peripheral circuit. Without increasing
The area accessed by the CPU is increased, such as a large number of registers or ports inside one peripheral circuit. [Configuration] internal register of the peripheral circuit by the read signal RD _{_} to write signal WR _{_} the time length R1, R
A register to be accessed is selected from 2, ..., Rn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system characterized by a method of selecting a register or a port inside a peripheral circuit when a CPU accesses the peripheral circuit.

[0002]

2. Description of the Related Art Generally, a computer system is a CP
It is composed of a U (Central Processing Unit), a memory, and a peripheral circuit (I / O device). CP
U is connected to the memory and peripheral circuits by a control signal line such as a data bus, an address bus, a read signal line for transmitting a read signal and a write signal line for transmitting a write signal. In the case of a memory, a plurality of data is stored in the memory. Which storage area to read the data from among the plurality of data stored in the memory,
Alternatively, which storage area to write the data to is determined by the CPU
Is specified by the address output by. In addition, there are many registers or ports in the peripheral circuit, and these registers or ports are often accessed selectively.

FIG. 9 shows a peripheral circuit having the above-mentioned configuration and C.
It is the figure which showed the connection relationship with PU. For simplicity, only one peripheral circuit is shown here. As shown in FIG. 9, the CPU and the peripheral circuits include a data bus, an address bus,
Chip select signal line for transmitting a _{_} chip select signal CS, a read signal line for transmitting a _{_} read signal RD, are connected by the write signal line for transmitting a write signal WR _{_.}

The decode logic decodes a part of the bits of the address signal output from the CPU, for example, the upper 4 bits of the 8-bit address signal to decode a plurality of peripheral circuits (see FIG. 9). Chip select signal _{CS_} to one of the two (only one shown). In addition, some of the remaining bits of the address signal are input to the peripheral circuit, and in the peripheral circuit, as shown in FIG.
, Rn exists, the register or port that the CPU is trying to access is selected from among the plurality of registers or ports R1, R2, ..., Rn by the combination of some of the input bits. It

For example, when four address signal lines are connected to the peripheral circuit, 16 internal registers or ports can be selected by a combination of address bits. Generally, 2 ⁿ registers or ports can be selected by ⁿ address signal lines.

[0006]

In the above-mentioned conventional method, 1
When the number of registers or ports inside one peripheral circuit increases, it is necessary to connect the number of address signal lines corresponding thereto. The increase in the number of address signal lines to connect is
It means an increase in the address space occupied by the peripheral circuits,
It is conceivable that the number of peripheral circuits connected to the CPU increases and the addresses run short. For example, if up to 2 ⁵ = 32 registers or ports inside one peripheral circuit are allowed, the number of peripheral circuits that can be connected to a CPU with an 8-bit address is limited to 2 ^8-5 = 2 ³ = 8. Will end up.

Further, when the CPU and the peripheral circuit are composed of separate LSIs, an increase in the number of connected address signal lines results in an increase in the number of terminals of the peripheral circuit LSI.
This also leads to an increase in the cost of the peripheral circuit LSI. In view of the above circumstances, the present invention provides a computer capable of increasing the area, such as a register or a port, which is accessed by the CPU in one peripheral circuit without increasing the address space occupied by the one peripheral circuit. The purpose is to provide a system.

[0008]

A computer system of the present invention which achieves the above object comprises a CPU and a peripheral circuit having a plurality of areas accessed by the CPU, and the CPU has a variable time length toward the peripheral circuit. Of the access signal and the peripheral circuit selects an area to be accessed according to the temporal length of the access signal.

Here, in the computer system of the present invention, the CPU executes an instruction to change the temporal length of the access signal, thereby sending an access signal of a temporal length corresponding to the instruction. Alternatively, in the above computer system of the present invention, a value is set by the CPU, and at the timing when the CPU sends an access signal, the CPU waits for a time length corresponding to the value. An auxiliary peripheral circuit for sending a signal may be provided.

Here, the "access signal" means a read signal for reading data from the peripheral circuit, a write signal for writing data to the peripheral circuit, and the like. Also,
The "area accessed by the CPU" refers to the above-mentioned registers, ports, etc., but may be any area to which data is written or read by the CPU, regardless of its function or name. .

[0011]

In the computer system of the present invention, the CPU is
Access signals such as read signals and write signals of variable time length are output to the peripheral circuit, and the peripheral circuit side selects the area to be accessed according to the time length of the access signal. A large number of regions such as registers or ports can be arranged inside the peripheral circuit without expanding the address space of the peripheral circuit.

To change the time length of the access signal,
C for executing an instruction to change the time length of an access signal
Although a PU may be prepared, an auxiliary peripheral circuit that sends a wait signal having a time length corresponding to the set value to the CPU at the timing when the CPU sends an access signal is provided, and
A conventional general-purpose PU may be used as it is.

[0013]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing an embodiment of a computer system of the present invention. For simplicity, only one peripheral circuit is shown here. Further, in FIG. 1, the same reference numerals, names, etc. are described for the same elements as those in the conventional example (see FIG. 9).

In the computer system shown in FIG.
The difference from the conventional computer system shown in FIG. 9 is that
The point is that the address lines forming the address bus do not extend to the peripheral circuits. Instead, the CPU, toward the peripheral circuit, variable time length of the read signal RD _{_,} write signal WR _{_} is delivered. FIG. 2 is a block diagram showing a detailed configuration of a characteristic part of the embodiment shown in FIG.

The register selection circuit uses the read signal RD._{_} Ah
Rui or light signal WR_{_} The time length of the clock signal C
Measure the LK clock pulse as a unit and
Many registers are provided inside the peripheral circuit according to the length.
Registers accessed from among R1, R2, ..., Rn
Select a select signal (each select
Signal R1SEL, R2SEL, ..., RnSEL
It is a circuit that outputs either). CPU to Lee
Signal RD_{_} Is sent or write signal WR _{_} Sent
The register to which the select signal was sent, depending on
(Any one of registers R1, R2, ..., RN)
Data is read out to the data bus or
The data input via the data bus is written to the
Get caught

FIG. 3 is a circuit diagram showing the internal structure of the register peripheral circuit shown by the block in FIG. The register peripheral circuit shown in FIG. 3 changes the time length of the read signal RD _{_} or the write signal WR _{_} from 1 clock length of the clock signal CLK to 4 clock lengths.
It is a circuit that outputs a register selection signal (any one of the register selection signals R1SEL, R2SEL, R3SEL, and R4SEL) to any one of the register signal lines according to the time length.

4, FIG. 5, FIG. 6, and FIG. 7 show the register selection circuit shown in FIG.
Pulses, 2 pulses, 3 pulses, a timing chart when _{the _} is 4 read signal of the temporal length of the pulse RD is input. Register selection signals R1SEL, R2SEL,
R3SEL, R4SEL is determined at the time of the read signal PD _{_} rise.

As shown in these figures, a register selection circuit shown in FIG. 3, after _{the _} falls read signal RD,
Between until the read signal RD _{_} rises, the clock signal C
It counts up at each rising edge of LK. The clock signal CL is the read signal RD _{_} the time length of the
K of each one pulse, 2 pulses, 3 pulses, depending on whether it is a 4 pulse, at the time of the read signal RD _{_} rise, respectively, each register selection signal R1SEL, R2SEL, R3SEL, R4SEL is' H 'Level, each register R1, R respectively
2, R3 and R4 are selected. Write signal when WR _{_} which is the same also.

Since the register selection circuit shown in FIG. 3 uses a 2-bit counter, the read signal RD.sub _.-- or write signal WR.sub _.-- has four time lengths from 1 clock length to 4 clock lengths. It can only measure, four registers R1, R2, R3, R4 only can not be selected, by increasing the number of bit counter, a longer read signal RD _{_} or write signal temporal length WR until _{_} clock length Can be measured, and a larger number of registers can be selected.

The read signal R having a variable time length as described above.
To generate D _{_} or the write signal WR _{_} , a CPU having a function of executing an instruction to change the temporal length of the read signal RD _{_} and the write signal WR _{_} may be prepared,
As will be described below, the function can be realized without preparing a CPU having such a special function.

FIG. 8 is a block diagram showing another embodiment of the computer system of the present invention. The embodiment shown in FIG. 8 differs from the embodiment shown in FIG. 1 in that an auxiliary peripheral circuit is added. The value of this auxiliary peripheral circuit is written in the internal register R1 by the CPU. Also, this auxiliary peripheral circuit, _{_} read signal RD from the CPU
_Or the sending of the write signal WR _{_} is monitored, and when the read signal RD _{_} or the write signal WR _{_} is sent from the CPU, the CPU waits for the time length corresponding to the value stored in the internal register R1. It sends a signal WAIT _{_.}

The CPU wait signal WAIT_{_} Receive
Until the weight is released,
This is the read signal RD_{_} Or write signal WR_{_} Send out
State). So around such an auxiliary
By preparing the circuit, the CPU can be
Read signal RD using CPU and variable time length
_{_} , Write signal WR_{_} Can be generated.

[0023] Thus, in the above embodiments, the access target register from the internal register of the peripheral circuit is selected by the read signal RD _{_} to write signal WR _{_} temporal length, thus the address of the peripheral circuit A large number of internal registers can be arranged in the peripheral circuit without expanding the space. The present invention can be applied not only when accessing a register provided in a peripheral circuit, but also when accessing an I / O port when the peripheral circuit has an I / O port. You can

[0024]

As described above, the computer system of the present invention selects an area to be accessed from a plurality of areas accessed by the CPU in accordance with the temporal length of the access signal. Therefore, it is possible to reduce the number of address lines connected to the peripheral circuit,
The address space occupied by one peripheral circuit can be reduced. Further, when the CPU and the peripheral circuit are composed of different LSIs, the number of address input terminals of the peripheral circuit LSI can be reduced, so that the peripheral circuit L
It is possible to reduce the cost of SI.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a computer system of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a characteristic part of the embodiment shown in FIG.

3 is a circuit diagram showing an internal configuration of a register selection circuit shown as a block in FIG.

4 is a timing chart when a read signal having a temporal length of one pulse of a clock signal is input to the register selection circuit shown in FIG.

5 is a timing chart when a read signal having a time length of two pulses of a clock signal is input to the register selection circuit shown in FIG.

6 is a timing chart when a read signal having a time length of 3 pulses of a clock signal is input to the register selection circuit shown in FIG.

7 is a timing chart when a read signal having a time length of 4 pulses of a clock signal is input to the register selection circuit shown in FIG.

FIG. 8 is a configuration diagram showing another embodiment of the computer system of the present invention.

FIG. 9 is a diagram showing a connection relationship between peripheral circuits and a CPU.

[Explanation of symbols]

CS _{_} chip select signal RD _{_} read signal WR _{_} write signal R1, R2, ..., Rn register

Claims (3)

[Claims] 1. A CPU comprising: a CPU; and a peripheral circuit having a plurality of areas accessed by the CPU,
Transmitting a variable time length access signal to the peripheral circuit, and the peripheral circuit selecting an area to be accessed according to the temporal length of the access signal. system. 2. The CPU executes an instruction for changing a temporal length of an access signal to send an access signal having a temporal length according to the instruction. The computer system according to item 1. 3. The CP is set when a value is set by the CPU and the CPU sends an access signal.
2. The computer system according to claim 1, further comprising an auxiliary peripheral circuit for sending a wait signal having a time length corresponding to the value to U.