JPH0895936A - Data transfer method between processors - Google Patents

Abstract

(57) [Summary] [Structure] The data transfer method between processors is such that the central processing unit 1 and the main storage unit 2 connected to a common bus are connected to one port of the dual port memory and common to the other port. In a multiprocessor system in which a plurality of single chip microcomputers connected to a bus are connected, a control register 60, a status register 61, a priority order determination circuit 62, and a bus right control circuit 63 are provided between the dual port memory and the single chip microcomputer. The input / output control circuit 6 is set. [Effect] It is possible to solve the problems of the conventional system, such as the decrease in the processing speed of the central processing unit and the single chip microcomputer, and the decrease in the reliability of the transfer data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system in a multiprocessor system in which a central processing unit accesses a plurality of single chip microcomputers connected to a bus different from the bus to which the central processing unit is connected. .

[0002]

2. Description of the Related Art A conventional method is shown in FIGS. Figure 3
Is a central processing unit 1, a main memory unit 2, and a plurality of single-chip microcomputers 9 each having a built-in memory having two small-capacity ports (hereinafter referred to as dual port memory).
4 is a multiprocessor system connected to the No. 4. In this system, the central processing unit 1 transfers the data read from the main storage device 2 to a small capacity dual port memory built in the single chip microcomputer 9, but the dual port memory built in the single chip microcomputer 9 has a small capacity. Since the size is small, if the data to be transferred to the single-chip microcomputer containing the small-capacity dual port memory exceeds the capacity, it is necessary to transfer the data in multiple times. Further, since the single-chip microcomputer 9 does not have means for making the central processing unit 1 recognize that the data transfer from the built-in small-capacity dual port memory to the internal storage device has been completed, the central processing unit 1 always operates. Since it is necessary to monitor the state of the small capacity dual port memory built in the single-chip microcomputer 9, the load on the central processing unit 1 increases and the processing speed decreases. FIG. 4 shows a multiprocessor system in which a central processing unit 1, a main storage unit 2 and a plurality of single chip microcomputers 9 are connected to common buses 3 and 4 via a dual port memory 5. In this system, the central processing unit 1 uses the dual port memory 5
Since there is no means for making the single-chip microcomputer 9 recognize that the data has been transferred to the single-chip microcomputer 9, the single-chip microcomputer 9 needs to constantly monitor the state of the dual port memory 5, so that the processing speed of the single-chip microcomputer 9 is Will fall.

[0003]

FIG. 3 shows a conventional technique.
In this method, the central processing unit 1 transfers the data read from the main storage device 2 to a small capacity dual port memory with a built-in single-chip microcomputer 9. Since the port memory has a small capacity, if the data read from the main storage device 2 by the central processing unit 1 exceeds the capacity, it is necessary to transfer the data in plural times, and the single chip microcomputer 9 is built in. Since the central processing unit 1 does not have a means for making the central processing unit 1 recognize that the data transfer from the small capacity dual port memory to the internal storage device has been completed, the central processing unit 1 always has the small capacity of the single chip microcomputer 9. Since it is necessary to monitor the state of the dual port memory of the capacity, the load on the central processing unit 1 increases and the processing speed increases. It was a problem that decreases. Further, in the system shown in FIG. 4, since the central processing unit 1 has no means for making the single-chip microcomputer 9 recognize that the data has been transferred to the dual port memory 5,
Since the single-chip microcomputer 9 needs to constantly monitor the state of the dual port memory 5, there is a problem that the processing speed of the single-chip microcomputer 9 decreases.

[0004]

According to the data transfer method of the present invention, a central processing unit and a main memory connected to a common bus, and a plurality of single chip microcomputers connected to a common bus different from the above-mentioned bus. Between the common bus connecting multiple single-chip microcomputers and one port of the dual port memory, the central processing unit moves from the main memory to the area of the dual port memory. A control register configured by a flag indicating that data has been transferred, and a status register configured by an end flag indicating that the single chip microcomputer has transferred data from the area of the dual port memory to an internal storage device are provided.
The central processor controls the common bus occupancy of the data transferred to the area of the dual port memory to the single-chip microcomputer until the data in the area disappears regardless of the operation of the central processor. , The problem described in the previous section was solved by setting a control circuit having a function of repeatedly transferring data.

[0005]

The operation of the control circuit will be described with reference to FIG. The control register 60 is a register having a bit width equal to or larger than the number of the single chip microcomputers 9.
The central processing unit 1 associates each single chip microcomputer 9 with a specified area of the dual port memory 5 in a one-to-one correspondence. The central processing unit 1 sets “1” in the bit of the control register 60 inside the control circuit 6 when executing the access to the dual port memory 5. The contents of the register set by the central processing unit 1 and the contents of the status register 61, which will be described later, are stored in the priority order determining circuit 6
2, the central processing unit 1 determines which single-chip microcomputer the access request is made to, and when a plurality of access requests occur, which request is given priority. . The bus right control circuit 63 transmits the bus right release request signal 10 to all the single chip microcomputers 9 at the time of initial execution. On the other hand, the single chip microcomputer 9 transmits the bus right release signal 11 to the bus right control circuit 63. After receiving the bus right release signal 11 from all the single chip microcomputers 9, the bus right control circuit 63 negates the bus right release request signal 10 of the single chip microcomputer 9 in response to the access request from the central processing unit 1. As a result, the single chip microcomputer 9 acquires the common bus use right, transfers the data stored in the area of the dual port memory 5 to the internal storage device, and has a bit width equal to or larger than the number of the single chip microcomputers 9. "1" is set to the bit of the status register 61, which is the register of. The bus right control circuit 63 confirms the bit “1” of the status register 61, and then the status register 61
"0" is cleared. In this way, by successively negating the bus right release request signals to the single chip microcomputer 9 corresponding to the specified area of the dual port memory 5 accessed by the central processing unit 1,
Due to the series of operations of causing the internal storage devices of the plurality of single-chip microcomputers 9 to transfer data, the processing speed of the central processing unit 1 and the single-chip microcomputer 9, which are problems in the conventional system, is reduced and the reliability of the transfer data is improved. The problem of the decrease of the is solved.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the internal structure of the control circuit, and FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 2 shows an example in which the data transfer system between processors of the present invention is used for controlling the stepping motor 12. In the control of the stepping motor, an error in the number of input pulses of the motor, that is, an error in the input data of the single-chip microcomputer 9 in this embodiment is the main cause of the reduction in the control accuracy of the stepping motor. In the data transfer method between processors of the present invention, the reliability of the input data of the single-chip microcomputer 9 is improved and the reduction of the processing speed of the central processing unit 1 and the single-chip microcomputer 9 is prevented. The operation of the control circuit will be described with reference to FIG. The control register 60 is a register having a bit width equal to or larger than the number of the single chip microcomputers 9.
The central processing unit 1 associates each single chip microcomputer 9 with a specified area of the dual port memory 5 in a one-to-one correspondence. The central processing unit 1 sets “1” in the bit of the control register 60 inside the control circuit 6 when executing the access to the dual port memory 5. The contents of the register set by the central processing unit 1 and the contents of the status register 61, which will be described later, are stored in the priority order determining circuit 6
2, the central processing unit 1 determines which single-chip microcomputer the access request is made to, and when a plurality of access requests occur, which request is given priority. . The bus right control circuit 63 transmits the bus right release request signal 10 to all the single chip microcomputers 9 at the time of initial execution. On the other hand, the single chip microcomputer 9 transmits the bus right release signal 11 to the bus right control circuit 63. After receiving the bus right release signal 11 from all the single chip microcomputers 9, the bus right control circuit 63 outputs the bus right release request signal 10 of the single chip microcomputer 9 in response to the access request from the central processing unit 1 as described above. Negate. As a result, the single chip microcomputer 9 acquires the common bus use right, transfers the data stored in the area of the dual port memory 5 to the internal storage device, and has a bit width equal to or larger than the number of the single chip microcomputers 9. "1" is set to the bit of the status register 61, which is the register of. The bus right control circuit 63 clears the bit "0" of the status register 61 after confirming the bit "1" of the status register 61. In this way, by successively negating the bus right release request signals to the single chip microcomputers 9 corresponding to the specified area of the dual port memory 5 accessed by the central processing unit 1, the plurality of single chip microcomputers 9 are Causes the internal storage device to transfer data.

[0007]

According to the data transfer system between processors of the present invention, the central processing unit transfers the data transferred to the area divided for each single chip microcomputer of the large capacity dual port memory to the single chip microcomputer.
By controlling the common bus occupancy right, regardless of the operation of the central processing unit, by setting a control circuit having a function of repeatedly transferring data until there is no data in the area, problems with the conventional method The problems of reduced processing speed of the central processing unit and single-chip microcomputer, and reduced reliability of transfer data have been resolved.

[Brief description of drawings]

FIG. 1 is a block diagram of a control circuit unit according to the present invention.

FIG. 2 is a block diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional multiprocessor system.

FIG. 4 is a block diagram of a conventional multiprocessor system.

[Explanation of symbols]

1 ... Central processing unit, 2 ... Main memory unit, 3, 7 ... Address bus, 4, 8 ... Data bus, 5 ... Dual port memory, 6 ... Input / output control circuit, 9a ... Single chip microcomputer, 9b ... Built-in Single-chip microcomputer, 60 ... Control register, 61 ... Status register, 62
... Priority determination circuit, 63 ... Bus right control circuit.

Claims (2)

[Claims] 1. A multiprocessor system comprising a central processing unit, a main storage unit, and a plurality of single-chip microcomputers, the storage elements which are divided into areas for each single-chip microcomputer and which can be accessed bidirectionally, for example, A memory having two ports is provided, one of the ports is connected to a common bus that connects the central processing unit and the main memory, and the other port is connected to a plurality of single-chip microcomputers that are connected to the common bus. Data transfer method between processors characterized by the above. 2. The area of the memory having two ports from the main memory to which the central processing unit is located between the plurality of single-chip microcomputers connected to the common bus and the memory having the two ports according to claim 1. A control register configured by a flag indicating that data has been transferred to the internal storage device, and a status register configured by an end flag indicating that the single chip microcomputer has transferred data to the internal storage device from the memory area having the two ports. , The central processing unit is provided with the number of areas, and the central processing unit controls the exclusive right of the common bus to the single chip microcomputer for the data transferred to the area of the memory having the two ports. Regardless of the operation of the device, data will be repeatedly acquired until there is no more data in the area. Data transfer system between processors, characterized in that setting the control circuit having a feed causes function.