JPH0896587A - Memory control device and memory control method - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a memory control device and a memory control method that can be used until the end of the life of the flash memory without worrying about the number of times the flash memory can be written in advance. . The system includes at least one flash memory, means for detecting a defective block in the flash memory, means for storing position information of the defective block, and means for controlling these means. Furthermore, if a defect diagnosis is performed for any memory block that has been accessed and a defect is detected,
The control unit stores the block number of the memory block in the unit that stores the position information of the defective block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory control device having a limited number of write operations and a memory control method thereof.

[0002]

2. Description of the Related Art Since a flash memory has an advantage that its stored contents are retained even when the power is turned off, demand for it as an external storage device is increasing. However, there is a drawback that the number of times of writing is limited, and there is an example in which reliability is ensured by means of counting the number of times of writing to avoid access errors in advance.

As an example of a conventional technique, Japanese Laid-Open Patent Publication No. 2-27596 discloses a method in which a spare n chips are prepared separately from a chip to be written, and the number of writing times of the chip to be written exceeds a limit value. Describes how to switch to a spare chip.

As another example, Japanese Patent Laid-Open No. 6-36579 discloses that one chip is divided into predetermined address ranges, and when the number of times of writing in a certain section reaches a limit value, the access target after that is reached. Is shown to switch to another partition.

[0005]

The method according to the prior art as described above is a method for forcibly switching the number of times of writing of the flash memory to be accessed by a predetermined limit value set in advance, and therefore, depending on the conditions of use. Even if the chip is still usable, there is a problem that it is determined that the chip cannot be used. Further, if the life of the chip is reached before the limit value set in advance is reached, there is a problem that it is not possible to perform control such as switching the chip to be accessed by detecting it.

[0006]

In order to solve the above problems, the present invention stores one or more of the above flash memories, a means for detecting a defective block in the flash memory, and position information of the defective block. Means and means for controlling these means.

Further, when a defective memory block occurs during use of the flash memory, in order to prohibit the use of the memory block thereafter, after accessing an arbitrary memory block, a defect diagnosis of the memory block is performed. If the defective memory block is detected and the defective memory block is detected, the control unit stores the block number of the defective memory block in the unit that stores the position information of the defective block.

[0008]

Since the present invention is a control method for diagnosing a defect of a memory block after accessing an arbitrary memory block, it is necessary to set the number of times of accessing the flash memory to a predetermined write limit number of times of the flash memory. It can be used until the end of the life of the flash memory, and one memory chip can be used to the maximum extent.

Further, the defective block number of the flash memory is separately provided on the RAM as defective block information, and the defective block can be ignored in advance by referring to the information when accessing the flash memory. Even if the bad blocks are scattered in, it can be treated as a continuous memory space.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The example shown in FIG. 1 is an embodiment of the flash memory controller circuit according to the present invention. The flash memories 103 to 106 are divided into n memory blocks in advance, and the access to the memory is performed for each memory block. Further, the memory has a function of outputting a status signal such as success or failure by accessing an arbitrary memory block, and is a memory capable of diagnosing a failure of the memory block.

The defect detection unit 102 is the flash memory 1
The control unit 1 decodes the status output when an arbitrary memory block of 03 to 106 is accessed and determines whether the memory block is a usable block.
Let 00 know. RAM 101 is a flash memory 103-
This is a part for storing the sequential numbers of all the defective blocks scattered in 106 for each chip separately. Further, even when the defect detection unit 102 determines that the memory block is unusable during use, the sequential number of the memory block is additionally stored in the RAM 101. Control unit 10
Reference numeral 0 is a portion that executes writing, reading, and erasing with respect to the flash memories 103 to 106, and controls input / output of information with respect to the defect detection unit 102 and the RAM 101.

The number of flash memories 103 to 106 prepared in this embodiment is arbitrary.

FIG. 2 is an embodiment showing a state in which the sequential numbers of defective blocks are stored in the RAM 101. The flash memories 103 to 106 are, as described above,
The flash memory 103 is divided into a predetermined number of memory blocks, and the first block of the flash memory 103 (triangle mark 2 in the figure).
The memory blocks indicated by 26 are sequentially identified by sequential numbers such as 1, 2, and 3. RAM1
In 01, areas for storing information of defective blocks are divided corresponding to the flash memories 103 to 106, and a memory ID is arranged at the boundary (head) of each division as information for identifying each. .

For example, the first flash memory 10
Memory ID 1 (20
1) is arranged, and the memory ID 2 (206) is arranged at the head of the information area corresponding to the second flash memory 104. Similarly, the third flash memory 10
5 is provided with a memory ID 3 (210), the nth flash memory 106 is provided with a memory IDn (213), and a section corresponding to all flash memories.

After each memory ID, the number of defective blocks 202, 207 in the flash memories 103 to 106,
211 and 214 are stored. For example, if the number of defective blocks 202 of the first flash memory 103 is “3”, the three pieces of storage information 203 to 205 after that are the sequential numbers of the defective blocks existing in the flash memory 103, and each of them is shaded. The memory blocks 218 to 220 indicated by are unusable memory blocks. When there is no defective block like the third flash memory 105, the memory ID3 (21
“0” is stored in the number of defective blocks in the section 0), and stored information (for example, stored information 212) until the next memory ID appears is treated as meaningless information.

Further, if a new defective block occurs in the third flash memory 105,
The sequential number of the defective block is stored in the storage information 212 portion, and 1 is added to the numerical value stored in the defective block number 211. The capacity of the RAM 101 is set to a capacity capable of storing the sequential numbers of all the memory blocks of the prepared flash memories 103 to 106, but the number that can be stored is an arbitrary number, for example, a sequential number of about half of all the memory blocks. It has a capacity that can be stored,
When more defective blocks are generated, the use of the device may be suspended, which can reduce the capacity of the RAM 101.

When accessing the flash memories 103 to 106, by referring to the defective block information stored in the RAM 101, scattered defective blocks can be ignored, and apparently continuous memory space is obtained. Can be treated as. Although not shown, the RAM 101 loses its information when the power is cut off. Therefore, a means for backing up only the RAM 101 with a battery or the like may be provided. In addition, a specific memory block of the flash memory is used as an area dedicated to temporarily saving the information stored in the RAM 101, and R is set every time the power is turned off.
The information of the AM 101 may be saved.

FIG. 3 is an embodiment of a flowchart showing the procedure for accessing the flash memory while referring to the information in the RAM. First, the chip number of the flash memory to be accessed is Acn (301), the memory block number to be accessed is Abn (302), RA
The number of defective blocks with the chip number Acn is read from M101 and set as Fn (303). At this time, if the number of defective blocks is other than 0 (Fn ≠ 0), the following defective block check procedure (305 to 310) is performed, and if the number of defective blocks is 0 (Fn = 0), the flash memory is immediately accessed. (311).

If there is a defective block in the Acn-th chip, the Ac stored in the RAM 101 is stored.
One sequential number of the defective block is read from the nth memory ID area and set as Fbn (30
5) Compare with the block number Abn of the chip currently trying to access (306). If the comparison result is different (Abn ≠ Fbn), 1 is subtracted from the number of defective blocks Fn (309). On the other hand, if the comparison results are in agreement (Abn = Fbn), Abn is a defective block, so the memory block to be accessed is changed to (Abn + 1), and this is newly defined as Abn (307).

At this time, if Abn exceeds the final memory block of the chip Acn to be accessed (30
In 8), the processing so far is interrupted, and error processing such as externally displaying that an error has occurred in memory access is executed (316).

Although not shown, as another error processing, the chip number to be accessed may be changed to another chip number, and the process may be executed again from the beginning of this flowchart. Further, in the present embodiment, the case where all the memory areas of one flash memory become unusable as a trigger for carrying out the error processing, but the number of unusable memory areas may be set to an arbitrary number. Good.

In processing operation 308, if Abn does not exceed the final memory block, the bad block check procedure (305-310) is performed until Fn reaches zero. After it turns out that Abn is not a bad memory block,
The memory block Abn of the flash memory Acn is accessed (311). After that, the status signal output from the flash memory indicating success or failure is analyzed (312 and 313), and if successful, the processing ends.
If the status signal fails, the memory block Ab
When n is determined to be a defective block, Abn is additionally stored in the Acn-th memory ID area on the RAM 101 (314), and 1 is added to the number of the Acn-th defective block to finish (315).

The processing operation for detecting that the memory block has reached the end of its life may be carried out for all the flash memories prepared when the power of the apparatus is turned on. As a result, when accessing a normal flash memory, it is possible to reduce processing operations related to defective memory block detection.

FIG. 4 is an embodiment of a flow chart showing a procedure for detecting defective memory blocks of all flash memories when the power of the apparatus is turned on. First, after the power of the device is turned on (401), the number of chips of the flash memory prepared in the device is Cn (402), and the number of memory blocks of one chip is Bn (403). Next, the memory block Bn of the flash memory Cn is accessed (404), and if the status signal output as a result fails, the memory block Bn is determined to be a defective block, Bn is stored in the RAM 101, and the number of defective blocks is set. 1 is added (405 to 408). Note that the processing operations (404 to 408) of this part are the processing operations shown in FIG.
Since it is the same as (311 to 315), detailed description will be omitted. Thereafter, the processing operations (404 to 408) are executed (409, 410) until the end of one chip (Bn = 0) while sequentially subtracting the number of memory blocks Bn by 1 (409, 410), and further the processing operations so far (403-). All chips of the flash memory prepared for 410) are finished (Cn = 0)
Repeat (411, 412).

[0025]

As described above, the present invention is a control method for diagnosing a defect of a memory block after accessing an arbitrary memory block. The flash memory can be used until it reaches the end of its useful life, and a single memory chip can be utilized to its maximum extent.

Further, the defective block number of the flash memory is separately prepared as a table on the RAM, and the defective block can be ignored in advance by referring to the information when the flash memory is accessed. Even if there are scattered
It can be treated as a continuous memory space.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a circuit configuration of a flash memory control device according to the present invention.

FIG. 2 is an explanatory diagram showing an embodiment showing a state in which a defective block number is stored in a RAM.

FIG. 3 is a flowchart showing an example of a procedure for accessing a flash memory.

FIG. 4 is a flowchart showing an example of a procedure for detecting all defective memory blocks.

[Explanation of symbols]

100 ... Control part, 101 ... RAM, 102 ... Defect detection part, 103 ... First flash memory, 104 ... Second flash memory, 105 ... Third flash memory, 106 ... Nth flash memory .

Claims (2)

[Claims] 1. A control device for performing memory management of a flash memory capable of diagnosing a defect of the memory block by accessing an arbitrary memory block, wherein at least one of the flash memories and a defective block of the flash memory. And a means for storing the position information of the defective block, and a means for controlling these means. 2. When a defect diagnosis of the memory block is performed after an arbitrary memory block is accessed and a defect is detected, the block number of the memory block is stored in a unit that stores the position information of the defective block. , A memory control method characterized by disabling the use of the memory block thereafter.