JPH0897292A - Method of manufacturing MOS transistor and complementary MOS transistor - Google Patents

Abstract

PURPOSE: To unnecessitate an element isolation step using selective oxidation that generates bird's beaks and form activation areas through injection after gate electrodes are formed by injecting second type impurities by using a first resist pattern and gate electrode as a mask and forming a source/drain region. CONSTITUTION: A conductive film is formed in the active region of a semiconductor substrate through an insulation film and the conductive film is etched to form a gate electrode. Next, an impurity of first conductivity type is implanted on the entire surface of the semiconductor substrate including the gate electrode so as to form a first conductivity type well. Then a first resist pattern having an opening is formed on the activation area. While the first resist pattern and gate electrode are used as a mask, an impurity of second conductive type is implanted to form a source/drain region. Further, heat treatment for activation is applied thereto and a wirings 12 are formed in a heavily doped region (source/ drain region) and gate electrodes through well-known contact step and metallization step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method of manufacturing a complementary MOS transistor. More specifically, the present invention can reduce the manufacturing cost by reducing the manufacturing process, and a MOS transistor and a complementary M
The present invention relates to a method for manufacturing an OS transistor.

[0002]

2. Description of the Related Art Complementary M for use with both n-channel and p-channel MOS transistors on one chip
OS (CMOS) transistors are the main technology for VLSI applications. Conventionally, the production of CMOS transistors is
It is manufactured as shown in FIGS. Figure 25 below
36 will be described.

That is, the oxide film 22 and the nitride film 23 are deposited in this order on the surface of the substrate 21. Thereafter, a well forming photoresist pattern 24 is formed on the nitride film 23, and using this as a mask, the nitride film 23 in the N well region is removed and an opening is formed until the oxide film 22 is exposed. Further, with the well forming photoresist pattern 24 as a mask, N
Type impurities (P ⁺ , As ^+, etc.) are implanted (see FIG. 25).

Next, after removing the well forming photoresist pattern 24, selective oxidation is performed to oxidize the N well region to form an oxide film 25 (see FIG. 26). Next, the nitride film 23 is removed, P-type impurity implantation (B ⁺ or the like) is performed in the P well region using the oxide film 25 as a mask, and heat treatment is performed to form a double well (twin well) (FIG. 27).
reference).

Next, the oxide films 22 and 25 on the substrate 21 are removed, and an oxide film 26 and a nitride film 27 are formed on the entire surface in this order. Then, an active region forming photoresist pattern 28 is formed on the nitride film 27, and the oxide film 26 and the nitride film 27 in the element isolation region are removed by anisotropic etching using this as a mask (see FIG. 28). Next, after removing the active region forming photoresist pattern 28, selective oxidation is performed to perform element isolation oxide film (so-called LOCOS oxide film) 2
9 is formed (see FIG. 29).

Next, after removing the oxide film 26 and the nitride film 27, a sacrificial oxide film (oxide film before implantation) 30 is formed. After that, impurity implantation is performed in the active region in order to adjust the thresholds required for the NMOS and PMOS, punch through stopper, and prevent inversion. At this time, at least two photolithography processes are required to separate the active regions of the NMOS and the PMOS (see FIGS. 30 and 31).

Next, the sacrificial oxide film 30 is removed, and the gate oxide film 31 and polysilicon are laminated in this order. Then, a gate electrode forming photoresist pattern 33 is formed on the polysilicon, and the polysilicon is processed using the photoresist pattern 33 as a mask to form the gate electrode 32 (see FIG. 32). Next, implantation is performed to form high-concentration regions 34 (source / drain) required for NMOS and PMOS. At this time, at least two photolithography processes are required to separate the active regions of the NMOS and the PMOS (see FIGS. 33 and 34).

Next, an inter-layer insulating film 35 is formed, and activation heat treatment is further performed (see FIG. 35). Next, a known contact opening and wiring process is performed to form the wiring 36, thereby completing the CMOS transistor (see FIG. 36).

[0009]

According to the method of manufacturing a CMOS transistor described above, nine masks (well formation, active region formation, NMOS threshold implantation, PMOS threshold implantation, gate electrode formation, NMOS high-concentration region implantation, PMOS high-density implantation) are used. For concentration region injection, contact opening, wiring processing) is required. Furthermore, selective oxidation (N well oxidation, LOCOS) is performed twice.
Oxidation) is also required, and the process is very complicated.

Further, since the selective oxidation is used as the element isolation method, an oxide film called bird's beak is bitten during the oxidation, so that the pattern shifts and it is difficult to obtain a desired pattern. On the other hand, JP-A-6
No. 0-130137 reports a method that does not use selective oxidation for element isolation formation. This method is shown in FIGS.
A brief description will be given with reference to No. 9.

First, after forming the oxide film 42 on the substrate 41, boron ions are implanted and the inversion prevention layer 4 is formed on the surface of the substrate 41.
3 is formed (see FIG. 37). Next, photoresist 4
Using the mask 4 as a mask, the oxide film 42 on the active region is removed to expose the substrate 41. After that, gate oxidation is performed to form a gate oxide film 45 (see FIG. 38).

Next, polysilicon is deposited and processed to form a gate electrode 46. Then, threshold value matching injection is performed (see FIG. 39). However, in this method, the inversion prevention implantation is performed on the entire surface, a part of the implanted ions is left in the oxide film 42, and the concentration of the isolation region is increased by diffusing the residual ions in the element isolation region in a subsequent process. . Therefore, it is difficult to control the concentration when the separation region is formed by diffusion. Even when this method is applied to CMOS, N-type inversion prevention implantation, P-type inversion prevention implantation, active region formation, gate electrode formation, NMOS threshold implantation, PMO
Eight masks for S threshold implantation, contact opening, and wiring processing are required, and the process is very complicated.

[0013]

Thus, according to the present invention, a step of forming a conductive film on an active region of a semiconductor substrate via an insulating film, a step of etching the conductive film to form a gate electrode, a first step A step of injecting a conductive type impurity into the entire surface of the semiconductor substrate including the gate electrode to form a first conductive type well, a step of forming a first resist pattern having an opening on an active region, a mask of the first resist pattern and the gate electrode And a step of implanting an impurity of the second conductivity type to form source / drain regions.
A method of manufacturing an S-transistor is provided.

Further, according to the present invention, the formation region of the first conductivity type MOS transistor and the second conductivity type MOS transistor of the semiconductor substrate and the first conductivity type and the second conductivity type MOS.
Forming a conductive film on the formation region of the element isolation region around the formation region of the transistor through an insulating film, etching the conductive film to form a gate electrode of a first conductivity type MOS transistor and a second conductivity type MOS transistor A step of forming on the region, a first region including at least a formation region of an element isolation region around the formation region of the first conductivity type MOS transistor
A step of forming a first resist pattern having an opening on the region, a step of implanting a second conductivity type impurity into the semiconductor substrate using the first resist pattern as a mask, and a step of removing the first resist pattern By forming a second resist pattern having an opening only on the active region and using the second resist pattern and the gate electrode as a mask to implant a first conductivity type impurity to form a source / drain region, a first conductivity type MOS is formed. A step of forming a transistor, a step of forming a third resist pattern having an opening on a second region including at least a formation region of an element isolation region around a formation region of a second conductivity type MOS transistor,
Step of implanting first conductivity type impurities into the semiconductor substrate using the third resist pattern as a mask, and removing the third resist pattern to form a fourth resist pattern having an opening only on the active region of the second conductivity type MOS transistor. And then the 4th
Of the complementary conductivity type MOS transistor, which comprises the step of forming a second conductivity type MOS transistor by implanting a second conductivity type impurity to form a source / drain region using the resist pattern and the gate electrode as a mask. A manufacturing method is provided.

That is, the present invention is characterized in that after forming a desired number of gate electrodes in a desired shape, the active region and the element isolation region are formed by impurity implantation. In the manufacturing method of the present invention, the first conductivity type and the second conductivity type are
It means P-type or N-type. Furthermore, when the first conductivity type is P-type, the second conductivity type is N-type, and when the first conductivity type is N-type, the second conductivity type is P-type. In addition, as impurities giving P-type, boron, indium, etc.
Impurities that give N-type include phosphorus, arsenic, antimony, and the like.

The method of manufacturing the MOS transistor of the present invention will be described below. First, a conductive film is formed over an active region of a semiconductor substrate with an insulating film interposed. As the semiconductor substrate used in the present invention, any semiconductor substrate used in this field can be used, and examples thereof include a silicon substrate. The semiconductor substrate may be preliminarily implanted with P-type or N-type impurities. An insulating film is formed on this semiconductor substrate. The insulating film may be, for example, silicon oxide, silicon nitride, or a laminated film of these having a film thickness of 50 to 150 Å, and the forming method thereof may be a thermal oxidation method, a CVD method or the like. Further, a conductive film to be a gate electrode later is formed over the insulating film. For the conductive film, polysilicon having a film thickness of 500 to 2000 Å or a two-layer structure made of WSi / polysilicon can be used. It is preferable to use WSi / polysilicon because resistance with a wiring layer formed later can be reduced. Further, impurities may be implanted into the polysilicon if necessary.

Next, the conductive film is etched to form a gate electrode. The etching method is not particularly limited,
Dry etching methods such as plasma etching, reactive ion etching, ion beam etching, and sputter etching, or wet etching methods can be used. Since the selective oxide film for element isolation is not formed on the semiconductor substrate, it is flat and does not cause etching residue of the step portion or disconnection of the gate electrode wiring.

Next, impurities of the first conductivity type are applied to the gate electrode.
Implanted on the entire surface of the semiconductor substrate including the first conductivity type well
It The impurity concentration of the well is 5 × 10¹⁶~ 2 x 10¹⁷/ C
m³The depth can be 1 to 2 μm. Change
In addition, the method of implanting impurities is based on the region under the gate electrode and
To obtain the desired impurity concentration profile in the outer region
In addition, it is preferable to use a multi-step method in which impurities are injected multiple times.
Good For example, using polysilicon for the gate electrode
In the case of NMOS, the implantation energy / implantation amount is 20 to 9
0 KeV / 1 x 10¹²~ 4 x 10¹²cm^-2, 60-21
0 KeV / 1 x 10¹²~ 4 x 10¹²cm^-2, 120-3
90 KeV / 1 x 10¹²~ 4 x 10¹²cm ^-2, 200-
360 KeV / 1 x 10¹²~ 4 x 10¹²cm^-2Multistage method
A well can be formed by. Also, well type
It is also possible to inject impurities for threshold adjustment at the same time as
Wear. Impurity injection conditions depend on the impurities used.
Injection energy is 5 to 30 KeV, and injection amount is 1 although it is different.
× 10¹²~ 4 x 10¹²cm^-2It can be.

Next, a first resist pattern having an opening on the active region is formed. Further, by using the first resist pattern and the gate electrode as a mask, second conductivity type impurities are implanted to form source / drain regions. The implantation conditions of the impurities vary depending on the impurities used, but the implantation energy is 40 to 150 KeV and the implantation amount is 1 × 10 ^{15 to} 5 × 1.
It can be set to 0 ¹⁵ cm ^-2 . Then, a MOS transistor can be manufactured by stacking interlayer insulating films by a known method and forming a wiring layer in the gate electrode and the source / drain regions.

Impurities for adjusting the threshold value may be implanted using the first resist pattern and the gate electrode as a mask. Thereby, it is possible to set the concentration to such a level that element isolation is performed at the time of implanting impurities for forming a well. In addition, after forming the source / drain regions, a second resist pattern covering the active region may be further formed, and the second conductive type impurities may be implanted for forming the element isolation region using the second resist pattern as a mask. . The implantation conditions of the impurities may vary depending on the impurities used, but the implantation energy may be 5 to 30 KeV and the implantation amount may be 1 × 10 ^{12 to} 3 × 10 ¹² cm ⁻² .

Next, a method of manufacturing the complementary MOS transistor of the present invention will be described below. First, the first of the semiconductor substrate
Formation regions of conductivity type MOS transistor and second conductivity type MOS transistor, and first conductivity type and second conductivity type MO
A conductive film is formed on the formation region of the element isolation region around the formation region of the S transistor via an insulating film. Further, the conductive film is etched to form a gate electrode on the formation regions of the first conductivity type MOS transistor and the second conductivity type MOS transistor. The method of forming the semiconductor substrate, the insulating film, the conductive film, and the gate electrode in this step is the same as that described in the method of manufacturing the MOS transistor.

Next, a step of forming a first resist pattern having an opening on the first region including at least the formation region of the element isolation region around the formation region of the first conductivity type MOS transistor, the first resist pattern is used as a mask. As a step of injecting a second conductivity type impurity into the semiconductor substrate, removing the first resist pattern, and then forming a second resist pattern having an opening only on the active region of the first conductivity type MOS transistor. A first conductivity type MOS transistor can be formed by implanting first conductivity type impurities and forming source / drain regions using the gate electrode as a mask.

Here, when the first region is a region where the first conductivity type MOS transistor and the element isolation region around it are formed (referred to as a first method), the second conductivity type impurity is implanted under the gate electrode. It is preferable to use a multi-step method in which the impurities are implanted a plurality of times in order to obtain a desired impurity concentration profile in the region 1 and the other formation regions. For example,
In the case of NMOS using polysilicon for the gate electrode,
Injection energy / injection amount is 20 to 90 KeV / 1 × 1
0 ¹² to 4 × 10 ¹² cm ^-2 , 60 to 210 KeV / 1 × 1
0 ¹² to 4 × 10 ¹² cm ^-2 , 120 to 390 KeV / 1 ×
10 ¹² to 4 × 10 ¹² cm ^-2 , 200 to 360 KeV / 1
The second-conductivity-type well can be formed by a multistage method of × 10 ¹² to 4 × 10 ¹² cm ^-2 . Further, it is possible to inject impurities for adjusting the threshold value at the same time when the well is formed.
The implantation conditions of the impurities vary depending on the impurities used, but the implantation energy is 5 to 30 KeV and the implantation amount is 1 × 10.
It can be ¹² to 4 × 10 ¹² cm ^-2 . By this implantation, the second conductivity type well is formed.

After removing the first resist pattern, a first
A second resist pattern having an opening is formed only on the active region of the conductivity type MOS transistor, and the first conductivity type impurity is implanted using the second resist pattern and the gate electrode as a mask to form the source / drain regions. The implantation conditions of impurities differ depending on the impurities used, but the implantation energy is 40 to 150 KeV, the implantation amount is 1 × 10 ^{15 to} 5
It can be set to × 10 ¹⁵ cm ^-2 .

On the other hand, when the first region is the formation region of the element isolation region around the formation region of the first conductivity type MOS transistor (the second method), the implantation condition of the second conductivity type impurity is plural times. It is preferable to use a multi-step method of implanting impurities because the impurity concentration on the surface of the element isolation region can be adjusted with high accuracy. For example, when polysilicon is used for the gate electrode, the implantation energy / implantation amount is 20 to 90 KeV / 1 × 10 ¹² to 4 × 10 ¹² c.
m ⁻² , 60 to 210 KeV / 1 × 10 ¹² to 4 × 10 ¹² c
m ^-2 , 120 to 390 KeV / 1 x 10 ¹² to 4 x 10 ¹²
cm ^-2 , 200 to 360 KeV / 1 x 10 ¹² to 4 x 10
Impurities can be implanted into the element isolation region by the multi-step method of ¹² cm ^-2 .

After removing the first resist pattern, the first
A second resist pattern having an opening is formed only on the active region of the conductivity type MOS transistor. A second conductive type well is formed by using the second resist pattern as a mask, and subsequently, a first conductive type impurity is implanted by using the second resist pattern and the gate electrode as a mask to form source / drain regions. The well forming conditions can be the same as the well forming conditions of the first method. Further, at the same time when the well is formed, an impurity for adjusting the threshold value can be injected in the same manner as the first method. Furthermore, the source / drain region formation conditions can be the same as in the first method.

The above-mentioned first method can be used for a transistor which is required to improve the punch-through breakdown voltage of the source / drain regions. On the other hand, the second method can be used for a transistor that requires a higher concentration in the element isolation region. These methods can be selected according to the required characteristics of the transistor.

Next, the second-conductivity-type MOS transistor is formed, and the forming method can be the same except that the conductivity type of the method of the first-conductivity-type MOS transistor is reversed. After that, an interlayer insulating film is laminated by a known method, and a wiring layer is formed in the gate electrode and the source / drain regions. By the above steps, a complementary MOS transistor composed of NMOS and PMOS can be formed.

MOS transistor of the present invention and complementary M
A desired number of OS transistors can be formed at the same time.

[0030]

According to the method of manufacturing a MOS transistor of the present invention, a step of forming a conductive film on an active region of a semiconductor substrate via an insulating film, a step of etching the conductive film to form a gate electrode, and a first conductivity type A step of injecting impurities into the entire surface of the semiconductor substrate including the gate electrode to form a first conductivity type well, a step of forming a first resist pattern having an opening on an active region, a second step using the first resist pattern and the gate electrode as a mask It is characterized in that it comprises a step of implanting a conductive type impurity to form a source / drain region, so that an activation region is formed by implantation after forming a gate electrode without requiring an element isolation process by selective oxidation that causes bird's beak. It is formed.

Further, after forming the source / drain regions, a second resist pattern covering the active region is formed, and impurities of the first conductivity type are implanted using the second resist pattern as a mask, whereby the element isolation region can be easily formed. Is formed. Furthermore, the number of masks to be used can be reduced by performing the impurity implantation for forming the first conductivity type well at the same time as the impurity implantation for adjusting the threshold value.

Further, by using the first resist pattern as a mask in the impurity implantation for adjusting the threshold value, the number of masks used can be reduced. Furthermore, according to the method of manufacturing the complementary MOS transistor of the present invention,
Conduction is performed on the formation region of the first conductivity type MOS transistor and the second conductivity type MOS transistor of the semiconductor substrate and the formation region of the element isolation region around the formation regions of the first conductivity type and the second conductivity type MOS transistor through an insulating film. A step of forming a film, a step of etching the conductive film to form a gate electrode on a formation region of a first conductivity type MOS transistor and a second conductivity type MOS transistor, an element around the formation region of the first conductivity type MOS transistor Forming a first resist pattern having an opening on a first region including at least an isolation region forming region, implanting a second conductivity type impurity into a semiconductor substrate using the first resist pattern as a mask,
After removing the first resist pattern, a second resist pattern having an opening only on the active region of the first conductivity type MOS transistor is formed, and impurities of the first conductivity type are implanted using the second resist pattern and the gate electrode as a mask. Sauce /
A step of forming a first conductivity type MOS transistor by forming a drain region, a third resist having an opening on a second region including at least a formation region of an element isolation region around a formation region of a second conductivity type MOS transistor A step of forming a pattern, a step of implanting an impurity of the first conductivity type into the semiconductor substrate using the third resist pattern as a mask, a third step
After removing the resist pattern of, a fourth resist pattern having an opening only on the active region of the second conductivity type MOS transistor is formed, and the second conductivity type impurity is implanted using the fourth resist pattern and the gate electrode as a mask. Sauce /
Since it is characterized in that it comprises a step of forming a second conductivity type MOS transistor by forming a drain region, gate electrode formation, NMOS well formation, PMOS well formation, NMOS high concentration region injection, PMOS high concentration region A CMOS is formed with seven masks for implantation, contact region opening, and wiring.

By making the first region and / or the second region a well region for forming the first conductivity type and / or the second conductivity type MOS transistor, the punch-through breakdown voltage of the source / drain region can be improved. An improved CMOS is obtained. Further, the first area and / or the second area are
An element isolation region of a conductivity type and / or a MOS transistor, and further impurity implantation is performed by using the second and / or fourth resist patterns used for forming the source / drain regions as a mask to form a second conductivity type well region. As a result, a transistor that requires a higher concentration in the element isolation region is provided.

[0034]

EXAMPLE A surface channel type NM using the method of the present invention is described below.
A process example of a CMOS transistor including an OS and a buried channel type PMOS will be shown. Note that the conditions used in the text are examples and do not limit the present patent. Example 1 A method for manufacturing a CMOS transistor of the present invention will be described in more detail with reference to FIGS.

First, the entire surface of the silicon substrate 1 is thermally oxidized at 900 ° C. to form the gate oxide film 2 having a film thickness of 100 Å, and the film thickness 60 is formed on the gate oxide film 2 by the LPCVD method.
0Å polysilicon 3 was formed. After that, a gate electrode forming photoresist pattern 4 was formed on the polysilicon 3, and the polysilicon 3 was removed using the same as a mask until the gate oxide film 2 was exposed (see FIG. 1 and FIG. 2 of the plan view).

Next, after removing the photoresist pattern 4, an N-type resist pattern 51 for forming an NMOS well is used.
A P-type well region was opened to form a MOS.
After that, threshold value matching and boron ion (B ⁺ ) implantation for obtaining a concentration profile necessary for forming a P-type well were performed by a multi-step method. The implantation conditions are: implantation energy / implantation amount: 10 KeV / 1.5 × 10 ¹² cm ^-2 , 30 KeV /
1.5 × 10 ¹² cm ^-2 , 70 KeV / 2.0 × 10 ¹² c
m ^-2 , 130 KeV / 2.0 x 10 ¹² cm ^-2 , 210K
It was set to eV / 3.0 × 10 ¹² cm ⁻² . A well having a depth of 1 μm was formed by this implantation (see FIG. 3 and FIG. 4 of the plan view). Next, the resist pattern 51 was removed, and the NMOS active region was opened by the resist pattern 61 for forming the NMOS high concentration region. Then, high concentration region (source / drain region) implantation (As ⁺ ; 50 KeV / 3 × 10 ¹⁵ cm ⁻² ) was performed to form high concentration region 5 (see FIG. 5 and FIG. 6 of the plan view).

Next, the element isolation region of the PMOS is opened by the resist pattern 71 for forming the PMOS well. After that, phosphorus ion (P ⁺ ) implantation for obtaining the concentration profile necessary for forming the N-type well was performed by a multi-step method. The implantation conditions are implantation energy / implantation amount of 60 KeV / 3.
× 10 ¹² cm ^-2 , 100 KeV / 1.0 × 10 ¹² c
m ^-2 , 230 KeV / 2.0 x 10 ¹² cm ^-2 , 400K
eV / 4.0 × 10 ¹² cm ^-2 , 600 KeV / 4.0 ×
It was 10 ¹² cm ^-2 (see FIG. 7 and FIG. 8 of its plan view).

Next, the resist pattern 71 is removed and P
The PMO is formed with the resist pattern 81 for forming the MOS high concentration region.
Phosphorus ion (P ⁺ ) for opening the S active region, adjusting the threshold, and obtaining the concentration profile necessary for forming the N-type well
Injection was performed by a multi-step method. The implantation condition for threshold adjustment is to implant boron ions at 30 KeV / 3 × 10 ¹² cm ^-2 , and the implantation condition for N-type well formation is implantation energy / implantation amount of 100 KeV / 1. 0x
10 ¹² cm ^-2 , 230 KeV / 2.0 x 10 ¹² cm ^-2 ,
400 KeV / 4.0 × 10 ¹² cm ^-2 , 600 KeV /
It was set to 4.0 × 10 ¹² cm ^-2 . After that, high-concentration region implantation (BF ₂ ⁺ ; 50 KeV / 3 × 10 ¹⁵ cm ⁻² ) was performed to form a high-concentration region 6 (see FIG. 9 and FIG. 10 of the plan view).

Next, after removing the resist pattern 81, an interlayer insulating film 10 (NSG; 4000Å) was deposited on the entire surface (see FIG. 11). Next, under N ₂ atmosphere, 900 ° C.
Then, heat treatment for activation is performed for 10 minutes, and the high-concentration regions 5 and 6 and the gate electrode 3 are formed by the known contact process and metal process.
If wiring 11 is applied to the mask, 7 masks (gate electrode, NM
OS well implantation, PMOS well implantation, NMOS high concentration region formation, PMOS high concentration region formation, contact opening,
As a result, a CMOS transistor (for wiring) without using an oxidation step for element isolation was obtained (see FIG. 12).

The processing time required for each step in Example 1 is shown in Table 1 together with the processing time required for each step of the CMOS transistor by the conventional LOCOS oxidation method.

[0041]

[Table 1]

As is clear from Table 1, the manufacturing method of the present invention can reduce the processing time to about half that of the conventional manufacturing method. Example 2 First, the entire surface of the silicon substrate 1 was thermally oxidized at 900 ° C. to form the gate oxide film 2 having a film thickness of 100 Å, and the polysilicon 3 having a film thickness of 600 Å was formed on the gate oxide film 2 by the LPCVD method. After that, a gate electrode forming photoresist pattern 4 was formed on the polysilicon 3, and the polysilicon 3 was removed using the same as a mask until the gate oxide film 2 was exposed (see FIG. 1 and FIG. 2 of the plan view).

Next, after removing the resist pattern 4,
An element isolation region around the NMOS was opened by a P-type well forming resist pattern 91. Thereafter, boron ion (B ⁺ ) implantation for obtaining a concentration profile necessary for forming a P-type well was performed by a multi-step method. The implantation conditions are: implantation energy / implantation amount: 10 KeV / 4.5 × 10 ¹² c
m ^-2 , 30 KeV / 1.5 x 10 ¹² cm ^-2 , 70 KeV
/2.0×10 ¹² cm ^-2 , 130 KeV / 2.0 × 10
^{It was set to 12} cm ⁻² and 210 KeV / 3.0 × 10 ¹² cm ⁻² (see FIG. 13 and FIG. 14 of its plan view).

Hereinafter, CMOS transistors were formed in the same manner as in FIG. In this second embodiment,
Impurity implantation is performed on the element isolation region separately from the impurity implantation for forming the entire well region. Therefore, Example 1
Although the number of times of injection is increased compared to the above, the amount of wells injected into the element region and the element isolation region can be changed, and the surface concentration of the element region and the element isolation region can be controlled more.

Further, since the threshold value adjustment and the high-concentration region formation are performed using the same mask, the number of masks can be reduced, and gate electrode formation, NMOS threshold value adjustment, NMOS inversion prevention, and PMO are performed.
A CMOS transistor could be formed with seven masks for S inversion prevention, contact opening, and wiring. Next, from FIG.
19, the NMOS transistors of Examples 1 and 2, FIG.
23 to 23 show the concentration profiles of the channel region, the element isolation region, the element isolation region under polysilicon, and the high concentration region of the PMOS transistors of Examples 1 and 2.

In the above embodiment, the PMOS transistor may be formed in the same manner as the NMOS transistor of the first embodiment. In addition, PMOS transistors and N
When forming the high concentration region of the MOS transistor, the gate electrode 3
It is also possible to form a buried channel type MOS transistor by injecting a low concentration impurity below.

Although FIGS. 1 to 14 show a CMOS transistor consisting of one NMOS transistor and one PMOS transistor, a plurality of MOS transistors having the same structure can be present even when a plurality of elements are formed (FIG. 24). reference).

[0048]

According to the method of manufacturing a MOS transistor of the present invention, a step of forming a conductive film on an active region of a semiconductor substrate via an insulating film, a step of etching the conductive film to form a gate electrode, and a first conductivity type -Type impurities are implanted into the entire surface of the semiconductor substrate including the gate electrode to form a first-conductivity-type well, a step of forming a first resist pattern having an opening on an active region, using the first resist pattern and the gate electrode as a mask It is characterized by including the step of implanting the second conductivity type impurity to form the source / drain regions, so that the activation region can be formed by implantation after forming the gate electrode without requiring a complicated element isolation process. . Therefore, the number of oxidation steps required in the LOCOS method can be reduced twice. Further, the number of masks can be reduced because the same mask is used for well formation and threshold adjustment, or threshold adjustment and high-concentration region formation.

Further, according to the method of manufacturing the complementary MOS transistor of the present invention, the formation regions of the first conductivity type MOS transistor and the second conductivity type MOS transistor of the semiconductor substrate and the first conductivity type and the second conductivity type MOS transistor are formed. Forming a conductive film on the formation region of the element isolation region around the formation region of the insulating film through the insulating film, and forming a gate electrode by etching the conductive film to form the first conductivity type MOS transistor and the second conductivity type MOS transistor. Forming on top,
A step of forming a first resist pattern having an opening on a first region including at least a formation region of an element isolation region around a formation region of a first conduction type MOS transistor, and a second conductivity type impurity using the first resist pattern as a mask Injecting into the semiconductor substrate, after removing the first resist pattern,
A second resist pattern having an opening is formed only on the active region of the first conductivity type MOS transistor, and the first conductivity type impurity is implanted using the second resist pattern and the gate electrode as a mask to form source / drain regions. Thereby forming a first conductivity type MOS transistor, and a second step
A step of forming a third resist pattern having an opening on a second region including at least a formation region of an element isolation region around a formation region of a conduction type MOS transistor, and using the third resist pattern as a mask, a semiconductor of the first conduction type impurity is used. In the step of implanting into the substrate, after removing the third resist pattern, a fourth resist pattern having an opening only on the active region of the second conductivity type MOS transistor is formed, and using the fourth resist pattern and the gate electrode as a mask, The method is characterized by including a step of forming a second conductivity type MOS transistor by implanting a second conductivity type impurity to form a source / drain region. Therefore, gate electrode formation, NMOS well formation, PMOS well formation, NMOS High concentration region implantation, PMOS high concentration region implantation, contact region opening, 7 sheets of wiring It can form a CMOS at risk.

Further, since the active region and the element isolation region are determined in the photo process by the above manufacturing method, the margin is determined by the exposure device, and the reproducibility of the process can be easily confirmed. That is, if the inspection after the photo process is sufficiently performed, the same product can be produced with high accuracy.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a manufacturing process of a CMOS transistor of the present invention.

FIG. 2 is a schematic plan view of FIG.

FIG. 3 is a schematic cross-sectional view of the manufacturing process of the CMOS transistor of the present invention.

FIG. 4 is a schematic plan view of FIG.

FIG. 5 is a schematic cross-sectional view of the manufacturing process of the CMOS transistor of the present invention.

FIG. 6 is a schematic plan view of FIG.

FIG. 7 is a schematic cross-sectional view of the manufacturing process of the CMOS transistor of the present invention.

FIG. 8 is a schematic plan view of FIG.

FIG. 9 is a schematic cross-sectional view of the manufacturing process of the CMOS transistor of the present invention.

FIG. 10 is a schematic plan view of FIG.

FIG. 11 is a schematic cross-sectional view of the manufacturing process of the CMOS transistor of the present invention.

FIG. 12 is a schematic cross-sectional view of the manufacturing process of the CMOS transistor of the present invention.

FIG. 13 is a schematic cross-sectional view of the manufacturing process of the CMOS transistor of the present invention.

FIG. 14 is a schematic plan view of FIG.

FIG. 15 is a concentration profile under a channel region on the NMOS transistor side of Examples 1 and 2 of the present invention.

FIG. 16 is a concentration profile under the source / drain regions on the NMOS transistor side of Examples 1 and 2 of the present invention.

FIG. 17 is a concentration profile below an element isolation region on the NMOS transistor side of Example 1 of the present invention.

FIG. 18 is a concentration profile below an element isolation region on the NMOS transistor side of Example 2 of the present invention.

FIG. 19 is a concentration profile under the element isolation region (polysilicon) on the NMOS transistor side according to the second embodiment of the present invention.

FIG. 20 is a concentration profile under the channel region on the PMOS transistor side in Examples 1 and 2 of the present invention.

FIG. 21 is a concentration profile under the source / drain regions on the PMOS transistor side of Examples 1 and 2 of the present invention.

FIG. 22 is a concentration profile below an element isolation region on the PMOS transistor side of Examples 1 and 2 of the present invention.

FIG. 23 is a concentration profile under an element isolation region (polysilicon) on the PMOS transistor side of Examples 1 and 2 of the present invention.

FIG. 24 is a schematic plan view showing a case where a plurality of CMOS transistors of the present invention are arranged.

FIG. 25 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 26 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 27 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 28 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 29 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 30 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 31 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 32 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 33 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 34 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 35 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 36 is a schematic cross-sectional view of the manufacturing process of the conventional CMOS transistor.

FIG. 37 is a schematic cross-sectional view of the manufacturing process of the conventional MOS transistor.

FIG. 38 is a schematic cross-sectional view of the manufacturing process of the conventional MOS transistor.

FIG. 39 is a schematic cross-sectional view of the manufacturing process of the conventional MOS transistor.

[Explanation of symbols]

 1 substrate 2 gate oxide film 3 gate electrode 4 resist pattern 5, 6 high concentration region 7, 10 P well 8, 9 N well 11 interlayer insulating film 12 wiring 51, 61, 71, 81, 91 resist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/336 H01L 29/78 301 Y

Claims (9)

[Claims] 1. A step of forming a conductive film on an active region of a semiconductor substrate with an insulating film interposed therebetween, a step of etching the conductive film to form a gate electrode, and a semiconductor substrate containing a gate electrode of a first conductivity type impurity. A step of forming a first conductivity type well by implanting it on the entire surface, a step of forming a first resist pattern having an opening on an active region, and a step of implanting a second conductivity type impurity using the first resist pattern and the gate electrode as a mask. A method of manufacturing a MOS transistor, comprising a step of forming source / drain regions. 2. A device isolation region is formed by forming a source / drain region, forming a second resist pattern covering the active region, and implanting a first conductivity type impurity using the second resist pattern as a mask. A method of manufacturing a MOS transistor according to claim 1. 3. The method of manufacturing a MOS transistor according to claim 1, wherein the impurity implantation for forming the first conductivity type well is performed at the same time as the impurity implantation for adjusting the threshold value. 4. The method for manufacturing a MOS transistor according to claim 1, wherein the first resist pattern is used as a mask in impurity implantation for threshold adjustment. 5. Insulation is provided on a formation region of a first conductivity type MOS transistor and a second conductivity type MOS transistor of a semiconductor substrate and a formation region of an element isolation region around a formation region of the first conductivity type and second conductivity type MOS transistors. A step of forming a conductive film through the film, etching the conductive film to form a gate electrode of the first conductivity type MOS
Forming on the formation region of the transistor and the second conductivity type MOS transistor, a first resist pattern having an opening on the first region including at least the formation region of the element isolation region around the formation region of the first conductivity type MOS transistor A step of forming the second resist pattern, a step of implanting a second conductive type impurity into the semiconductor substrate using the first resist pattern as a mask, and a step of removing the first resist pattern,
A second resist pattern having an opening is formed only on the active region of the first conductivity type MOS transistor, and the first conductivity type impurity is implanted using the second resist pattern and the gate electrode as a mask to form source / drain regions. Thereby forming the first conductivity type MOS transistor, and forming the third resist pattern having an opening on the second region including at least the formation region of the element isolation region around the formation region of the second conductivity type MOS transistor. A step of implanting a first conductivity type impurity into the semiconductor substrate using the third resist pattern as a mask, and a fourth resist pattern having an opening only on the active region of the second conductivity type MOS transistor after removing the third resist pattern. Then, using the fourth resist pattern and the gate electrode as a mask, impurities of the second conductivity type are implanted to form a saw. A method of manufacturing a complementary MOS transistor, which comprises the step of forming a second conductivity type MOS transistor by forming a drain / drain region. 6. The method of manufacturing a complementary MOS transistor according to claim 5, wherein the first region is a well region for forming a first conductivity type MOS transistor. 7. The method of manufacturing a complementary MOS transistor according to claim 6, wherein the second region is a well region for forming a second conductivity type MOS transistor. 8. The first region is an element isolation region of the first conductivity type MOS transistor, and further impurity implantation is performed by using the second resist pattern used for forming the source / drain regions as a mask. The method of manufacturing a complementary MOS transistor according to claim 5, wherein a region is formed. 9. The second region is an element isolation region of the second conductivity type MOS transistor, and further impurity implantation is performed by using the fourth resist pattern used for forming the source / drain regions as a mask. 9. The method for manufacturing a complementary MOS transistor according to claim 8, wherein a region is formed.