JPH0897409A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Object] A method for manufacturing a semiconductor integrated circuit device, for example, in manufacturing a complementary semiconductor integrated circuit device in which an n-type transistor and a p-type transistor are separately manufactured, crystal growth is performed in the middle of the manufacturing. In order to simplify the manufacturing process, it is not necessary to do so, and it is not necessary to implant the n-type impurity ions and the p-type impurity ions for separately forming the n-type transistor and the p-type transistor. [Structure] GaAsSb, which is a semiconductor material having a different conductivity type depending on the growth temperature, is grown at a temperature below a critical temperature at which the conductivity type is reversed, that is, below 550 [° C.], and n-G is grown.
aAs _0.5 Sb _0.5 gate layer is formed and n-GaAs
_The p-GaAsSb gate 14P is generated by local heating at a temperature of 550 [° C.] or higher so that the conductivity type of the p-type FET portion in the _0.5 Sb _0.5 gate layer is inverted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an improvement in a method for manufacturing a complementary semiconductor integrated circuit device in which a type transistor and an n-type transistor are manufactured.

It is needless to say that a complementary type is extremely important as a semiconductor integrated circuit device used in electronic equipment, but there are various difficulties in obtaining a complementary type device in an ultrahigh speed device. I have to overcome this.

[0003]

2. Description of the Related Art At present, Si MOSFETs (silicon MOSFETs), which are semiconductor elements widely used, are used.
de semiconductor field ef
A semiconductor device that can operate at a higher speed than that of a semiconductor (Fact Transistor) has been variously studied centering on GaAs which is a compound semiconductor.

All of them utilize the high-speed mobility of electrons, which is a physical characteristic of semiconductor materials as described above, and a typical example thereof is a high electron mobility transistor (high electron mobility).
transistor: HEMT).

The HEMT is, for example, an AlGaAs layer or an GaAs layer which forms a heterojunction interface.
This is a high electron mobility transistor in which an impurity donor is introduced only into a layer, electrons are confined on the GaAs layer side of the heterojunction interface, and electrons and impurities are spatially separated to reduce the influence of impurity scattering.

When integrating HEMT, AlGaAs
An important issue is how to make the impurity concentration and the layer thickness of the layer uniform.

The reason is that the threshold voltage that determines the characteristics of the HEMT depends on the above two conditions. At present, the crystal growth technique having extremely high controllability is used to satisfy the above two conditions, but the implementation thereof involves various difficulties.

Further, a semiconductor device having a structure capable of avoiding the above problems has also been proposed.

FIG. 4 shows an SIS (semiconductor)
r-insulator-semiconductor
(Gate) FET is a cutaway side view of a main part of a semiconductor device called (FET is called “K.
o, et al. "ELECTRONICS LETT
ERS 24th May 1984 Vol. 20N
o. 11 pp. 462-463 ": PM Solo.
mon, et al. "IEEE ELECTRON
DEVICE LETTERS, VOL. EDL-5
NO. 9, SEPTEMBER 1984 "").

In the figure, 1 is an i-GaAs substrate, 2 is an i-AlGaAs gate insulating film, 3 is an n-GaAs gate, 4 is a source contact region, 5 is a drain contact region, 6 is a source, 7 Indicates a drain, and 8 indicates a two-dimensional electron gas layer.

As is apparent from the figure, this semiconductor element has a structure similar to that of a semiconductor gate SiMOSFET, and non-doped AlGaAs is adopted as the material of the gate insulating film instead of an insulator such as SiO ₂ . High concentration GaAs is used as the gate.

The SISFET is exactly the same as the HEMT in that electrons traveling in the channel are released from impurity scattering.

In this semiconductor element, the threshold voltage does not depend on the thickness of the semiconductor layer or the impurity concentration, and the SIS
The combination of materials that make up the structure, that is, in the illustrated example,
Since it is determined by the combination of the i-GaAs substrate 1, the i-AlGaAs gate insulating film 2, and the n-GaAs gate 3, there is an advantage that a large number of devices having uniform threshold voltages can be manufactured.

Attempts have been made to fabricate a complementary circuit using the SISFET described above (see Matsumoto et al., If necessary).

Usually, in a complementary circuit, both conductivity type transistors of an n-type transistor and a p-type transistor are used, so Matsumoto et al. Manufacture it by the regrowth method. That is, after manufacturing an n-type SISFET, a p-type SIS
Crystals for making FETs are growing.

[0016]

As described above, the SI
The SFET is a promising semiconductor device because it can avoid the manufacturing difficulty in the HEMT, but when the complementary circuit forming the core of the integrated circuit semiconductor device is manufactured, the conventional technique described above is used. However, it is not preferable because it is necessary to grow crystals during the circuit fabrication.

The present invention eliminates the need for crystal growth during the manufacture of, for example, a complementary semiconductor integrated circuit device that requires the n-type transistor and the p-type transistor to be manufactured separately. In addition, it is not necessary to implant the n-type impurity ions and the p-type impurity ions for separately forming the p-type transistor and to simplify the manufacturing process.

[0018]

[Means for Solving the Problems] In recent years, GaAs _0.5 Sb
During experiments to grow _0.5 crystals, it was found that the conductivity of the material was reversed from n-type to p-type due to slight differences in growth temperature (if required, "A. Sandhu, e
t al. "ELECTRONICS LETTERS
14th April 1988 Vol. 24 N
o. 8 pp. 451 "").

FIG. 5 is a diagram for explaining the inversion of the conductivity type in a GaAs _0.5 Sb _0.5 crystal, in which the crystal growth temperature is plotted on the horizontal axis and the impurity concentration and carrier mobility are plotted on the vertical axis. There is.

In the figure, is the n-type impurity concentration and is p
The type impurity concentration, electron mobility, and hole mobility, respectively. The impurity in this case is Si.

According to the figure, the crystal growth temperature is 490 [° C.]
It can be seen that the conductivity type inversion occurs between 1 and 520 [° C.]. In the above literature, utilizing this phenomenon, one type of impurity element is used and the temperature is controlled to generate a pn junction.

The present invention is based on the technique of inverting the conductivity type of the semiconductor material due to the difference in the growth temperature and locally inverting the conductivity type.

In order to realize the local inversion of the conductivity type, it is necessary to locally raise the temperature of the semiconductor material. For this purpose, a particle beam such as an electron beam or a laser beam is used.

This heating using a particle beam has been conventionally used for cutting wiring metal and activating impurities after ion implantation, and is known to be a stable technique.

From the above, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, (1) a critical temperature at which the conductivity type of a semiconductor material having a different conductivity type depending on the growth temperature is reversed (for example, 550 [ C.]) and is grown at a temperature of less than one conductivity type semiconductor layer (for example, n-G).
forming a as _0.5 Sb _0.5 gate layer 14),
Next, locally heating at a temperature equal to or higher than the critical temperature so as to invert the conductivity type of a selected region in the one conductivity type semiconductor layer to generate an opposite conductivity type region (for example, p-GaAsSb gate 14P). Is included, or

(2) In the above (1), the semiconductor material having a different conductivity type depending on the growth temperature is GaAsSb, or

(3) In the above (1) or (2),
It is characterized by performing local heating by irradiating an electron beam, or

(4) In the above (1) or (2),
Local heating is performed by irradiating a laser beam, or

(5) i-InG on the semi-insulating InP substrate
aAs layer, i-AlInAs layer and n-GaAs_0.5Sb
_0.5Growing the layers sequentially, and then n-GaA
s_0.5Sb _0.5Pattern layers to form gates
And then n-GaAs_0.5Sb_0.5Or
The gate consisting of
Then, the ion implantation method is applied to the source region.
And forming a drain region, and then a metal electrode.
Process of forming poles / wiring to complete complementary basic gate
It is characterized by including and.

[0030]

By adopting the above means, it is possible to easily form elements having different conductivity types on the same semiconductor substrate,
At that time, re-growth of crystals, or p-type impurity ions and n
There is no need to rely on a complicated means such as implantation of type impurity ions, and it is effective, for example, when realizing a complementary semiconductor integrated circuit device using SISFET.

[0031]

EXAMPLE FIG. 1 shows an S manufactured according to an example of the present invention.
It is a principal part cutting side view showing a semiconductor integrated circuit device using ISFET.

In the figure, 11 is a semi-insulating InP substrate,
12 is an i-InGaAs active layer, 12A is an element isolation groove, 13 is an i-AlInAs gate insulating layer, and 14N is n.
N-GaAsSb gate, 14P in FET type FET
Is a p-GaAsSb gate in the p-type FET portion, 1
5N is a source region in the n-type FET portion, and 15P is p
16N is an n-type FET in the source region of the n-type FET
Drain region in the portion, 16P is a drain region in the p-type FET portion, 17N is a source electrode in the n-type FET portion, 17P is a source electrode in the p-type FET portion, and 18N is an n-type FET portion. Drain electrode at 1
Reference numerals 8P denote drain electrodes in the p-type FET portion, respectively.

In the illustrated example, the drain electrode 18N in the n-type FET portion and the drain electrode 18P in the p-type FET portion are connected to form a complementary basic gate.

FIG. 2 and FIG. 3 are side sectional views showing a main part of the semiconductor integrated circuit device in the process steps for explaining the embodiment, which will be described below with reference to these figures.
The same symbols as those used in FIG. 1 represent the same parts or have the same meanings.

See FIG. 2A. 2 (A) -1 Molecular beam epitaxial growth (molecular bee)
The active layer 12, the gate insulating layer 13, and the gate layer 14 are grown on the substrate 11 in lattice matching with the substrate 11 by applying the am epitaxy (MBE) method.

The main data of each of the above parts are illustrated below. Substrate 11 Material: Semi-insulating InP active layer 12 Material: i-InGaAs Thickness: 2000 [Å] Gate insulating layer 13 Material: i-AlInAs Thickness: 300 [Å] Gate layer 14 Material: n- GaAs _0.5 Sb _0.5 Impurity: Si Impurity concentration: 5 × 10 ¹⁸ [cm ⁻³ ] Thickness: 3000 [Å]

Here, the growth temperature of the n-GaAs _0.5 Sb _0.5 gate layer 14 is set to a temperature below the critical temperature at which conductivity type inversion occurs, that is, 500 [° C.] to 480 [° C.].

See FIG. 2B. 2 (B) -1 Reactive ion etching using a resist process and an etching gas of CCl ₂ F _{2 in the} lithography technique:
By applying the RIE method, n-GaAs _0.5 S
b _0.5 gate layer 14 is patterned to form an n-type FET
A gate 14N in the portion and a gate 14P in the p-type FET portion are formed. At this stage, the gate 14P is not converted to the p-type.

The gate 14P in the 2 (B) -2 p-type FET portion is irradiated with a particle beam such as an electron beam or a laser beam, and the temperature of that portion is a temperature above the critical temperature at which conductivity type inversion occurs, for example. It is heated to 550 [° C.] and inverted from n-type to p-type.

Whether an electron beam is used as the particle beam or a laser beam is used,
Power of about 0.1 [W / μm] per beam diameter, beam diameter of 5 [μm] to 50 [μm], scanning speed of 20 [cm]
/ Sec], and the back surface of the substrate is cooled to about 50 ° C. during scanning. The beam is a CW (continuous
ave) or pulse may be used.

See FIG. 3A. 3 (A) -1 Resist process in lithography technology, and
Wet using etchant as a hydrofluoric acid etchant
By applying the etching method, i-AlInAs
The gate insulating layer 13 is patterned so as to correspond to each element.

3 (A) -2 Resist process in lithography technology, and
By applying a wet etching method using a phosphoric acid-based etching solution as an etchant, i-InGaAs
Etching is performed so as to reach a part of the InP substrate 11 from the surface of the active layer 12 to form an element isolation groove 12A.

See FIG. 3B. 3 (B) -1 Resist process in lithography technology, and
By applying the ion implantation method, the dose amount is set to 1 × 10 ¹³ [cm ⁻² ] and the ion acceleration energy is set to 100 [keV] in the source region formation planned portion and the drain region formation planned portion of the n-type FET portion. Ions are implanted to form the source region 15N and the drain region 16N.

3 (B) -2 Resist process in lithography technology, and
By applying the ion implantation method, the dose amount is set to 1 × 10 ¹³ [cm ⁻² ] and the ion acceleration energy is set to 100 [keV] in the source region formation planned portion and the drain region formation planned portion of the p-type FET portion. Ions are implanted to form the source region 15P and the drain region 16P. The source region and the drain region are formed by n-type F
Which of the ET portion and the p-type FET portion comes first is arbitrary.

3 (B) -3 By applying the resist process, the vacuum deposition method and the lift-off method in the lithography technique, the n-type FE is applied.
At the T portion, the source electrode 17N made of AuGe / Au
And a drain electrode 18N are formed, and in the p-type FET portion, a source electrode 17P and a drain electrode 18P made of AuZn / Au are formed. The electrodes are formed by n-type F
Which of the ET portion and the p-type FET portion comes first is arbitrary.

3 (B) -4 Thereafter, if necessary, by applying a usual technique, the drain region 16N of the n-type FET portion and the p-type FET are formed.
It suffices to connect the partial drain region 16P and lead out other wiring to form a complementary basic gate.

The present invention is not limited to the above embodiments, and many modifications can be realized by applying ordinary techniques within the scope of the matters described in the claims.

For example, in the step 3 (A) -2,
Although the element isolation trench 12A is formed to insulate each element, this is the same effect even if the insulating region is formed by ion implantation of oxygen so as to reach the InP substrate 11 from the surface.

In the above embodiment, G is used as a semiconductor material whose conductivity type is inverted from n-type to p-type depending on temperature control.
Although aAsSb is used, GaAs or the like may be used (if necessary, "A. Sandhu,
et al. "Material Research
Society Symposium Proceed
ings Vol. 144 p. 215-220, 19
89 "", see especially FIG. 2 and its description).

[0050]

In the method for manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor material having a different conductivity type depending on the growth temperature is grown at a temperature below the critical temperature at which the conductivity type is reversed. A one-conductivity-type semiconductor layer is formed, and locally heated at a temperature equal to or higher than the critical temperature so that the conductivity type of a selected region in the one-conductivity-type semiconductor layer is reversed to generate a counter-conductivity type region.

By adopting the above structure, it is possible to easily form elements having different conductivity types on the same semiconductor substrate, in which case regrowth of crystals or p-type impurity ions and n-type impurities are performed. It is not necessary to rely on complicated means such as ion implantation, and it is effective, for example, when realizing a complementary semiconductor integrated circuit device using SISFET.

[Brief description of drawings]

FIG. 1 is a SISFE manufactured according to an embodiment of the present invention.
FIG. 6 is a side view of a main part of a semiconductor integrated circuit device using T.

FIG. 2 is a side sectional view showing a main part of a semiconductor integrated circuit device in a process main part for explaining one embodiment.

FIG. 3 is a side sectional view showing a main part of a semiconductor integrated circuit device in a process key point for explaining an embodiment.

FIG. 4 is a side sectional view showing a main part of a semiconductor device called SISFET.

FIG. 5 is a diagram for explaining inversion of conductivity type in a GaAs _0.5 Sb _0.5 crystal.

[Explanation of symbols]

11 semi-insulating InP substrate 12 i-InGaAs active layer 12A element isolation groove 13 i-AlInAs gate insulating layer 14N n-GaAsSb gate in n-type FET portion 14P p-GaAsSb gate 15N n in p-type FET portion Source region in the p-type FET portion 15P Source region in the p-type FET portion 16N Drain region in the n-type FET portion 16P Drain region in the p-type FET portion 17N Source electrode in the n-type FET portion 17P p Source electrode 18N for n-type FET portion Drain electrode for n-type FET portion 18P Drain electrode for p-type FET portion

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 21/8238 27/092 27/095 9171-4M H01L 29/80 E

Claims (5)

[Claims] 1. A step of growing a semiconductor material having a different conductivity type depending on a growth temperature at a temperature lower than a critical temperature at which the conductivity type is reversed to form a semiconductor layer of one conductivity type, and then forming the semiconductor layer of one conductivity type. Integrated circuit, comprising locally heating at a temperature equal to or higher than a critical temperature to generate an opposite conductivity type region so that the conductivity type of a selected region in the type semiconductor layer is inverted. Device manufacturing method. 2. The semiconductor material having a different conductivity type depending on the growth temperature is GaAsSb.
A method for manufacturing the semiconductor integrated circuit device described. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the local heating is performed by irradiating an electron beam. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the local heating is performed by irradiating a laser beam. 5. i-InGaAs on a semi-insulating InP substrate
A layer, an i-AlInAs layer, and an n-GaAs _0.5 Sb _0.5 layer are grown in this order, a step of patterning the n-GaAs _0.5 Sb _0.5 layer to form a gate, and then the n-GaAs _{0.5 layer.} A step of selectively heating the gate made of Sb _0.5 to invert the conductivity type to p-type, a step of forming a source region and a drain region by applying an ion implantation method, and then a metal electrode / wiring And a step of forming the complementary basic gate to complete the semiconductor integrated circuit device.