JPH0897566A - Printed board - Google Patents

Printed board

Info

Publication number
JPH0897566A
JPH0897566A JP6257592A JP25759294A JPH0897566A JP H0897566 A JPH0897566 A JP H0897566A JP 6257592 A JP6257592 A JP 6257592A JP 25759294 A JP25759294 A JP 25759294A JP H0897566 A JPH0897566 A JP H0897566A
Authority
JP
Japan
Prior art keywords
power supply
layer
wiring
gnd
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6257592A
Other languages
Japanese (ja)
Inventor
Hideho Inagawa
秀穂 稲川
Tomoyasu Arakawa
智安 荒川
Toru Otaki
徹 大滝
Yasushi Takeuchi
靖 竹内
Toru Aisaka
徹 逢坂
Yoshimi Terayama
芳実 寺山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP6257592A priority Critical patent/JPH0897566A/en
Publication of JPH0897566A publication Critical patent/JPH0897566A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

(57)【要約】 【目的】 基板各部の電源/GND配線のインダクタン
スが低くかつ均一で、信頼性の高いプリント基板を提供
する。 【構成】 各層の電源/GND配線5をほぼ同一ピッチ
の平行線パターンに形成するとともに、その平行線パタ
ーンの向きを層ごとに直角にずらせて井桁状に組み合わ
せ、その井桁状に組み合わせた各層の電源/GND配線
5どうしを、互いに交差関係にある位置でバイアホール
6を通して接続する。そして各層の電源/GND配線5
およびバイアホール6を避けた状態で信号配線3を設け
る。これにより、基板各部の電源/GND配線5のイン
ダクタンスをほぼ均一とし、しかも各層の電源/GND
配線5どうしの電磁的影響を小さくしてそのインダクタ
ンスの値を低くし得る。
(57) [Summary] [Object] To provide a highly reliable printed circuit board in which the inductance of the power supply / GND wiring of each part of the board is low and uniform. [Structure] The power supply / GND wirings 5 of each layer are formed in parallel line patterns having substantially the same pitch, and the directions of the parallel line patterns are shifted at right angles for each layer to combine them in a checkered pattern. The power supply / GND wirings 5 are connected to each other through the via holes 6 at positions where they cross each other. And the power supply / GND wiring 5 of each layer
The signal wiring 3 is provided while avoiding the via hole 6. As a result, the inductance of the power supply / GND wiring 5 of each part of the substrate is made substantially uniform, and the power supply / GND of each layer is
The electromagnetic effect between the wirings 5 can be reduced to reduce the value of the inductance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、搭載電子部品に接続す
る信号配線と、電源及び/又はGND配線とを多層に設
けて成るプリント基板の配線構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a printed circuit board in which signal wirings connected to mounted electronic parts and power supply and / or GND wirings are provided in multiple layers.

【0002】[0002]

【従来の技術】従来より、プリント基板における配線を
設計する場合、電源/GND配線よりも信号配線を優先
させる傾向にあり、例えば、2層(両面)基板では、各
層の空いているスペースに電源/GND配線をベタに設
け、また3層以上の多層基板では、内部に電源層とGN
D層とを設けるようにしていた。
2. Description of the Related Art Conventionally, when designing wiring on a printed circuit board, there is a tendency to give priority to signal wiring over power / GND wiring. For example, in a two-layer (double-sided) board, the power supply is placed in an empty space of each layer. / GND wiring is solidly provided, and in a multi-layer substrate with three or more layers, the power supply layer and the GND are internally provided.
And the D layer.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上述の
ような従来のプリント基板における配線構造では、電源
/GND配線は、信号配線やランドクリアランスによっ
て分断されてしまうことが多い。その結果、基板各部の
電源/GND配線のインダクタンスが不均一になって、
インダクタンスの高い部分ができ、そこに大きな電流が
流れると電位変動が起こって、強い放射ノイズを発生さ
せることがある。またGND電位が不安定になって、誤
動作の原因にもなる。
However, in the conventional wiring structure of the printed circuit board as described above, the power supply / GND wiring is often divided by the signal wiring and the land clearance. As a result, the inductance of the power supply / GND wiring of each part of the board becomes uneven,
A part with high inductance is created, and when a large current flows through it, potential fluctuation occurs, which may cause strong radiation noise. Further, the GND potential becomes unstable, which causes malfunction.

【0004】本発明は、このような問題を解決するため
に提案されたもので、基板各部の電源/GND配線のイ
ンダクタンスが低くかつ均一で、信頼性の高いプリント
基板を提供することを目的とする。
The present invention has been proposed to solve such a problem, and an object thereof is to provide a highly reliable printed circuit board in which the inductance of the power supply / GND wiring of each part of the board is low and uniform. To do.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係るプリント基板では、各層の電源及び/
又はGND配線を、ほぼ同一ピッチの平行線パターンに
形成するとともに、その平行線パターンの向きを層ごと
に直角にずらせて井桁状に組み合わせ、その井桁状に組
み合わせた各層の電源及び/又はGND配線どうしを、
互いに交差関係にある位置で、バイアホールを通して接
続した。そして、上記各層の電源及び/又はGND配
線、及びバイアホールを避けた状態で、信号配線を設け
るようにした。
In order to achieve the above object, in a printed circuit board according to the present invention, a power source for each layer and / or
Alternatively, the GND wirings are formed in parallel line patterns having substantially the same pitch, the directions of the parallel line patterns are shifted at right angles for each layer and combined in a checkerboard pattern, and the power supply and / or the GND wiring in each layer combined in the checkerboard pattern. Between
Connections were made through via holes at positions that intersect each other. Then, the signal wiring is provided while avoiding the power supply and / or the GND wiring of each layer and the via hole.

【0006】[0006]

【作用】上述のような配線構造としたプリント基板で
は、電源及び/又はGND配線がほぼ均一に設けられる
とともに、各層の電源及び/又はGND配線の平行線パ
ターンが互いに直角に向けられているため、基板各部の
電源及び/又はGND配線のインダクタンスがほぼ均一
となり、しかも各層の電源及び/又はGND配線どうし
の電磁的影響が小さくなるため、そのインダクタンスの
値も低くなる。
In the printed circuit board having the above-mentioned wiring structure, the power supply and / or the GND wiring are provided substantially uniformly, and the parallel line patterns of the power supply and / or the GND wiring of each layer are oriented at right angles to each other. The inductance of the power supply and / or the GND wiring of each part of the substrate is substantially uniform, and the electromagnetic influence between the power supply and / or the GND wiring of each layer is small, so that the inductance value is also low.

【0007】[0007]

【実施例】以下、図面に基づいて本発明の実施例を説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0008】図1は、本発明に係るプリント基板の配線
構造を示す斜視図で、2層(両面)基板での例を示した
ものである。
FIG. 1 is a perspective view showing a wiring structure of a printed board according to the present invention, showing an example of a two-layer (double-sided) board.

【0009】図のように、このプリント基板1は、IC
などの電子部品2を搭載した上層(上面)とその反対側
の下層(下面)とに、電子部品2に接続する信号配線3
と電源/GND配線(電源及び/又はGND配線)5と
を設けたものである。
As shown in the figure, the printed circuit board 1 is an IC
Signal wiring 3 connected to the electronic component 2 on the upper layer (upper surface) on which the electronic component 2 is mounted and the lower layer (lower surface) on the opposite side.
And a power supply / GND wiring (power supply and / or GND wiring) 5.

【0010】上下各層の電源/GND配線5a,5b
は、それぞれ端部を閉じた平行線パターンに形成される
とともに、その平行線パターンの向きが層ごとに直角に
ずらされて井桁状に組み合わされている。即ち、上層の
電源/GND配線5aは、基板1の長手方向に平行な平
行線パターン、下層の電源/GND配線5bは、基板1
の短手方向に平行な平行線パターンとされている。ま
た、それぞれの平行線パターンのピッチPはほぼ同一に
設定され、しかも本実施例では、そのピッチPは、層間
隔D、つまり基板1の厚さとほぼ同一に設定されてい
る。さらに、井桁状に組み合わせた各層の電源/GND
配線5a,5bどうしは、互いに交差関係にある各位置
で、多数のバイアホール6を通して接続されている。こ
れらのバイアホール6は、各層の平行線パターンのピッ
チPがほぼ同一であることから、やはりほぼ同一のピッ
チで並ぶことになる。
Power supply / GND wirings 5a and 5b of upper and lower layers
Are formed in parallel line patterns with their ends closed, and the directions of the parallel line patterns are shifted at right angles for each layer and are combined in a cross beam shape. That is, the power supply / GND wiring 5a in the upper layer is a parallel line pattern parallel to the longitudinal direction of the substrate 1, and the power supply / GND wiring 5b in the lower layer is the substrate 1
It is a parallel line pattern parallel to the lateral direction of. Further, the pitch P of the respective parallel line patterns is set to be substantially the same, and in the present embodiment, the pitch P is set to be substantially the same as the layer interval D, that is, the thickness of the substrate 1. In addition, the power supply / GND of each layer combined in a grid pattern
The wirings 5a and 5b are connected to each other through a large number of via holes 6 at positions where they intersect each other. Since the via holes 6 have substantially the same pitch P of the parallel line pattern of each layer, they are also arranged at substantially the same pitch.

【0011】そして電子部品2および信号配線3は、上
記平行線パターンを成す各層の電源/GND配線5a,
5b、および層間を結ぶバイアホール6を避けた状態で
設けられている。つまり、電子部品2から出た信号配線
3は、上層では、その上層の電源/GND配線5aの平
行線パターンと平行に延ばされ、電源/GND配線5a
を横断する必要がある場合には、上記バイアホール6と
平行に、同じくバイアホール(不図示)を通して一旦下
層に逃がされ、その下層の電源/GND配線5bの平行
線パターンと平行に延ばされてから、適当な位置で再び
バイアホール(不図示)を通して上層に戻される。
The electronic component 2 and the signal wiring 3 are composed of the power source / GND wiring 5a of each layer forming the parallel line pattern,
5b and the via hole 6 connecting the layers are avoided. That is, the signal wiring 3 extending from the electronic component 2 is extended in the upper layer in parallel with the parallel line pattern of the power supply / GND wiring 5a in the upper layer, and the power supply / GND wiring 5a is formed.
When it is necessary to traverse the same, it is allowed to escape to the lower layer through the same via hole (not shown) in parallel with the via hole 6 and extends in parallel with the parallel line pattern of the power supply / GND wiring 5b in the lower layer. After that, it is returned to the upper layer through a via hole (not shown) at an appropriate position.

【0012】上述のような配線構造としたプリント基板
1では、電源/GND配線5がほぼ均一に設けられると
ともに、上下各層の電源/GND配線5a,5bの平行
線パターンが互いに直角に向けられているため、基板各
部の電源/GND配線5のインダクタンスがほぼ均一と
なり、しかも各層の電源/GND配線5a,5bどうし
の電磁的影響が小さくなるため、そのインダクタンスの
値も低くなる。さらに、本実施例のように、各層の平行
線パターンのピッチPが層間隔Dとほぼ同一であれば、
インダクタンスの均一性がより高まる。
In the printed circuit board 1 having the above-mentioned wiring structure, the power supply / GND wirings 5 are provided substantially uniformly, and the parallel line patterns of the power supply / GND wirings 5a and 5b in the upper and lower layers are oriented at right angles to each other. Therefore, the inductance of the power supply / GND wiring 5 in each part of the substrate becomes substantially uniform, and the electromagnetic influence between the power supply / GND wirings 5a and 5b in each layer becomes small, so that the inductance value also becomes low. Further, if the pitch P of the parallel line pattern of each layer is substantially the same as the layer spacing D as in this embodiment,
The uniformity of inductance is further increased.

【0013】このように、基板各部の電源/GND配線
のインダクタンスが低くかつ均一となることにより、電
位変動による放射ノイズの発生や、不安定なGND電位
による誤動作がなくなる。
As described above, since the inductance of the power supply / GND wiring of each part of the substrate is low and uniform, radiation noise due to potential fluctuation and malfunction due to unstable GND potential are eliminated.

【0014】また、多層の電源/GND配線5のうち、
少なくとも1層は基板1の長手方向にのみパターンを配
線することにより、例えば、信号パターンを、第1層で
は基板長手方向に長く、第2層では基板短手方向に長く
配線でき、よって、電源/GND配線5のパターンにぶ
つかるたびにバイアホール6により迂回する必要がなく
なり、効率良く信号パターンを配線することが可能とな
る。
Of the multi-layer power supply / GND wiring 5,
By wiring the pattern in at least one layer only in the longitudinal direction of the substrate 1, for example, the signal pattern can be wired in the longitudinal direction of the substrate in the first layer and in the lateral direction of the substrate in the second layer. Each time it hits the pattern of the / GND wiring 5, it is not necessary to make a detour by the via hole 6, and the signal pattern can be efficiently wired.

【0015】なお、本実施例では2層基板の場合につい
て説明したが、3層以上の多層基板の場合には、各層の
電源/GND配線をほぼ同一ピッチの平行線パターンに
形成するとともに、隣り合う層どうしの平行線パターン
の向きを層ごとに直角にずらせて井桁状に組み合わせ、
その井桁状に組み合わせた各層の電源/GND配線どう
しを、互いに交差関係にある位置で、バイアホールを通
して接続する。そして、その各層の電源/GND配線お
よびバイアホールを避けるようにして、信号配線を設け
ればよい。これにより、基板各部の電源/GND配線の
インダクタンスをほぼ均一にかつ低くすることができ
る。さらに、各層の平行線パターンのピッチを層間隔と
ほぼ同一に設定すれば、インダクタンスの均一性をより
高めることができる。
In the present embodiment, the case of a two-layer board has been described, but in the case of a multi-layer board having three or more layers, the power supply / GND wirings of the respective layers are formed in parallel line patterns of substantially the same pitch and adjacent to each other. The directions of the parallel line patterns of the matching layers are shifted at right angles for each layer and combined in a cross beam pattern,
The power supply / GND wirings of the respective layers combined in the shape of a cross are connected through via holes at positions where they intersect with each other. Then, the signal wiring may be provided so as to avoid the power supply / GND wiring and the via hole in each layer. As a result, the inductance of the power supply / GND wiring of each part of the substrate can be made substantially uniform and low. Further, by setting the pitch of the parallel line pattern of each layer to be substantially the same as the layer interval, the uniformity of inductance can be further improved.

【0016】また、電源/GND配線の配線方向と平行
に配線された層を、必要に応じて他の配線層に接続する
部分を有する信号パターンを設ければ、出力と入力との
部品位置が電源/GND配線の延長線上にない場合にも
バイアホールで切り返す必要がなくなり、よって高密度
なパターン配線が可能となる。さらに、その信号パター
ンを電源/GND配線のパターンと平行に形成すれば、
より高密度なパターン配線ができ、その結果、基板サイ
ズをより小さくし得るとともに、ノイズも低減させるこ
とができる。つまり、ノイズは、信号配線と電源/GN
D配線とのつくるループ面積に比例するため、高密度な
パターン配線によってそのループ面積を小さくすればノ
イズが低減する。
If a signal pattern having a portion for connecting a layer wired in parallel to the wiring direction of the power supply / GND wiring to another wiring layer as needed is provided, the component positions of the output and the input are arranged. Even if it is not on the extension line of the power supply / GND wiring, it is not necessary to cut back with a via hole, and therefore high density pattern wiring is possible. Furthermore, if the signal pattern is formed in parallel with the pattern of the power supply / GND wiring,
Higher density pattern wiring can be made, and as a result, the substrate size can be made smaller and noise can be reduced. In other words, noise is caused by signal wiring and power supply / GN.
Since it is proportional to the loop area formed with the D wiring, noise can be reduced if the loop area is reduced by a high-density pattern wiring.

【0017】[0017]

【発明の効果】以上説明したように、本発明によれば、
基板各部の電源/GND配線のインダクタンスが低くか
つ均一で、それによって放射ノイズの発生や誤動作を防
止し得る、信頼性の高いプリント基板を実現することが
できる。
As described above, according to the present invention,
It is possible to realize a highly reliable printed circuit board in which the inductance of the power supply / GND wiring of each part of the board is low and uniform, thereby preventing generation of radiation noise and malfunction.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例におけるプリント基板の配線構
造を示す斜視図である。
FIG. 1 is a perspective view showing a wiring structure of a printed circuit board according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 プリント基板 2 電子部品 3 信号配線 5(5a,5b) 電源/GND配線 6 バイアホール 1 Printed Circuit Board 2 Electronic Component 3 Signal Wiring 5 (5a, 5b) Power / GND Wiring 6 Via Hole

フロントページの続き (72)発明者 竹内 靖 東京都大田区下丸子3丁目30番2号 キヤ ノン株式会社内 (72)発明者 逢坂 徹 東京都大田区下丸子3丁目30番2号 キヤ ノン株式会社内 (72)発明者 寺山 芳実 東京都大田区下丸子3丁目30番2号 キヤ ノン株式会社内(72) Inventor Yasushi Takeuchi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Toru Osaka, 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Yoshimi Terayama 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 電子部品を搭載し、該搭載電子部品に接
続する信号配線と電源及び/又はGND配線とを多層に
設けて成るプリント基板において、 上記各層の電源及び/又はGND配線を、ほぼ同一ピッ
チの平行線パターンに形成するとともに、該平行線パタ
ーンの向きを層ごとに直角にずらせて井桁状に組み合わ
せ、該井桁状に組み合わせた各層の電源及び/又はGN
D配線どうしを、互いに交差関係にある位置で、バイア
ホールを通して接続し、 該各層の電源及び/又はGND配線、及び前記バイアホ
ールを避けた状態で、上記信号配線を設けたことを特徴
とするプリント基板。
1. A printed circuit board comprising electronic components mounted thereon, and a signal wiring for connecting to the mounted electronic components and a power supply and / or GND wiring provided in multiple layers, wherein the power supply and / or GND wiring of each layer is substantially The power source and / or GN of each layer are formed in parallel line patterns having the same pitch, and the directions of the parallel line patterns are shifted at right angles for each layer, and are combined in a checkerboard pattern.
The D wirings are connected to each other through via holes at positions where they intersect with each other, and the signal wirings are provided while avoiding the power supply and / or GND wirings of the respective layers and the via holes. Printed board.
【請求項2】 前記多層の電源及び/又はGND配線の
うち、少なくとも1層は基板の長手方向にのみパターン
を配線したことを特徴とする請求項1記載のプリント基
板。
2. The printed circuit board according to claim 1, wherein at least one layer of the multi-layered power supply and / or GND wiring is provided with a pattern only in the longitudinal direction of the board.
【請求項3】 前記電源及び/又はGND配線の配線方
向と平行に配線された層を、必要に応じて他の配線層に
接続する部分を有する信号パターンを設けたことを特徴
とする請求項1又は2記載のプリント基板。
3. A signal pattern having a portion for connecting a layer wired in parallel with the wiring direction of the power supply and / or the GND wiring to another wiring layer as required. The printed circuit board according to 1 or 2.
JP6257592A 1994-09-26 1994-09-26 Printed board Pending JPH0897566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6257592A JPH0897566A (en) 1994-09-26 1994-09-26 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6257592A JPH0897566A (en) 1994-09-26 1994-09-26 Printed board

Publications (1)

Publication Number Publication Date
JPH0897566A true JPH0897566A (en) 1996-04-12

Family

ID=17308415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6257592A Pending JPH0897566A (en) 1994-09-26 1994-09-26 Printed board

Country Status (1)

Country Link
JP (1) JPH0897566A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07321429A (en) * 1994-03-31 1995-12-08 Canon Inc Printed wiring board and design method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07321429A (en) * 1994-03-31 1995-12-08 Canon Inc Printed wiring board and design method

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