JPH0897686A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To prevent mis-latching caused by a delay of a clock in an internal circuit or a change point or the like of each of data with a simple configuration when a large amount of data are latched to each DFF synchronously with the clock. CONSTITUTION: When a clock 2 is differentiated by a differentiation circuit 20 to obtain a differentiation pulse, a delay time between an internal circuit 3 and an inverter 4 is used as a differentiation pulse for a prescribed pulse width and the pulse is used for a hold pulse V5. Data 1A-1N are received respectively by D latches 6A-6N and latched for a presence period of the hold pulse V5. Latch outputs V6A-V6N are latched by DFF7A-7N synchronously with the delayed clock pulse V3. Since one differentiation circuit is enough for lots of data, the circuit is realized with a simple configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit which takes in a plurality of input data in synchronization with a clock signal.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit of this kind, it is necessary to fetch many data signals of an internal circuit in a flip-flop in synchronization with a clock signal supplied from the outside and output them in synchronization with the clock signal. . In this case, a clock signal supplied from the outside is often delayed by passing through an internal circuit. Therefore, FIG. 3 shows an example of a circuit that outputs a lot of data in synchronization with the delayed clock signal.

In FIG. 3, since the clock signal CLK2 is delayed by the internal circuit 3, each data DATA1A
.About.1N are supplied to DFFs (D type flip-flops) 7A to 7N through delay circuits 9 to 9N, respectively, and the respective delay data V6A to V6N are latched in synchronization with the delay clock CLK2.

FIG. 4 is a time chart showing the operation of each part of FIG. Since the clock CLK2 has a delay time, each delay circuit 9 is prevented so that the change areas of the input data 1A to 1N do not come within both the setup time and the hold time, which are the data change areas of the DFFs 7A to 7N.
It is designed to be adjusted from A to 9N. In addition, Q8A-Q
Reference numeral 8N indicates each output of the DFFs 7A to 7N.

As another example, there is a circuit having the configuration shown in FIG. 5 disclosed in Japanese Patent Laid-Open No. 2-109414. In this circuit, variable delay circuits 12A to 12N whose delay times are controllable by delay time control signals 11A to 11N are provided for the respective input data 1A to 1N, and switches 13A to 13N are provided.
N, 14A to 14N to switch control signals 10A, 10N
The respective delay circuits 12A to 12N are made to be through or the clock signal is delayed by performing on / off control.

For example, when the setup time of the DFFs 7A-7N cannot be taken, the switch control signals 10A-1
The clock signal 2 is input to the DFF via the delay circuits 12A to 12N by 0N so that the setup time can be taken.

When the DFFs 7A to 7N cannot hold the hold time, the switch control signals 10A to 10N convert the data signals 1A to 1N into the delay circuits 12A to 12N.
Input to the DFF via each so that the hold time can be taken.

[0008]

In the conventional circuit shown in FIG. 3, when there are a large number of input data, each data is input to the DFF through the delay circuit. Therefore, the delay time varies depending on each variation of the delay circuit. There is a problem that is not constant. This problem becomes more remarkable when the delay time is large.
Also, since a delay circuit is required according to the number of data,
Many gates are required and the circuit scale increases.

In the conventional circuit of FIG. 5, since the data signal and the clock signal are applied to the DFF through the variable delay circuit, the delay time of each variable delay circuit can be adjusted even if there are some variations in the layout and the wiring length. Data can be fetched into the DFF by means of this, but since the number of circuits is also proportional to the number of data lines, the number of gates increases, and the control terminals 10A-1
0N and 11A to 11N are required, which is not a good idea.

It is an object of the present invention to provide a semiconductor integrated circuit having a simple structure capable of absorbing variations in layout and wiring length and stably fetching data.

[0011]

According to the present invention, there is provided a semiconductor integrated circuit which takes in a plurality of input data in synchronism with the level transition of a clock signal, the predetermined level being determined from the level transition timing of the clock signal. Hold pulse generating means for generating a hold pulse of a time width, holding means for respectively taking and holding the plurality of input data during the generation period of the hold pulse, and taking in a plurality of holding data respectively held by the holding means A semiconductor integrated circuit including a plurality of flip-flops is obtained.

[0012]

When a hold pulse having a fixed time width is generated from the level transition timing of the clock signal, each data signal is latched and held during this hold pulse, and each latch output is fetched and output to the DFF. It is possible to absorb the delay of the clock signal and take in the data signal in the data change area with a very simple configuration.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform chart of each part showing the operation of the block of FIG. In FIG. 1, the same parts as those in FIGS. 3 and 5 are designated by the same reference numerals.

The data signals 1A to 1N are held while being taken in by the hold pulse V5 in the D type latches 6A to 6N. These holding outputs V6A to V6N are taken into the corresponding DFFs 7A to 7N in synchronization with the pulse V3 and are derived as output data 8A to 8N.

The clock signal 2 is delayed for a predetermined time through the internal circuit 3, and the delayed pulse V3 and the clock signal 2 are input to the differentiating circuit 20. In the differentiating circuit 20, the delay pulse V3 is inverted by the inverter 4 having a delay function, and the delayed inverted output V4 and the clock signal 2 are input to the NAND gate 5. The output of the gate 5 becomes the hold pulse V5.

The rising timing of the clock signal 2 is delayed by the internal circuit 3 for a fixed time and transmitted to the output V3. The NAND gate 5 further generates a hold pulse V5 having a constant pulse width, which has a waveform obtained by performing NAND operation on the delayed inverted signal V4 of the delayed output V3 and the input clock signal 2.

Therefore, in the D type latches 6A to 6N,
At the falling edge of the hold pulse V5 for latching, the data inputs 1A to 1N are taken in and held for a low level of this pulse V5. If this low-level period is set so as to include at least the data change region of the input data clock signals 1A to 1N, the DFF 7 of the next stage
A-7N are synchronized with the pulse V3, and these latches 6A-6
By inputting N, data input 1A to 1N
Each data can be latched at a stable point without change.

[0019]

As described above, according to the present invention, since the hold pulse may be commonly generated for all data signals, the circuit scale does not increase even if the number of data increases. Also, even if the delay time of the internal circuit increases, the gate circuit for delay (inverter 4 with delay function)
Since it is common, there is an effect that the circuit scale does not increase.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a time chart of each part showing the operation of the circuit of FIG.

FIG. 3 is a diagram showing a conventional circuit example.

FIG. 4 is a time chart of each part showing the operation of the circuit of FIG.

FIG. 5 is a diagram showing another conventional circuit example.

[Explanation of symbols]

 1A to 1N Data signal 2 Clock signal 3 Internal circuit 4 Inverter 5 NAND gate 6A to 6N D type latch 7A to 7N DFF 8A to 8N Output data 20 Differentiation circuit

Claims (3)

[Claims] 1. A semiconductor integrated circuit adapted to take in a plurality of input data in synchronization with a level transition of a clock signal, the hold pulse generating a hold pulse of a predetermined time width from the level transition timing of the clock signal. Generating means, holding means for respectively taking in and holding the plurality of input data during the generation of the hold pulse, and a plurality of flip-flops for taking in the plurality of held data respectively held by the holding means. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the hold pulse generating means is a differentiating means for differentiating the clock signal to generate a differential pulse having the predetermined time width. 3. The differentiating means uses a delay circuit for delaying the clock signal for the predetermined time, an inverting circuit for delaying and inverting the output of the delay circuit, the clock signal and the inversion signal for the predetermined time. 3. The semiconductor integrated circuit according to claim 2, further comprising a gate circuit that generates a hold pulse having a width.