JPH0897731A - Interleave method and interleave circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To increase the distribution interval of input data without increasing the circuit scale of the memory. In an interleave method in which two memories 100 and 200 are controlled so that a read operation of one memory and a write operation of the other memory are alternately reversed, a memory in one write mode is controlled. Is
When the input data is sequentially and continuously written in the row direction of the memory cell array and the writing of that row is completed, the same write operation is sequentially performed for the adjacent row, and the memory cell array for the memory in the other read mode. If data is read continuously in the column direction of, and all the data in that column is read, the next column to be read is selected in a non-continuous order according to a predetermined rule, and the selected columns are selected. The same read operation is sequentially performed on the selected columns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave system and an interleave circuit for the purpose of error correction.

[0002]

2. Description of the Related Art As is well known in the art, by adopting an interleave method, the capability of correcting a burst error in an error correction code is improved. In other words, by applying the interleave method, burst errors are dispersed (error concentration is mitigated), and error concentration can be suppressed within the range of the correction capability that the error correction code originally has. .

FIG. 1 shows the structure of an interleave circuit.
2 is a selector, 100 and 200 are memory circuit blocks respectively, and 6 is memory circuit blocks 100 and 200.
Is a controller for fetching parallel data to the controller, 7 is a controller for controlling output data from the memory circuit blocks 100 and 200, and 8 is a selector. The inside of the memory circuit block 100 is a serial / parallel converter 3
The memory circuit block 2 is composed of 1 and m FIFO memories 401 to 40m and an output data selector 51.
00 has the same configuration and includes a serial / parallel converter 32, m FIFO memories 411 to 41m, and an output data selector 52.

The selector 2 sends the input data stream to the memory circuit block 100 side or 200
Switching to send to the side. If the selector 2 is now selecting the memory circuit block 100, this memory circuit block 100 is in the write mode and the other memory circuit block 200 is in the read mode. Then, the selector 8 selects the memory circuit block 200 in the read mode, and the contents of the memory are output. Memory circuit block 1 in write mode
When the specified number of data has been written to 00, the data from the memory circuit block 200 in the read mode is also just read, so the mode of each memory circuit block is reversed and the same operation is repeated.

The operation of the conventional memory circuit block will be described below. When the memory circuit block 100 is in the write mode, the input data from the selector 2 is supplied to the serial / parallel converter 31. The serial / parallel converter 31 converts the supplied data into m pieces of parallel data under the control of the input side controller 6, and the FIFO 40
Writing is performed in m FIFOs from 1 to 40 m. FIG. 2 shows the serial / parallel converter 31 and the F
The connection with the IFO memories 401 to 40m is shown. Thus, m input by the parallel / serial converter 31
Each piece of data is sequentially written into the FIFOs from the FIFO 401 to the FIFO 40m, and such a writing operation is sequentially repeated to write a specified number of data in the memory.

On the other hand, at this time, the memory circuit block 200 is in the read mode, and the output side selector controller 7
First, all the data written in the FIFO 411 is read out under the control of, and after reading all the data written in this FIFO 411, the next FIFO 41
The data of No. 2 is read out, and similarly, the data written in all the FIFOs up to the FIFO 41m are sequentially read out.
The selector 52 performs a switching operation so as to supply the FIFO output thus read to the selector 8. Since the selector 8 selects the output of the memory circuit block on the read mode side, the output of the selector 52 is output from the selector 8 and becomes the output data stream.

FIG. 3 shows a specific configuration of the controllers 6 and 7. Reference numerals 61 and 71 are m-ary counters, and 72 is an n-ary counter. In order to perform the above-described operation, the m-ary counter 61 of the controller 6 performs S / S every m data clocks.
The load signal of the P converter is generated, and this m-bit parallel data is actually transmitted from the FIFO 401 to the FIFO 40m of the FI.
Write in the FO. The controller 7 is composed of an m-ary counter 71 and an n-ary counter 72, and is configured to advance the state of the m-ary counter 71 by detecting that the n-ary counter 72 has read out the entire contents of the FIFO 401, for example. There is. Specifically, n of the n-ary counter 72
For each count output, the clock of the m-ary counter 71 is enabled to advance the state. And
The count output of the m-ary counter 71 is used as a control signal for the output side selectors 51 and 52.

FIG. 4 illustrates a memory access state according to such a conventional interleave method. As shown in the drawing, the writing and reading directions of the memory configured in a two-dimensional matrix in the memory circuit block are sequential in the order of adjacent rows and columns. As a result, as shown in FIG. 5, in the output data stream, one of the input data is replaced and output.

Such an interleave circuit is often used when performing concatenated coding of a block code and a convolutional code. When the convolutional code of the concatenated coded received data stream is Viterbi-decoded, if there is a transmission line error exceeding the correction capability, the Viterbi decoding circuit generates a burst-like error. If the interleaving process is not performed, errors concentrate in one block of the block code concatenated as the outer code, and the error in this block cannot be corrected. However, since the burst-like error can be dispersed by performing the interleave processing, the error dispersed by the block code can be corrected.

Further, this interleave system is often used in a transmission line in which the reception level is lowered by fading, so-called instantaneous C / N is lowered, and errors occur in bursts. Also in this case, by performing the interleaving process, it is possible to prevent the errors exceeding the error correction capability from intensively occurring due to fading, and it is possible to perform the error correction effectively by dispersing the errors.

As described above, the interleaving process is used for the purpose of improving the effect of the error correction process by dispersing the errors generated by burst-like concentration. Is evaluated by.

[0012]

According to the conventional interleave method, as shown in FIGS. 4 and 5, when a memory arranged in a matrix of m rows and n columns is used,
The input data is distributed every n data. Therefore, in order to increase the distribution interval of input data, it is necessary to increase the circuit scale of the memory.

An object of the present invention is to provide an interleaving system and an interleaving circuit in which the distribution interval of input data can be made larger than before without increasing the circuit scale of the memory.

[0014]

According to the first invention, the matrix 2
An interleave method for handling a common input / output data stream by controlling so that the read operation of one memory and the write operation of the other memory are alternately reversed with respect to two sets of memories having a dimensional array of memory cell arrays. In, in one of the write mode memories, input data is sequentially and continuously written in the row direction of the memory cell array, and when the writing of the row is completed, the same write operation is sequentially performed on the adjacent row, For the memory in the other read mode, if data is read sequentially and continuously in the column direction of the memory cell array and all the data in that column is read, a non-sequential order according to a predetermined rule. Select the column to be read next with, and perform the same read operation for the selected column in sequence. Upon completion of the series of operations of the write mode and read mode and were to repeat the same operation by reversing the operation mode of the memories.

According to the second aspect of the present invention, two sets of memories having a two-dimensional matrix storage cell array are controlled so that the read operation of one memory and the write operation of the other memory are alternately reversed. In the interleave method that handles a common input / output data stream, the input data is sequentially and continuously written in the row direction of the memory cell array to the memory in one of the write modes. The row to be read next is selected in a non-continuous order according to the determined rule, the same write operation is sequentially performed on the selected row, and the memory cell array of the other read mode is selected. If you read all the data in the column sequentially and continuously, and read all the data in that column, the same reading will be performed for the next column. Sequentially performed work, Once for each of the memory after a series of operations of the write mode and read mode, and repeats the same operation by reversing the operation mode of the memories.

In the interleave circuit to which the interleave method of the first invention is applied, the read operation of one memory and the write operation of the other memory are performed for two sets of memories having a memory cell array of a matrix two-dimensional array. An interleave circuit that handles a common input / output data stream by controlling them so that they are alternately reversed.For a memory in one write mode, input data is sequentially and continuously written in the row direction of a memory cell array. When the writing of the row is completed, the writing order control means for sequentially performing the same writing operation on the adjacent row and the memory in the other reading mode sequentially and continuously write the data in the column direction of the memory cell array. After reading and reading all the data in that column, the non-sequential order according to a predetermined rule Then, the column to be read is selected next, and the read order control means for sequentially performing the same read operation for the selected column and the series of operations in the write mode and the read mode for each memory are completed. For example, a mode switching control unit that reverses the operation modes of both memories and repeats similar operations is provided.

In the interleave circuit to which the interleave system of the second invention is applied, the read operation of one memory and the write operation of the other memory are performed for two sets of memories having a memory cell array of a matrix two-dimensional array. An interleave circuit that handles a common input / output data stream by controlling them so that they are alternately reversed, and sequentially writes input data in a row direction of a memory cell array to a memory in one write mode, When the writing of the row is finished, the writing order control means for selecting the row to be read next in a non-continuous order according to a predetermined rule and sequentially performing the same writing operation on the selected row. And for the memory in the other read mode, the data is sequentially and continuously read in the column direction of the memory cell array. If all the data in that column has been read, read sequence control means for sequentially performing the same read operation for the adjacent column, and if the series of operations in the write mode and read mode described above for each memory is completed. For example, a mode switching control unit that reverses the operation modes of both memories and repeats similar operations is provided.

In the above-mentioned configurations of the inventions, "a discontinuous order according to a predetermined rule" is an order defined by the set division method or the bit inversion method.

[0019]

In either the write mode or the read mode, the memory is accessed in a non-continuous order according to a predetermined rule, for example, according to the set division method or the bit inversion method, The distribution interval of input data can be made larger than that of the conventional method for the memory of the same circuit scale, and the error correction characteristic is improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

The structure of the target interleave circuit is the same as that of the conventional example at the level expressed in FIG. 1, but the serial / parallel converters 31 and 32 to the FIFO 40 are used.
1 to 40 m and the connections to the FIFOs 411 to 41 m are different. In the memory access in the conventional example, as shown in FIG. 2, reading and writing were performed from the youngest row and column of the interleaved memory. On the other hand, in the present invention, when writing (or reading from) the memory, the memory is accessed as in the conventional case, but when reading from (or writing to) the memory, the order is determined according to a predetermined rule. by. This rule is characterized by using the set division method and the bit inversion method.

FIG. 6 shows an example of the set division method. As in this example, when there is, for example, a set consisting of memories each having a FIFO number of 8, the set is divided into four FIFOs whose minimum Euclidean distance is larger than the minimum Euclidean distance of the original set. Then, the same division is sequentially repeated for the divided set. Then, a read order number is assigned to each FIFO. In the example of FIG. 6, the average number of adjacent sequence numbers is about 3.8 lines, and the minimum number of lines is two lines, which means that the data can be dispersed more than the conventional array in which only one line is always separated. Recognize. Further, FIG. 7 shows an example in which a position number and a sequence number different from those in FIG. 6 are assigned by using the same set division method. In this example, adjacent sequence numbers have about 4.4 lines, and at least 3 lines. The rows are separated and the data can be distributed more than the allocation in FIG.

FIGS. 8A and 8B explain how to define the order rule by the bit inversion method. This method allocates memory line numbers to the FIFOs 401 to 40m in order, obtains a number obtained by reversing the order of arrangement of bits of the memory line number represented by a binary number, and according to this bit inversion number, F
This is a method of determining the order of reading from the IFO. Even when this bit inversion method is used, the adjacent sequence numbers are on average about 3.6 lines apart, and at least 2 lines apart, and even if such an order rule by the bit inversion method is used, only one line is always present. The data can be distributed more than the arrays that are not separated.

FIG. 9 shows a memory access method according to the first embodiment of the present invention when the row or column number of the memory corresponding to the position number is called according to the sequence number of the allocation method of FIG. The interleave circuit of FIG. 1 can be used as a circuit for realizing such a memory access. However, as the input / output circuit, the read order is programmed in advance in order to control the read order from the memory as shown in FIG. The read ROM 70 is accessed by the output of the m-ary counter 71.

In the example of FIGS. 9 and 10 which is the first embodiment, the writing to the memory is performed conventionally, and the reading order is controlled by using the preprogrammed ROM when reading from the memory. As a second embodiment, conversely, the writing order is controlled when writing to the memory, and when reading from the memory, the FIF is changed as in the conventional case.
It is also possible to sequentially read from O1 to FIFOm. Such a memory access method is shown in FIG.
The memory access method as shown in FIG. 11 can be realized only by configuring the serial / parallel conversion units 31 and 32 in the conventional interleave circuit of FIG. 1 as shown in FIG. That is, the serial / parallel converters 31 and 32
Each bit of the parallel output from is connected according to the order of reading from the memory. In this way, the input / output control circuits 6 and 7 can be made different from the conventional ones only by changing the correspondence between each bit of the serial / parallel converter and the connection of the FIFO. Therefore, it is necessary to add the ROM as in the first embodiment. Nor.

[0026]

As described above, according to the present invention, the rules such as the set division method and the bit inversion method are used for the memory access order, so that the input can be performed at a larger interval than before without increasing the circuit scale of the memory. The interleave system and circuit are such that data can be distributed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration of an interleave circuit (common to a conventional device and the present invention).

FIG. 2 is a diagram for explaining a connection between a conventional serial / parallel converter and a FIFO memory.

FIG. 3 is a configuration diagram of a conventional input / output control circuit.

FIG. 4 is a diagram illustrating a configuration of a conventional interleaved memory and an access method thereof.

FIG. 5 is a conceptual diagram of an input / output data stream of a conventional interleave memory.

FIG. 6 is a diagram illustrating an order rule according to a first set division method.

FIG. 7 is a diagram illustrating an order rule according to a second set division method.

8A is a diagram showing a correspondence between a memory row number and a reading order number by the bit inversion method, and FIG. 8B is a diagram explaining an order rule by the bit inversion method.

9A and 9B are conceptual diagrams showing the access method of the interleaved memory in the first embodiment.

FIG. 10 is a diagram illustrating a configuration of an input / output circuit according to the first embodiment.

11A and 11B are conceptual diagrams showing an access method of an interleaved memory in the second embodiment.

FIG. 12 is a diagram for explaining the connection between the serial / parallel converter and the FIFO in the second embodiment.

[Explanation of symbols]

 1 ... Input data stream 2 ... Select 100, 200 ... Memory circuit block 6, 7 ... Controller 8 ... Select 9 ... Output data stream 31, 32 ... Serial / parallel converter 401-40n ... FIFO memory 411-41n ... FIFO memory 51 , 52 ... Output data selector

Claims (8)

[Claims] 1. For two sets of memories having a memory cell array of a matrix two-dimensional array, the read operation of one memory and the write operation of the other memory are controlled so as to be alternately reversed, and a common input is performed. In the interleave method that handles the output data stream, the input data is sequentially and continuously written in the row direction of the memory cell array to the memory in one of the write modes. Write operation is sequentially performed, and for the memory in the other read mode, if data is sequentially read continuously in the column direction of the memory cell array and all the data in that column is read, a predetermined rule is applied. The next column to be read is selected in a non-sequential order, and the same read operation is sequentially performed on the selected column. Once for each of the memory after a series of operations of the write mode and read mode, interleaving scheme and repeating the same operation by reversing the operation mode of the memories. 2. With respect to two sets of memories having a memory cell array of a matrix two-dimensional array, a common input is performed by controlling the read operation of one memory and the write operation of the other memory alternately to be reversed. In the interleave method that handles the output data stream, the input data is sequentially and continuously written to the memory in one of the write modes in the row direction of the memory cell array, and when the writing of the row is completed, a predetermined rule is set. The row to be read next is selected in a non-contiguous sequence according to the above, and the same write operation is sequentially performed on the selected row.For the memory in the other read mode, data is read in the column direction of the memory cell array. If you read all the data in that column sequentially and sequentially, the same read operation is performed sequentially for the next column. Once for each of the memory after a series of operations of the write mode and read mode, interleaving scheme and repeating the same operation by reversing the operation mode of the memories. 3. The interleave method according to claim 1, wherein the discontinuous order according to a predetermined rule is an order defined by a set division method. . 4. The interleave method according to claim 1, wherein the discontinuous order according to a predetermined rule is an order defined by a bit inversion method. . 5. For two sets of memories having a memory cell array of a matrix two-dimensional array, a common input is performed by controlling the read operation of one memory and the write operation of the other memory alternately to be reversed. An interleave circuit that handles an output data stream.For a memory in one write mode, input data is sequentially and continuously written in the row direction of the memory cell array, and when the writing of that row is completed, the next row For the write order control means for sequentially performing the same write operation for the above, and for the memory in the other read mode, if the data is sequentially and continuously read in the column direction of the memory cell array and all the data in the column is read. , Select the column to be read next in a non-sequential order according to a predetermined rule, and perform the same for the selected column. A read order control means for sequentially performing a read operation, and a mode in which the same operation is repeated by reversing the operation modes of both memories when the series of operations of the write mode and the read mode are completed for each memory. An interleave circuit comprising a switching control means. 6. With respect to two sets of memories having a memory cell array of a matrix two-dimensional array, the read operation of one memory and the write operation of the other memory are controlled so as to be alternately reversed, and a common input is performed. An interleave circuit that handles an output data stream.For a memory in one of the write modes, input data is sequentially and continuously written in the row direction of the memory cell array. For the memory in the other read mode, the write order control means for selecting the row to be read next in a non-continuous order according to the rule and sequentially performing the same write operation for the selected row, If data is sequentially and continuously read in the column direction of the memory cell array and all the data in that column is read, the same applies to the adjacent column. A read order control means for sequentially performing a read operation, and a mode in which the same operation is repeated by reversing the operation modes of both memories when the series of operations of the write mode and the read mode are completed for each memory. An interleave circuit comprising a switching control means. 7. The interleave circuit according to claim 5, wherein the discontinuous order according to a predetermined rule is an order defined by a bit inversion method. . 8. The interleave circuit according to claim 5, wherein the discontinuous order according to a predetermined rule is an order defined by a bit inversion method. .