JPH0897802A - FM multiple encoder - Google Patents

Abstract

(57) [Abstract] [Purpose] In bit error rate measurement using FM multiplexed standard signal data, the delay time from the transmission of the measurement signal to the reception of the signal under measurement is automatically detected and synchronized,
Take a measurement. [Structure] FM multiplex standard signal data created by using an FM multiplex encoder and dedicated software is used as a measurement signal and output to an output plug 93, and at the same time, the timing control counter 2 controls the start timing of reading the data. The data is written in the FIFO type shift register 1 to be written. The measurement signal output to the output plug 93 is input as the signal to be measured after the delay time generated in the measurement system has elapsed,
5 is input. The count value set in the timing control counter 2 is automatically changed so that the signal under measurement and the FIFO
When the result of bit comparison with the data read from the mold shift register 1 is 0, the difference between the two is automatically detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bit error rate measurement of an FM multiplex encoder.

[0002]

2. Description of the Related Art Conventionally, in the bit error rate measurement of FM multiplex signals, a pseudo random pattern is used as a measurement signal. A pseudo random pattern generation circuit is prepared on the transmission side and the reception side, and the signal generated by the pseudo random pattern generation circuit on the transmission side is transmitted as a signal for measurement. In addition, the received signal under measurement is read as an initial value into the pseudo random pattern generation circuit on the receiving side, the signal generated by free running the circuit and the received signal are bit-compared, and synchronization is performed when no error occurs. Then, the bit error rate is measured.

[0003]

When the measurement signal is FM multiplex standard signal data, it is possible to measure the bit error rate under a condition closer to the actual one. However, since the FM multiplex standard signal data consists of data of 9792 bytes per frame and is composed of a plurality of frames, the above-mentioned conventional synchronization detection of the reading method is not suitable. In this case, as the synchronization detection method, the method of delaying the internal measurement reference data by the delay time of the measurement system from the transmission of the signal for measurement to the reception of the signal under measurement is suitable. However, there is a problem in that it is not possible to grasp the exact value because it differs depending on the individual measurement system.

The present invention solves the above conventional problems, and an object of the present invention is to provide an excellent FM multiplex encoder capable of measuring a bit error rate under conditions closer to actual FM multiplex broadcasting. is there.

[0005]

In order to achieve the above object, the present invention uses, as a measurement signal, FM multiplex standard signal data created by using an FM multiplex encoder and dedicated software, and at the same time as transmitting the data, the data is recorded. Write to the FIFO shift register of the circuit. By automatically changing the timing of starting the reading of data from the FIFO type shift register, the time from the transmission of the measurement signal to the measurement is changed, and the bit error rate between the read data and the received data becomes 0. Then, the bit error rate is measured by detecting the timing at which the synchronization is achieved.

[0006]

Therefore, according to the present invention, by automatically synchronizing, the FM multiplex standard signal data can be used as the measurement signal, and the bit error rate can be easily measured under the condition closer to the actual FM multiplex broadcasting. it can.

[0007]

1 and 2 show the structure of an embodiment of the present invention. In FIG. 2, FM multiplex standard signal data created by using this FM multiplex encoder and dedicated software is input to the input terminal 91 as a measurement signal in synchronization with a 16 kHz clock input to the input terminal 92. The input terminal 92 is the write pulse input terminal of the FIFO type shift register 1 and the read timing control counter 2
Connected to the clock terminal of. The input terminal 91 is connected to the modulation circuit 9 and the FIFO shift register 1, and the FM multiplex standard signal data is L-MSK modulated by the modulation circuit 9. The output of the modulation circuit 9 is connected to the output connector 93 and is output as a measurement signal. At the same time, the FM multiplex standard signal data is written in the FIFO type shift register 1 at the timing of the clock input to the input terminal 92, and the read timing control counter 2 which can set the count value at any time is the clock. Start counting. The measurement data output to the output plug 93 is demodulated by the device under test, and this demodulated data is input as the measured data to the input plug 9.
5 and the demodulation clock output simultaneously with the demodulation data are input to the input plug 94. Input plug 9
Reference numeral 4 is connected to the clock generation circuit 4, and the clock generation circuit 4 generates a measurement clock synchronized with the demodulation clock. The output terminal of the clock generation circuit 4 is connected to the input terminal of the gate 3 and the clock input terminal of the data number counter 8. The data number counter 8 counts the total number of data to be measured. The output terminal of the timing control counter 2 is connected to the input terminal of the gate 3. When the timing control counter 2 finishes counting the set count value, the gate 3 synchronizes with the measurement clock output from the clock generation circuit 4 connected to the other input terminal of the gate 3 in synchronization with the FIFO type. The data read signal of the shift register 1 is output. The output terminal of the gate 3 is connected to the data read pulse input terminal of the FIFO type shift register 1. The FIFO type shift register 1 outputs data as a reference for measurement in synchronization with the data reading pulse. The data output terminal of the FIFO type shift register 1 is connected to one input terminal of the gate 5, and at the gate 5, a signal to be measured input to the input connector 95 connected to the other input terminal of the gate 5 A comparison is made. The output terminal of the gate 5 is connected to the pulsing circuit 6,
An error pulse is output from the pulsing circuit 6 when the two data input to the gate 5 are different from each other as an error. The output terminal of the pulse conversion circuit 6 is connected to the clock input terminal of the error number counter 7, and the error number counter 7 counts error pulses. When the data number counter 8 finishes counting the preset number of data, the error number counter 7 finishes the counting operation.

FIG. 3 shows an example of the above series of operations. The delay of the measurement system is m, and the count value set in the timing control counter 2 is n. When m> n, the reading of the data of the FIFO type shift register 1 starts before the signal under measurement reaches the input plug 95 of the unit, and as a result of comparing both data with the gate 5, An error pulse is output from 6. If the count value of the error number counter 7 is not 0 when the data number counter 8 finishes counting, the count value of the read timing control counter 2 is automatically set to n = n + 1 and the same operation is repeated. . When m = n, both data compared by the gate 5 are the same, so that no error pulse is generated from the pulsing circuit 6 and the count value of the error number counter 7 becomes zero. When the count value of the error number counter 7 becomes 0, remeasurement is performed without updating the count value set in the timing control counter 2. At this time, if the count value of the error number counter 7 is 0 again, it is determined that the synchronization is established, the set value of the timing control counter 2 is fixed, and the bit error rate is measured.

[0009]

The present invention is clear from the above embodiment,
The FM multiplex standard signal data created using this FM multiplex encoder and dedicated software is used as a measurement signal, and at the same time as transmission, the data is written to the FIFO type shift register of this circuit and the reading of the data of the FIFO type shift register is started. By automatically controlling the timing up to the number of errors, synchronization can be established according to the delay of the measurement system, and the bit error rate can be easily measured under conditions closer to actual FM multiplex broadcasting. Have.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a measurement state of an FM multiplex encoder according to an embodiment of the present invention.

FIG. 2 is a block diagram of an FM multiple encoder according to the same embodiment.

FIG. 3 is a signal waveform diagram in the example.

[Explanation of symbols]

 1 FIFO type shift register 2 Timing control counter 3 Gate 4 Clock generation circuit 5 Gate 6 Pulsing circuit 7 Error number counter 8 Data number counter 9 Modulation circuit 91 FM multiple standard data input terminal 92 16 kHz clock input terminal 93 Measurement signal output connection Plug 94 Demodulation clock input plug 95 95 Measured data input plug

Claims (1)

[Claims] 1. A FIFO type shift register, a data read timing control counter from the FIFO type shift register, a data comparison circuit, a total data number counter, and an error using FM multiplex standard signal data as a measurement signal. An FM multiplex encoder equipped with a circuit that measures the bit error rate by automatically detecting the delay time from the transmission of the measurement signal to the reception of the signal under measurement and synchronizing with the number counter.