JPH089792Y2 - SCSI adapter circuit for host-to-host communication - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a SCSI host adapter circuit for inter-host communication, which enables communication between SCSI host adapters without a target function.

(Prior Art) Conventionally, when performing communication between two host computers via a SCSI bus, it was necessary to give a host adapter connected to each host computer both an initiator function and a target function. .

That is, as shown in FIG. 11, when transmitting data from the host computer 6a to the host computer 6b, the host adapter 5a sends a SEND to the host adapter 5b.
The procedure is such that a command is transmitted (initiator function), the host adapter 5b which receives the command interprets the command, and receives data from the host adapter 5a (target function). The initiator function is a function of issuing a command to the target and receiving the status from the target, and the target function is a function of receiving, interpreting, executing the command from the initiator and returning the status.

(Problems to be solved by the invention) Generally, since the host adapter circuit is configured assuming that it is connected to an input / output device such as a disk device, it has a target function of receiving, interpreting, and executing commands. Often not. In such a case, it has been impossible to perform communication between host computers.

The present invention has been made in view of the above problems of the conventional technology, and an object thereof is to provide a simple configuration that enables communication between host computers even when the SCSI host adapter does not have a target function. To provide a SCSI adapter circuit.

(Means for Solving the Problems) The present invention is a SCSI adapter circuit for host-to-host communication used for communication between SCSI host adapters that do not have a target function, and which is a source host adapter connected to a SCSI bus. A buffer memory for temporarily storing the data sent by the transfer command (SEND) until it is transferred to the destination host adapter, and a transfer command (SEND) sent from the source host adapter. And a command decoding means for receiving and interpreting a reception command (RECEIVE) sent from the destination host adapter, and if the received command is a transfer command (SEND), the data sent from the transmission source is stored in the buffer. If it is a receive command (RECEIVE) stored in the memory, the data to be transmitted according to the receive command is stored in the buffer memory. They determine have been paid, to determine its or transmits the data according to the result, or waits for the arrival of data, and having a command processing unit for executing the processing.

(Operation) The host adapter that is trying to communicate is SEND and RE
By issuing the CEIVE command to the adapter circuit for inter-host communication connected on the same SCSI bus, bidirectional data communication becomes possible.

(Example) Next, the Example of this invention is described with reference to drawings.

(1) Configuration FIG. 1 is a diagram showing the configuration of an embodiment of an inter-host communication adapter circuit of the present invention.

The host-to-host communication adapter circuit 1 includes a buffer memory 4 for temporarily storing data sent from a transmission source,
5 (4 is a data buffer when the host adapter A is the transmission source, and 5 is a data buffer when the host adapter B is the transmission source), and further has a functional block (hardware is software). Command decoding means 2 for receiving and interpreting a command sent thereto and means for realizing a predetermined function constructed by operating in accordance with Command processing means 3 for executing the specified operation.

Actually, these functional blocks are, as shown in FIG. 2, a SCSI bus control unit 10, a DMA control unit 12, a RAM 13, and a CP.
It is realized by executing a predetermined operation with U11.

The SCSI control unit 10 controls the SCSI protocol, and executes the data transmission / reception with the host adapter on the SCSI bus in accordance with the SCSI protocol in response to a command from the CPU 11.

The buffer memory 13 is configured by using semiconductor RAM, and
From the source host adapter connected to the CSI bus, SEND
Upon receiving the command, the data transmitted following this SEND command is temporarily stored. The inside of this buffer memory 13 is divided into two banks, and each bank is assigned to two host adapters for communication, respectively, whereby the buffers 4 and 5 for each host adapter in FIG. 1 are allocated. Substantially realized.

The DMA control unit 12 controls DMA between the SCSI bus and the buffer memory 13 by using the control lines a and b as handshake signals.

(2) Operation Next, referring to FIG. 3, the host-to-host communication adapter circuit 1
The outline of the operation of will be described.

Initialized host adapter circuit (step
20), when selected by the host adapter (step 21), executes the command receiving process (step 22) to receive the command.

If the received command is a SEND command (step
23), confirm that the buffer memory area for storing data is not used (step 24), perform error processing if it is in use (step 33), and start SEND Data processing if it is not in use. Then, the DMA from the SCSI bus to the buffer is executed to store the received data in the buffer (step 25). After this, the status is transmitted to perform status processing, and the bus is released (step 26). At this time, if the RECEIVE command from the destination host adapter is not received, the process is terminated and waits for the RECEIVE command to come. If the RECEIVE command has already been received (step 27), the RESELECT process is performed. (Step
28), the destination host adapter is recombined, the previously stored data is transferred, and then the status is transmitted (steps 30 and 32).

In step 23 above, the received command is RECE
If it is an IVE command, look at the status of the buffer corresponding to the host adapter that issued the data transfer command (step 29), and if data is already stored in that buffer, execute DMA from the buffer to the SCSI bus. It is activated to transfer data (step 30), and then status processing is executed (step 32). If the data is not stored in the buffer, the host adapter is temporarily DISCONNECTed to end the process and wait for the data to be sent from the transmission source (step 31).

 Next, details of each processing in FIG. 3 will be individually described.

Command reception process (Fig. 4) First, the bus phase (Bus phase) is set to message out (Message Out) (step 40), and Identify
The message is received (step 41). After that, the bus phase is set to the command phase (Comm and phase) (step 42), and the command is received (step 4).
3).

Status processing (Fig. 5) First, the bus phase is set to the status phase (step 50) and the status is transmitted (step 5).
1). Next, the bus phase is changed to the message in phase (M
essage In Phase) (step 52), send an end message (step 53) and release the SCSI bus (step 54).

Disconnect processing (Fig. 6) First, the bus phase is changed to the message in phase (Mess
age In phase) (step 60), after sending the Disconnect message (step 61), the SCSI bus is released (step 62).

Reselect Processing (Fig. 7) First, the target host adapter is reselcted (step 7).
0) Next, the bus phase is set to the message-in phase (step 71), and the Identify message is transmitted (step 72).

Error Processing (FIG. 8) First, the bus phase is set to the status phase (step 80) and the error status is transmitted (step 81). Next, the bus phase is set to the message in phase (step 82), the end message is transmitted (step 83), and the SCSI bus is released (step 84).

Send data (SEND DATA) processing (Fig. 9) First, set the bus phase to data out (Data Out), request the data transmission from the initiator of the transmission source (step 90), and DMA from the SCSI bus to the corresponding buffer. Is activated to take in the data (step 91) and determine the end (step 92).

Receive data (RECEIVE DATA) processing (Fig. 10) First, the bus phase is set to the data-in phase (step 100), DMA from the buffer to the SCSI bus is activated (step 101), and the end judgment is made (step 102). ).

(Effect of the Invention) As described above, the present invention realizes an adapter circuit for host-to-host communication having a simple structure having a command decoding function, a command processing function, and a buffer memory, and a host adapter which attempts to perform communication is By issuing a command to this adapter circuit, bidirectional data exchange can be performed. As a result, bidirectional communication is possible between host adapters that do not have the target function.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing the configuration of an adapter circuit for host-to-host communication of the present invention, FIG. 2 is a diagram showing an example of an actual configuration of the adapter circuit for inter-host communication of FIG. 1, and FIG. FIG. 4 is a flowchart showing an outline of a series of operations of the adapter circuit for host-to-host communication, FIG. 4 is a flowchart showing an operation of command reception processing, FIG. 5 is a flowchart showing an operation of status processing, and FIG. FIG. 7 is a flowchart showing the operation of reselection processing, FIG. 8 is a flowchart showing the operation of error processing, FIG. 9 is a flowchart showing the operation of send data processing, and FIG. 10 is a receive operation. FIG. 11 is a flowchart showing the operation of data processing, and FIG. 11 is a diagram showing an example of the configuration of a conventional system for performing inter-host communication. 1 ... Adapter circuit for communication between hosts 2 ... Command decoding means 3 ... Command processing means 4,5 ... Buffer (RAM) 10 ... SCSI bus control section 11 ... CPU 12 ... DMA control section a, b ... Control lines

Claims (1)

[Scope of utility model registration request] 1. A SCSI adapter circuit for host-to-host communication used for communication between SCSI host adapters without a target function, which is transmitted by a transfer command (SEND) from a source host adapter connected to a SCSI bus. Buffer memory (4,5) for temporarily storing incoming data until it is transferred to the destination host adapter, and the transfer command (SEND) and destination sent from the source host adapter A command decoding means (2) for receiving and interpreting a received command (RECEIVE) sent from the host adapter, and if the received command is a transfer command (SEND), the data sent from the sender is stored in the buffer. Memory (4,
5) and if it is a receive command (RECIVE), check whether the data to be sent according to the receive command is stored in the buffer memory (4,5), and send the data according to the result. Command processing means (3) for determining whether to wait for the arrival of data
And a SCSI adapter circuit for inter-host communication.