JPH09101892A - Information processing device and sequencer for exception processing - Google Patents

Abstract

(57) Abstract: An object of the present invention is to downsize a sequencer for exception processing by indirect memory addressing. SOLUTION When an interrupt occurs (S20 =
(YES), the exception processing sequencer starts operating, and executes stack saving of the program state PSR of the interrupted program and stack saving of the program counter PC (S30, S40). Up to here is the same as the conventional one,
Next, the program address of the jump instruction is loaded from the storage device (S50), and the program address of this normal instruction is set in the PC (S60). After that, as the processing by the jump instruction, the address calculation of the exception processing vector (S70) to the PC setting of the exception processing vector (S90) are executed, and the process branches to the exception processing routine (S100).
The exception processing sequencer can be configured with only the instruction group for executing the processing of S30 to S60, and can be downsized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to miniaturization of an exception processing control unit in an information processing device.

[0002]

2. Description of the Related Art Conventionally, an arithmetic function is divided into five stages of IF (instruction reading), ID (instruction decoding), EX (computation), MA (memory access), and WB (write back), and each stage is connected in parallel. Figure 3 by executing
There is known a microprocessor that executes pipeline processing as shown in FIG.

FIG. 4 is a block diagram of such a microprocessor. This type of microprocessor is composed of a decoder 1 and a data path 2. The decoder 1
According to the data on the address bus 4, an instruction is read from a memory (not shown) via the data bus 3 and decoded. Then, the data path 2 is controlled via the control bus 5 according to the result of the decoding. The data path 2 includes an arithmetic unit 2-1 that performs logic, arithmetic, shift arithmetic, etc., a register file 2-2 that stores the arithmetic result, a program counter 2-3 that counts the address of the current program, and an arithmetic unit. Two
-1 or an address unit 2-4 for switching the output from the program counter 2-3 to the address bus 4. The program counter 2-3 is the PC register 2
3-1 and two PSR registers 2-3-2 32b
It has an it register.

Regarding the time correspondence between each stage of the pipeline processing and the block diagram, the program counter 2-3 at the IF stage, the decoder 1 and the register file 2-2 at the ID stage, and the EX stage at the EX stage. The arithmetic unit 2-1 has an address unit 2-4 during the MA stage.
However, in the WB stage, the register files 2-2 are in a relationship of operating respectively.

In such a microprocessor,
When transitioning from the normal state to the exception handling state, (1)
Two processes are performed: saving the interrupted program state and (2) branching to the exception handling routine. The program state of (1) is the state register of the interrupted instruction and the address of the instruction, and the storage device or the internal register of the microprocessor is used as the save destination.

The branch address setting method of (2) is 2
Yes, one is a vector interrupt method in which the exception processing source itself transfers an address to the microprocessor, and the other is a non-vector interrupt method in which branch information is stored in advance in the storage device and fetches it. .

In the vector interrupt method, the exception processing source itself transfers "branch destination address" to the microprocessor and "memory direct addressing", and the branch destination address is stored in a storage device. There are two types of "memory indirect addressing" for transferring an offset value from the stored address or base address of the destination address to the microprocessor ("Computer Architect: Ohmsha").

The flow of the state transition processing to the exception processing state in the memory indirect addressing of the conventional microprocessor is configured as shown in FIG. When an interrupt occurs in the state where a certain program is being executed (S110) (S120 = YES), first,
The stack of the program state PSR of the interrupted program is saved (S130), the stack of the program counter PC is saved (S140), and the offset value for specifying the exception processing vector is loaded from the storage device (S150). ), The address of the exception processing vector is calculated from the offset value and the base address (S160), the exception processing vector is loaded from the storage device based on the address (S170), and the program counter of the exception processing vector is set ( The procedure of branching to the exception handling routine (S190) has been adopted.

This is shown in FIG. 6 as a pipeline flow. In this figure, when an interrupt signal is input at the ID stage 401 during execution of the instruction 400, the exception processing sequencer starts operation (instruction 40).
0 '). Then, first, PS is performed on the first MA stage 402.
The contents of the R register 2-3-2 are saved in the storage device and the second
At the MA stage 403, the contents of the PC register 2-3-1 are saved in the storage device. Then, the third MA stage 404
Then, the offset value from the address of the storage location of the branch destination address value or the base address is loaded from the exception processing source. In the subsequent second EX stage 405, the third MA
When the address value is loaded in the stage 404, the value is loaded into the PC register 2-3-1. When the offset value is loaded in the third MA stage 404, the absolute address value calculated from the base address and the offset value is loaded into the PC register 2-3-1. set. Then, on the subsequent fourth MA stage 406, the PC
The data of the address set in the register 2-3-1 is loaded from the storage device, and the load data is set in the PC register 2-3-1 in the third EX stage 407. In this way, the exception handling routine is started from the instruction 490. The interrupt response at this time is 10 cycles, and in order to control the third EX stage 407, the control unit 400'-
Ninety-eight cycles of 480 would have to be decoded.

[0010]

Thus, the transition to the exception processing state by the conventional memory indirect addressing is as follows.
There is a problem that the control unit becomes large because two kinds of processing of saving the program state and setting the branch destination address are performed by one sequencer.

Therefore, an object of the present invention is to downsize a sequencer for exception processing by memory indirect addressing.

[0012]

The information processing apparatus of the present invention, which has been made to achieve the above object, sets a branch destination address of an exception process by a normal instruction in memory indirect addressing. More specifically, when an exception handling interrupt is made, the normal counter is set after saving the program counter and program state of the program being executed, and the address value or address offset value from the exception handling source is set. Based on this, the normal instruction is executed to set the branch destination address. For this purpose, it is preferable to use an exception processing sequencer in which an instruction for loading a normal instruction that can be used for branch processing and setting it in the program counter is set after the instruction for saving the program state and the program counter. As such normal instructions, jump instructions, program counter relative branch instructions, load instructions, transfer instructions, etc. can be used. Since a jump instruction is originally provided in many information processing apparatuses, it is easy to use it.

According to the present invention, of the two types of processing (1) and (2) necessary for exception processing, "(2) branch to exception processing routine" is executed by a normal instruction such as a jump instruction. Therefore, the number of control items as a sequencer for exception handling is reduced. As a result, according to the present invention, the control unit of the information processing device can be downsized.

[0014]

Next, an embodiment of the present invention will be described. The hardware configuration of the microprocessor may be the same as the conventional one, but the feature is that the state transition sequencer for memory indirect addressing at the time of exception handling transition is configured as follows.

That is, in this embodiment, as shown in FIG. 1, a state in which a certain program is being executed (S1
In 0), if an interrupt occurs (S20 =
YES), the exception processing sequencer starts operating, and first the stack of the program state PSR of the interrupted program is saved (S30). Then, the stack of the program counter PC is saved (S40). Up to this point, it is the same as the conventional one. However, next, the program address of the normal instruction (jump instruction) is loaded from the storage device (S50), and the program address of this normal instruction is sent to the PC.
It is set in the register 2-3-1 (S60). During this period, S30 to S60 are the contents of the exception processing sequencer in the embodiment.

When the program address of the normal instruction is set in this manner, the processing of the normal instruction is started following the processing by the exception processing sequencer. Since the jump instruction is set here, the following address calculation of the exception processing vector (S70) to PC setting of the exception processing vector (S90) is executed as processing by the jump instruction, and the process branches to the exception processing routine (S100). .

This is shown in the flow of the pipeline as shown in FIG. That is, when an interrupt signal is input at the ID stage 601 of the instruction 600, the instruction 600 is broken and the exception processing sequencer to the interrupt state starts to operate (instruction 600 ′). Then, the first MA stage 602 transfers the contents of the PSR register 2-3-2 to the storage device, and the second MA stage 603 transfers the PC register 2-.
3-1 transfers the contents of 3-1 to the storage device, and the third MA stage 6
At 04, the program address of the jump instruction is transferred from the storage device, and at the second EX stage 605, the program address of the jump instruction loaded at the third MA stage 604 is set in the PC register 2-3-1.

As a result, the jump instruction is executed by the instruction 670, the address offset value of the storage area in which the branch destination address of the head program of the exception processing routine is stored is loaded from the exception processing source, and this and the base are loaded. The program address of the exception handling routine is calculated from the address and the program address is stored in the PC register 2-
Set to 3-1. Then, at instruction 680, the exception handling routine is started.

Thus, in this embodiment,
Instruction 600 ': Stack saving of program state,
Instruction 610: save stack of program counter,
Instruction 620: Load program address of jump instruction, Instruction 630: NOP (Non Operation)
on), instruction 640: program address set of jump instruction, instruction 650: NOP, instruction 66
A sequencer for exception processing is built with only 7 instructions of 0: NOP.

By the way, in the prior art exception processing sequencer described with reference to FIGS. 5 and 6, the instruction 40
0 ': program state stack save, instruction 41
0: Program counter stack save, instruction 42
0: load address offset for specifying branch destination address storage location, instruction 430: NOP, instruction 440: address calculation of branch destination address storage location and load of branch destination address based on operation result, instruction 4
50: NOP, instruction 460: set branch destination address, instruction 470: NOP, instruction 480: NOP
9 instructions were required.

As described above, according to the above-described embodiment, the exception processing sequencer based on the memory indirect addressing can be made smaller than the prior art. Although only the example of the information processing apparatus adopting the pipeline processing method has been described in the embodiment, the exception processing sequencer can be downsized by applying the present invention to the information processing apparatus not adopting the pipeline processing method. There is no difference in what you can do. Therefore, it goes without saying that the present invention can be applied to an information processing device that does not adopt these pipeline processes.

[Brief description of the drawings]

FIG. 1 is a flowchart showing operation contents of a state transition sequencer according to an embodiment of the invention.

FIG. 2 is a schematic diagram showing a flow of pipeline processing when an exception processing occurs in the embodiment of the present invention.

FIG. 3 is a schematic diagram showing a flow of general 5-stage pipeline processing.

FIG. 4 is a block diagram showing a configuration of a general microprocessor.

FIG. 5 is a flowchart showing the operation contents of a state transition sequencer in a conventional example.

FIG. 6 is a schematic diagram showing a flow of pipeline processing when an exception processing occurs in a conventional example.

[Explanation of symbols]

1 ... Decoder, 2 ... Data path, 2-1 ...
Operation unit, 2-2 ... Register file, 2-3 ...
Program counter, 2-3-1, ... PC register,
2-3-2 ... PSR register, 2-4 ... Address unit, 3 ... Data bus, 4 ... Address bus, 5 ... Control bus.

Claims (4)

[Claims] 1. An information processing apparatus for setting a branch destination address by memory indirect addressing at the time of transition to an exception processing state, wherein the branch destination address for exception processing is set by a normal instruction. 2. The information processing apparatus according to claim 1, wherein
When an exception processing interrupt is made, the normal counter is set after saving the program counter and program state of the program being executed, and the normal instruction is set based on the address value or address offset value from the exception processing source. An information processing device characterized by setting a branch destination address by executing the information processing device. 3. The information processing apparatus according to claim 1 or 2, wherein the normal instruction is a jump instruction. 4. In an exception processing sequencer for executing exception processing by memory indirect addressing, a normal instruction that can be used for branch processing is loaded and set in the program counter after a program state and program counter save instruction. A sequencer for exception processing in which the instruction to set is set.