JPH09106949A - Compound semiconductor substrate and manufacturing method thereof - Google Patents
Compound semiconductor substrate and manufacturing method thereofInfo
- Publication number
- JPH09106949A JPH09106949A JP26140295A JP26140295A JPH09106949A JP H09106949 A JPH09106949 A JP H09106949A JP 26140295 A JP26140295 A JP 26140295A JP 26140295 A JP26140295 A JP 26140295A JP H09106949 A JPH09106949 A JP H09106949A
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- Prior art keywords
- compound semiconductor
- thin film
- semiconductor thin
- substrate
- temperature
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- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
(57)【要約】
【課題】 化合物半導体薄膜12表面が平坦とならず、
また結晶性が悪いためHEMT等のデバイス特性が劣化
する。
【解決手段】 Si基板11上に、格子定数の異なる化
合物半導体薄膜20が形成された化合物半導体基板10
において、化合物半導体薄膜20が第1の結晶成長温度
で形成され、第2の結晶成長温度以上650℃以下の温
度で熱処理された第1の化合物半導体薄膜12aと、第
1の化合物半導体薄膜12a上に形成された1〜2原子
層の金属薄膜13aと、金属薄膜13a上に第2の結晶
成長温度で形成された第2の化合物半導体薄膜14とか
らなる。
(57) Abstract: The surface of the compound semiconductor thin film 12 is not flat,
In addition, device characteristics such as HEMT are deteriorated due to poor crystallinity. SOLUTION: A compound semiconductor substrate 10 in which compound semiconductor thin films 20 having different lattice constants are formed on a Si substrate 11
On the first compound semiconductor thin film 12a, the compound semiconductor thin film 20 is formed at the first crystal growth temperature and heat-treated at a temperature not lower than the second crystal growth temperature and not higher than 650 ° C. And a second compound semiconductor thin film 14 formed on the metal thin film 13a at the second crystal growth temperature.
Description
【0001】[0001]
【発明の属する技術分野】本発明は化合物半導体基板及
びその製造方法に関し、より詳細には、例えば光または
高速電子デバイス等に使用される化合物半導体基板及び
その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor substrate and a method for manufacturing the same, and more particularly to a compound semiconductor substrate used for, for example, an optical or high-speed electronic device and a method for manufacturing the same.
【0002】[0002]
【従来の技術】近年、基板上にこれとは異種の化合物半
導体薄膜をエピタキシャル成長させ、該化合物半導体薄
膜及び前記基板におけるそれぞれの長所を活用可能な化
合物半導体基板の製造が研究されている。例えばシリコ
ン(以下、Siと記す)基板上にGaAs薄膜をエピタ
キシャル成長させることにより、Si基板が有する機械
的強度とGaAsが有する高速応答性とを兼ね備えた化
合物半導体基板(GaAs/Si)が作製されており、
このような方法によって得られた化合物半導体基板は、
電子デバイス、光デバイス等に応用されている。2. Description of the Related Art In recent years, a compound semiconductor thin film, which is different from the compound semiconductor thin film, is epitaxially grown on a substrate, and the manufacture of the compound semiconductor thin film and a compound semiconductor substrate capable of utilizing respective advantages of the substrate have been studied. For example, by epitaxially growing a GaAs thin film on a silicon (hereinafter referred to as Si) substrate, a compound semiconductor substrate (GaAs / Si) having both the mechanical strength of the Si substrate and the high-speed response of GaAs is manufactured. Cage,
The compound semiconductor substrate obtained by such a method is
It is applied to electronic devices and optical devices.
【0003】しかしながら、前記化合物半導体基板(G
aAs/Si)におけるSiとGaAsとでは格子定数
が異なっており、GaAs層をSi基板上に直接エピタ
キシャル成長させることは困難であった。この問題に対
処するため、2段階成長法による製造方法が提案されて
いる(Akiyama et al:Japanese Journal of AppliedPhy
sics Vol.23(1984),No.11,L843 〜L845)。これは、ま
ず400〜500℃程度の比較的低温(第1の結晶成長
温度)において約5〜20nmのアモルファス状態に近
いGaAs等の第1の化合物半導体薄膜をSi基板上に
成長させる。次に600〜750℃程度の比較的高温
(第2の結晶成長温度)まで昇温して前記第1の化合物
半導体薄膜を固相成長により単結晶化させると共に、こ
の上にGaAs等の第2の化合物半導体薄膜を所望の膜
厚だけエピタキシャル成長させる方法である。However, the compound semiconductor substrate (G
Since Si and GaAs in (aAs / Si) have different lattice constants, it was difficult to directly epitaxially grow the GaAs layer on the Si substrate. In order to deal with this problem, a two-step growth method has been proposed (Akiyama et al: Japanese Journal of Applied Phy.
sics Vol.23 (1984), No.11, L843 ~ L845). First, at a relatively low temperature (first crystal growth temperature) of about 400 to 500 [deg.] C., a first compound semiconductor thin film of GaAs or the like having an amorphous state of about 5 to 20 nm is grown on a Si substrate. Next, the temperature is raised to a relatively high temperature (second crystal growth temperature) of about 600 to 750 ° C. to single crystallize the first compound semiconductor thin film by solid phase growth, and a second crystal of GaAs or the like is formed thereon. Is a method of epitaxially growing the compound semiconductor thin film of (3) by a desired thickness.
【0004】[0004]
【発明が解決しようとする課題】上記2段階成長法によ
る化合物半導体基板の製造方法では、Si基板上に化合
物半導体薄膜をエピタキシャル成長させることができ
る。しかし図3に示したように、Si基板11上にアモ
ルファス状態に近い第1の化合物半導体薄膜12を成長
させた場合(図3(a))、これらの界面近傍に第1の
化合物半導体薄膜12とSi基板11との格子定数の差
に基づく歪みエネルギーが発生し易い。また第1の結晶
成長温度から第2の結晶成長温度に昇温すると、熱の影
響により第1の化合物半導体薄膜12が凝集して島状結
晶12bとなる(図3(b))。図示しないが、さらに
この島状結晶12b上に第2の化合物半導体薄膜をエピ
タキシャル成長させると、島が大きくなり島同士が会合
する際に会合部近傍に転位が発生したり、これら島状結
晶12b表面の凹凸形状を反映し、前記第2の化合物半
導体薄膜の表面に表面荒れが発生する。このような化合
物半導体基板により高電子移動度トランジスタ(HEM
T:High Electron Mobility Transistor)等の電子デバ
イスを形成すると、活性層界面における二次元電子ガス
の移動度が低下し易く、素子の特性が劣化するという課
題があった。In the method of manufacturing a compound semiconductor substrate by the above two-step growth method, a compound semiconductor thin film can be epitaxially grown on a Si substrate. However, as shown in FIG. 3, when the first compound semiconductor thin film 12 close to the amorphous state is grown on the Si substrate 11 (FIG. 3A), the first compound semiconductor thin film 12 is formed near the interface between these. Strain energy based on the difference in lattice constant between the Si substrate 11 and the Si substrate 11 is easily generated. Further, when the temperature is raised from the first crystal growth temperature to the second crystal growth temperature, the first compound semiconductor thin film 12 aggregates due to the effect of heat to form island crystals 12b (FIG. 3B). Although not shown, when the second compound semiconductor thin film is further epitaxially grown on the island-shaped crystals 12b, the islands become large and dislocations occur near the meeting points when the islands meet with each other, and the surface of these island-shaped crystals 12b grows. The surface roughness occurs on the surface of the second compound semiconductor thin film, reflecting the uneven shape of the above. With such a compound semiconductor substrate, a high electron mobility transistor (HEM
When an electronic device such as T: High Electron Mobility Transistor) is formed, there is a problem that the mobility of the two-dimensional electron gas at the interface of the active layer is likely to be lowered and the characteristics of the device are deteriorated.
【0005】本発明はこのような課題に鑑みなされたも
のであり、島状結晶が形成されることなく、表面が平坦
で、かつ結晶性に優れた化合物半導体薄膜がSi基板上
にエピタキシャル成長された化合物半導体基板及びその
製造方法を提供することを目的としている。The present invention has been made in view of these problems, and a compound semiconductor thin film having a flat surface and excellent crystallinity was epitaxially grown on a Si substrate without forming island crystals. An object is to provide a compound semiconductor substrate and a method for manufacturing the same.
【0006】[0006]
【課題を解決するための手段及びその効果】HEMT等
のデバイス特性を決定する前記Si基板の平坦性を向上
させるためには、前記第1の化合物半導体薄膜が前記熱
処理により凝集し、島状になることを抑制すればよい。Means for Solving the Problems and Effects Thereof In order to improve the flatness of the Si substrate that determines device characteristics such as HEMT, the first compound semiconductor thin film is aggregated by the heat treatment to form islands. It should be suppressed.
【0007】一般に前記島状化の際には、前記第1の化
合物半導体薄膜及びSi基板の表面エネルギーと、前記
第1の化合物半導体薄膜と前記Si基板との間の界面エ
ネルギーとの関係において、前記第1の化合物半導体薄
膜の表面エネルギーが最小になるように形状が決定され
る。従って、前記第1の化合物半導体薄膜の表面エネル
ギーを低下させることができれば上記島状化を抑制する
ことが可能となる。Generally, at the time of the island formation, the relationship between the surface energy of the first compound semiconductor thin film and the Si substrate and the interface energy between the first compound semiconductor thin film and the Si substrate is as follows: The shape is determined so that the surface energy of the first compound semiconductor thin film is minimized. Therefore, if the surface energy of the first compound semiconductor thin film can be lowered, the island formation can be suppressed.
【0008】本発明者らは、前記第1の化合物半導体薄
膜を形成した後に金属薄膜を1〜2原子層形成し、その
後熱処理することにより、前記第1の化合物半導体薄膜
の島状化を抑制し得ることを見い出し、本発明を完成す
るに至った。The present inventors suppress the formation of islands of the first compound semiconductor thin film by forming a metal thin film of 1 to 2 atomic layers after forming the first compound semiconductor thin film and then performing heat treatment. The inventors have found what can be done and have completed the present invention.
【0009】すなわち上記目的を達成するために本発明
に係る化合物半導体基板は、Si基板上に、化合物半導
体薄膜が形成された化合物半導体基板において、前記化
合物半導体薄膜が、第1の結晶成長温度で形成され、第
2の結晶成長温度以上650℃以下の温度で熱処理され
た第1の化合物半導体薄膜と、該第1の化合物半導体薄
膜上に形成された1〜2原子層の金属薄膜と、該金属薄
膜上に前記第2の結晶成長温度で形成された第2の化合
物半導体薄膜とからなることを特徴としている。That is, in order to achieve the above object, the compound semiconductor substrate according to the present invention is a compound semiconductor substrate in which a compound semiconductor thin film is formed on a Si substrate, wherein the compound semiconductor thin film is at a first crystal growth temperature. A first compound semiconductor thin film formed and heat-treated at a temperature not lower than a second crystal growth temperature and not higher than 650 ° C .; a metal thin film having 1 to 2 atomic layers formed on the first compound semiconductor thin film; It is characterized by comprising a second compound semiconductor thin film formed on the metal thin film at the second crystal growth temperature.
【0010】上記化合物半導体基板によれば、表面が平
坦で、かつ結晶性に優れた化合物半導体薄膜がSi基板
上にエピタキシャル成長しており、HEMT等のデバイ
ス特性を向上させることができる。According to the above compound semiconductor substrate, the compound semiconductor thin film having a flat surface and excellent crystallinity is epitaxially grown on the Si substrate, and device characteristics such as HEMT can be improved.
【0011】金属薄膜が厚くなると、熱処理時に島状化
が起こる。一方、薄すぎると金属薄膜を形成する効果が
ない。金属薄膜は1〜2原子層とするのが良く、1原子
層で形成するのが最適である。When the metal thin film becomes thick, island formation occurs during heat treatment. On the other hand, if it is too thin, there is no effect of forming a metal thin film. The metal thin film is preferably 1 to 2 atomic layers, and most preferably formed to be 1 atomic layer.
【0012】また、本発明に係る化合物半導体基板の製
造方法は、Si基板上に、化合物半導体薄膜を形成する
化合物半導体基板の製造方法において、第1の結晶成長
温度で第1の化合物半導体薄膜を形成する工程と、前記
第1の化合物半導体薄膜上に金属薄膜を1〜2原子層形
成する工程と、第2の結晶成長温度以上650℃以下の
温度まで昇温させて熱処理を施す工程と、前記第2の結
晶成長温度で第2の化合物半導体薄膜を形成する工程と
を含むことを特徴としている。The method of manufacturing a compound semiconductor substrate according to the present invention is the method of manufacturing a compound semiconductor substrate in which a compound semiconductor thin film is formed on a Si substrate, wherein the first compound semiconductor thin film is formed at a first crystal growth temperature. A step of forming, a step of forming a metal thin film of 1 to 2 atomic layers on the first compound semiconductor thin film, and a step of performing heat treatment by raising the temperature to a temperature of not lower than a second crystal growth temperature and not higher than 650 ° C. And a step of forming a second compound semiconductor thin film at the second crystal growth temperature.
【0013】上記化合物半導体基板の製造方法によれ
ば、第1の化合物半導体薄膜を形成した後に金属薄膜を
1〜2原子層形成することにより、第1の化合物半導体
薄膜の表面エネルギーを低下させ、熱処理時の第1の化
合物半導体薄膜の島状化を抑制し得るため、化合物半導
体薄膜の表面平坦性及び結晶性に優れた化合物半導体基
板を形成することができる。この熱処理温度が650℃
を超えると島状化が起こるので、この温度は第2の結晶
成長温度以上650℃以下とする。According to the above method of manufacturing a compound semiconductor substrate, the first compound semiconductor thin film is formed, and then the metal thin film is formed by one or two atomic layers to reduce the surface energy of the first compound semiconductor thin film. Since the island formation of the first compound semiconductor thin film during the heat treatment can be suppressed, the compound semiconductor substrate having excellent surface flatness and crystallinity of the compound semiconductor thin film can be formed. This heat treatment temperature is 650 ° C
If it exceeds, the island formation occurs, so this temperature is set to the second crystal growth temperature or more and 650 ° C. or less.
【0014】[0014]
【発明の実施の形態】以下、本発明に係る化合物半導体
基板及びその製造方法の実施の形態を図面に基づいて説
明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a compound semiconductor substrate and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.
【0015】図1は化合物半導体薄膜にGaAs、金属
薄膜にInを使用した場合の実施の形態に係る化合物半
導体基板(GaAs/Si)の構造を示した模式的断面
図であり、図2(a)〜(c)は該化合物半導体基板を
製造するにあたっての工程の一部を示した模式的部分断
面図である。なお、従来例と同一の機能を有する構成部
品には同一の符合を付すものとする。FIG. 1 is a schematic sectional view showing the structure of a compound semiconductor substrate (GaAs / Si) according to the embodiment when GaAs is used for the compound semiconductor thin film and In is used for the metal thin film. )-(C) are schematic partial cross-sectional views showing a part of the steps in manufacturing the compound semiconductor substrate. Note that components having the same functions as those of the conventional example are denoted by the same reference numerals.
【0016】Si基板11の上には第1の化合物半導体
薄膜12aが形成され、第1の化合物半導体薄膜12a
の上には金属薄膜13aが形成されており、さらにその
上には第2の化合物半導体薄膜14が形成されている。
これら第1の化合物半導体薄膜12a、金属薄膜13a
及び第2の化合物半導体薄膜14から化合物半導体薄膜
20が構成されている。A first compound semiconductor thin film 12a is formed on the Si substrate 11, and the first compound semiconductor thin film 12a is formed.
A metal thin film 13a is formed on the above, and a second compound semiconductor thin film 14 is further formed thereon.
These first compound semiconductor thin film 12a and metal thin film 13a
The compound semiconductor thin film 20 is composed of the second compound semiconductor thin film 14 and the second compound semiconductor thin film 14.
【0017】上記した構成の化合物半導体基板10を製
造するにあたっては、まずSi基板11の表面をフッ酸
系エッチャントを用いて洗浄し、Si基板11上の自然
酸化膜(図示せず)を除去した後、アンモニア水、過酸
化水素水及び純水の混合水溶液中に浸漬し、表面保護膜
としての薄い酸化膜を形成する。次にこれを超高真空チ
ャンバー(図示せず)内に載置した後、該チャンバー内
を加熱し、Si基板11を所定の基板温度まで上昇させ
て前記酸化膜を除去し、清浄表面を形成する。次にSi
基板11を所定の基板温度まで降温させ、エピタキシャ
ル成長装置(図示せず)のGaセルとAsセルとを開け
て、所定の成長速度、所定のAsに対するGaの分圧比
(Asの蒸気圧に対するGaの蒸気圧の比)にて第1の
化合物半導体薄膜(熱処理前)12を所定厚みまでエピ
タキシャル成長させる(図2(a))。その後、前記G
aセルと前記Asセルとを閉じ、前記降温時の基板温度
のままInセルを開けて第1の化合物半導体薄膜(熱処
理前)12上に金属薄膜(熱処理前)13を1〜2原子
層形成する(図2(b))。次に、前記Asセルを開け
てAsフラックスを照射しながら所定の基板温度まで昇
温させ、5〜10分間熱処理を施した後(図2
(c))、該基板温度を維持したままGaセルを開けて
所定の成長速度、所定のAsに対するGaの分圧比にて
第2の化合物半導体薄膜14を所定厚み成長させる。In manufacturing the compound semiconductor substrate 10 having the above structure, the surface of the Si substrate 11 is first cleaned using a hydrofluoric acid-based etchant to remove the natural oxide film (not shown) on the Si substrate 11. After that, it is immersed in a mixed aqueous solution of aqueous ammonia, hydrogen peroxide and pure water to form a thin oxide film as a surface protective film. Next, after placing this in an ultra-high vacuum chamber (not shown), the inside of the chamber is heated to raise the Si substrate 11 to a predetermined substrate temperature to remove the oxide film and form a clean surface. To do. Next, Si
The substrate 11 is cooled to a predetermined substrate temperature, the Ga cell and the As cell of an epitaxial growth apparatus (not shown) are opened, and a predetermined growth rate, a partial pressure ratio of Ga to a predetermined As (Ga to a vapor pressure of As). The first compound semiconductor thin film (before heat treatment) 12 is epitaxially grown to a predetermined thickness at a vapor pressure ratio) (FIG. 2A). Then, the G
The a cell and the As cell are closed, the In cell is opened with the substrate temperature at the time of the temperature decrease, and a metal thin film (before heat treatment) 13 is formed on the first compound semiconductor thin film (before heat treatment) 12 in an amount of 1 to 2 atomic layers. (FIG. 2B). Next, after opening the As cell and heating the substrate to a predetermined substrate temperature while irradiating with As flux, heat treatment is performed for 5 to 10 minutes (see FIG. 2).
(C)) While maintaining the substrate temperature, the Ga cell is opened, and the second compound semiconductor thin film 14 is grown to a predetermined thickness at a predetermined growth rate and a predetermined partial pressure ratio of Ga to As.
【0018】なお、本実施の形態では成長法として分子
線エピタキシー(MBE)法を用いたが、何らこれに限
定されるものでなく、別の実施の形態として有機金属気
相成長(MOCVD)法でも可能である。この場合、原
料にはトリメチルガリウム(TMG)、アルシン(As
H3 )、トリメチルインジウム(TMI)を用いる。Although the molecular beam epitaxy (MBE) method is used as the growth method in the present embodiment, the growth method is not limited to this, and as another embodiment, a metal organic chemical vapor deposition (MOCVD) method is used. But it is possible. In this case, the raw materials are trimethylgallium (TMG) and arsine (As
H 3 ) and trimethylindium (TMI) are used.
【0019】また、本実施の形態では化合物半導体薄膜
20としてGaAsを原料に用いたが、何らこれに限定
されるものでなく、別の実施の形態としてInP、Ga
P、InAs等の化合物半導体薄膜等を成長させること
も可能である。Further, in this embodiment, GaAs is used as a raw material for the compound semiconductor thin film 20, but the present invention is not limited to this, and InP and Ga may be used as another embodiment.
It is also possible to grow a compound semiconductor thin film such as P or InAs.
【0020】また、本実施の形態では金属薄膜13aと
してInを原料に用いたが、何らこれに限定されるもの
でなく、別の形態としては、第1及び第2の化合物半導
体に用いる元素以外でこれらの化合物半導体と混晶を形
成するか、n型、p型のドーパントとなり得る金属元素
であればよく、Sn、Sb、Bi等を用いることもでき
る。In addition, although In is used as a raw material for the metal thin film 13a in the present embodiment, the present invention is not limited to this. In another form, elements other than the elements used for the first and second compound semiconductors are used. Any metal element that can form a mixed crystal with these compound semiconductors or can serve as an n-type or p-type dopant can be used, and Sn, Sb, Bi, or the like can also be used.
【0021】[0021]
薄膜形成方法:分子線エピタキシー法 原料:固体のGa、As、In Si基板11:(001)面方位を有し、[110]方
向に2°傾いたSi基板 Si基板11表面の酸化膜除去時の基板温度:900℃ 降温時の基板温度:400℃ 第1の化合物半導体薄膜12aの膜厚:0.1μm 第1の化合物半導体薄膜(熱処理前)12の成長速度:
0.3μm/h 第1の化合物半導体薄膜(熱処理前)12成長時のAs
に対するGaの分圧比:10 昇温時の基板温度:600℃ 熱処理時間:10分 第2の化合物半導体薄膜14の膜厚:3μm 第2の化合物半導体薄膜14の成長速度:1.0μm/
h 第2の化合物半導体薄膜14の成長時のAsに対するG
aの分圧比:20 以下に、実施例に係る製造方法により成長させた化合物
半導体薄膜20に関し、平坦度及び結晶性を調査した結
果について説明する。Thin film forming method: Molecular beam epitaxy Raw material: Solid Ga, As, In Si substrate 11: Si substrate having (001) plane orientation and tilted by 2 ° in [110] direction When removing oxide film on Si substrate 11 surface Substrate temperature: 900 ° C. Substrate temperature during cooling: 400 ° C. Film thickness of first compound semiconductor thin film 12a: 0.1 μm Growth rate of first compound semiconductor thin film (before heat treatment) 12:
0.3 μm / h As during growth of first compound semiconductor thin film (before heat treatment) 12
Ratio of Ga to Ga: 10 Substrate temperature during heating: 600 ° C. Heat treatment time: 10 minutes Thickness of second compound semiconductor thin film 14: 3 μm Growth rate of second compound semiconductor thin film 14: 1.0 μm /
h G for As during the growth of the second compound semiconductor thin film 14
Partial pressure ratio of a: 20 Hereinafter, the results of investigating the flatness and crystallinity of the compound semiconductor thin film 20 grown by the manufacturing method according to the example will be described.
【0022】平坦度として第2の化合物半導体薄膜14
の表面粗さを原子間力顕微鏡(AFM)により測定し、
基準仮想平面上の凸部の高さの標準偏差に基づいて評価
した結果を表1に示す。なお、比較例として従来の2段
階成長法により形成された化合物半導体薄膜を用いて評
価した結果を表1に併記する。The second compound semiconductor thin film 14 has a flatness.
The surface roughness of is measured by an atomic force microscope (AFM),
Table 1 shows the results of evaluation based on the standard deviation of the heights of the convex portions on the reference virtual plane. As a comparative example, Table 1 also shows the results of evaluation using a compound semiconductor thin film formed by the conventional two-step growth method.
【0023】[0023]
【表1】 [Table 1]
【0024】表1から明らかなように、比較例に係る化
合物半導体薄膜の平坦度5.0〜6.0nmに比べ、実
施例に係る化合物半導体薄膜20の平坦度は3.0〜
3.5nmとなっており、第1の化合物半導体薄膜12
a及び第2の化合物半導体薄膜14の表面が平坦化され
ている。As is clear from Table 1, the flatness of the compound semiconductor thin film 20 of the example is 3.0 to 6.0 nm as compared with the flatness of the compound semiconductor thin film of the comparative example of 5.0 to 6.0 nm.
The thickness is 3.5 nm, and the first compound semiconductor thin film 12
The surfaces of a and the second compound semiconductor thin film 14 are flattened.
【0025】次に、結晶性として化合物半導体薄膜20
の結晶性をX線2結晶回折ピークの半値幅により評価し
た結果を表2に示す。なお、比較例に関しては上記平坦
度の調査に用いたものと同様である。Next, the compound semiconductor thin film 20 is crystallized.
Table 2 shows the results of evaluation of the crystallinity of the above by the half width of the X-ray 2 crystal diffraction peak. The comparative example is the same as that used in the investigation of the flatness.
【0026】[0026]
【表2】 [Table 2]
【0027】表2から明らかなように、比較例の場合に
比べて実施例に係る化合物半導体薄膜20の場合、結晶
性に優れており、第1の化合物半導体薄膜12a、第2
の化合物半導体薄膜14中の転移密度が減少している。As is clear from Table 2, the compound semiconductor thin film 20 according to the example has excellent crystallinity as compared with the comparative example, and the first compound semiconductor thin film 12a and the second compound semiconductor thin film
The dislocation density in the compound semiconductor thin film 14 is decreased.
【0028】上記結果から明らかなように、実施例に係
る化合物半導体基板10によれば、化合物半導体薄膜2
0が第1の結晶成長温度で形成され、第2の結晶成長温
度以上650℃以下の温度で熱処理された第1の化合物
半導体薄膜12aと、第1の化合物半導体薄膜12a上
に形成された1〜2原子層の金属薄膜13aと、金属薄
膜13a上に前記第2の結晶成長温度で形成された第2
の化合物半導体薄膜14とからなっているので、化合物
半導体薄膜20の表面が平坦で、かつ結晶性に優れてい
ることによりHEMT等のデバイス特性を向上させるこ
とができる。As is clear from the above results, according to the compound semiconductor substrate 10 of the example, the compound semiconductor thin film 2
0 is formed at the first crystal growth temperature and is heat-treated at a temperature not lower than the second crystal growth temperature and not higher than 650 ° C., and 1 is formed on the first compound semiconductor thin film 12a. ˜2 atomic layer metal thin film 13a and a second thin film formed on the metal thin film 13a at the second crystal growth temperature
Since the compound semiconductor thin film 14 is composed of the compound semiconductor thin film 14, the compound semiconductor thin film 20 has a flat surface and excellent crystallinity, so that device characteristics such as HEMT can be improved.
【0029】また、実施例に係る化合物半導体基板10
の製造方法によれば、第1の結晶成長温度で第1の化合
物半導体薄膜(熱処理前)12を形成する工程と、第1
の化合物半導体薄膜(熱処理前)12上に金属薄膜(熱
処理前)13を1〜2原子層形成する工程と、第2の結
晶成長温度以上650℃以下の温度まで昇温させて熱処
理を施す工程と、前記第2の結晶成長温度で第2の化合
物半導体薄膜14を形成する工程とを含んでいるので、
第1の化合物半導体薄膜(熱処理前)12の表面エネル
ギーを低下させ、熱処理時の第1の化合物半導体薄膜
(熱処理前)12の島状化を抑制し得るため、化合物半
導体薄膜20の表面平坦性及び結晶性に優れた化合物半
導体基板10を形成することができる。Further, the compound semiconductor substrate 10 according to the embodiment.
According to the manufacturing method of 1., the step of forming the first compound semiconductor thin film (before heat treatment) 12 at the first crystal growth temperature;
Forming 1 to 2 atomic layers of a metal thin film (before heat treatment) 13 on the compound semiconductor thin film (before heat treatment) 12 and performing heat treatment by raising the temperature to a temperature not lower than the second crystal growth temperature and not higher than 650 ° C. And the step of forming the second compound semiconductor thin film 14 at the second crystal growth temperature,
Since the surface energy of the first compound semiconductor thin film (before heat treatment) 12 can be lowered and the islanding of the first compound semiconductor thin film (before heat treatment) 12 at the time of heat treatment can be suppressed, the surface flatness of the compound semiconductor thin film 20. Also, the compound semiconductor substrate 10 having excellent crystallinity can be formed.
【図1】本発明の実施の形態に係る化合物半導体基板を
示した模式的断面図である。FIG. 1 is a schematic cross-sectional view showing a compound semiconductor substrate according to an embodiment of the present invention.
【図2】実施の形態に係る化合物半導体基板の製造工程
の一部を工程順に示した模式的部分断面図である。FIG. 2 is a schematic partial cross-sectional view showing a part of the manufacturing process of the compound semiconductor substrate according to the embodiment in the order of processes.
【図3】従来の2段階成長法による化合物半導体基板の
製造工程の一部を工程順に示した模式的部分断面図であ
る。FIG. 3 is a schematic partial cross-sectional view showing, in the order of steps, part of a conventional method of manufacturing a compound semiconductor substrate by a two-step growth method.
11 Si基板 12a 第1の化合物半導体薄膜 13a 金属薄膜 14 第2の化合物半導体薄膜 20 化合物半導体薄膜 11 Si substrate 12a First compound semiconductor thin film 13a Metal thin film 14 Second compound semiconductor thin film 20 Compound semiconductor thin film
Claims (2)
された化合物半導体基板において、前記化合物半導体薄
膜が、第1の結晶成長温度で形成され、第2の結晶成長
温度以上650℃以下の温度で熱処理された第1の化合
物半導体薄膜と、該第1の化合物半導体薄膜上に形成さ
れた1〜2原子層の金属薄膜と、該金属薄膜上に前記第
2の結晶成長温度で形成された第2の化合物半導体薄膜
とからなることを特徴とする化合物半導体基板。1. A compound semiconductor substrate having a compound semiconductor thin film formed on a Si substrate, wherein the compound semiconductor thin film is formed at a first crystal growth temperature and at a temperature of not lower than a second crystal growth temperature and not higher than 650 ° C. Formed on the first compound semiconductor thin film, a metal thin film of 1 to 2 atomic layers formed on the first compound semiconductor thin film, and formed on the metal thin film at the second crystal growth temperature. A compound semiconductor substrate comprising a second compound semiconductor thin film.
する化合物半導体基板の製造方法において、第1の結晶
成長温度で第1の化合物半導体薄膜を形成する工程と、
前記第1の化合物半導体薄膜上に金属薄膜を1〜2原子
層形成する工程と、第2の結晶成長温度以上650℃以
下の温度まで昇温させて熱処理を施す工程と、前記第2
の結晶成長温度で第2の化合物半導体薄膜を形成する工
程とを含むことを特徴とする化合物半導体基板の製造方
法。2. A method of manufacturing a compound semiconductor substrate for forming a compound semiconductor thin film on a Si substrate, the method comprising forming a first compound semiconductor thin film at a first crystal growth temperature,
Forming a metal thin film of 1 to 2 atomic layers on the first compound semiconductor thin film; performing a heat treatment by raising the temperature to a second crystal growth temperature or more and 650 ° C. or less;
And a step of forming a second compound semiconductor thin film at a crystal growth temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26140295A JPH09106949A (en) | 1995-10-09 | 1995-10-09 | Compound semiconductor substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26140295A JPH09106949A (en) | 1995-10-09 | 1995-10-09 | Compound semiconductor substrate and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09106949A true JPH09106949A (en) | 1997-04-22 |
Family
ID=17361376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26140295A Pending JPH09106949A (en) | 1995-10-09 | 1995-10-09 | Compound semiconductor substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09106949A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015053386A (en) * | 2013-09-06 | 2015-03-19 | 旭化成株式会社 | Compound semiconductor substrate manufacturing method and compound semiconductor substrate |
-
1995
- 1995-10-09 JP JP26140295A patent/JPH09106949A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015053386A (en) * | 2013-09-06 | 2015-03-19 | 旭化成株式会社 | Compound semiconductor substrate manufacturing method and compound semiconductor substrate |
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