JPH09114695A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide more effective tracing information for fault analysis or the like. SOLUTION: In two processors 5 and 10, the same pieces of the tracing information 7 and 12 are traced to tracer memories 9 and 14 and turned to the object of double checking at the time of a normal operation. In the prescribed case of debugging or the like, a tracing control signal for instructing tracing in mutually different forms is outputted from a tracer control circuit. As a result, a tracing write circuit 8 on a master side and the tracing write circuit 13 on a slave side perform different tracing control and the different pieces of the tracing information are recorded in the tracer memories 9 and 14. Also a master and a slave are specified by a master/slave control circuit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which adopts a duplication check method (FRM).

[0002]

2. Description of the Related Art In a conventional information processing apparatus of this type, the same internal information is traced in the tracer memory of each processor which is the target of FRM, and the master / master
The slaves are alternately controlled by tracing internal information in the tracer memory.

[0003]

In the trace control in the above-mentioned conventional information processing apparatus, the capacity of the trace memory is limited even when each processor traces the same internal information or when the master / slave is traced alternately. However, there is a problem that failure analysis becomes difficult when a failure occurs that requires more internal information than the capacity of the tracer memory.

[0004]

According to the information processing apparatus of the present invention, two processors having the same configuration operate in the same manner including the trace of internal information to the trace memory during normal operation. In this case, the traces in the two processors are different from each other.

[0005]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which has two processors 5 and 10, and each processor 5 and 10 performs the same operation with the same structure including the FRM mechanism. The master / slave control circuit 1 outputs a master / slave control signal 2 for instructing a master or a slave to the processors 5 and 10. The tracer control circuit 3 outputs, to the processors 5 and 10, a tracer control signal 4 for instructing the write control of the microprogram and the mode for instructing the normal write or the write of only the branch instruction for the trace information 7, 12. .

The trace unit 6 of the processor 5 is composed of a trace write circuit 8 and a tracer memory A9, and the trace unit 11 of the processor 10 is composed of a trace write circuit 13 and a trace memory 14.
As described above, since the processor 5 and the processor 10 have exactly the same structure, they will be collectively described.

Tracer memory 9 and tracer memory 14
Holds the trace information 7 and 12 edited by the trace writing circuit 8 and the trace writing circuit 13, respectively. The trace information 7 and 12 are operation histories of instruction units of microprograms in the processors 5 and 10, and are exactly the same data. The trace write circuits 8 and 13 receive the trace memory 9 and the tracer memory 14 respectively according to the master / slave control signals 2 and 4.
Write control to.

When the master is instructed by the master / slave control signal 2, the tracer write circuits 8 and 13 store their own trace information 7 and 12 according to the instructions of the microprogram regardless of the tracer control signal 4. Write to 9 and 14. Further, when the slave is designated, only when the tracer control signal 4 instructs the writing of the trace information of only the branch instruction, only the branch instruction in the own trace information 7 or 12 is extracted and the own trace memory 9 or Write to 14.

Next, the operation of this embodiment will be described.
Here, description will be given below assuming that the processor 5 is a master and the processor 10 is a slave.

In this case, the master / slave control circuit 1 outputs a master / slave control signal 2 instructing the trace writing circuit 8 of the processor 5 to be the master and the trace writing circuit 13 of the processor 10 to be the slave. The tracer control circuit 3, during normal operation (operation) of the information processing device, is a mode for instructing the write circuit 8 and the trace write circuit 13 to perform normal writing and a tracer control for instructing write control of the microprogram. The signal 4 is output. Therefore, the tracer write circuit 8 and the tracer write circuit 13 are irrespective of the master / slave control signal 2 and trace information 7, 1 as instructed by the tracer control signal 4, respectively.
2 is written in each tracer memory 9, 14. Therefore, the contents of each trace memory at this time are the same, and a double check can be performed by collating and matching the two.

Next, when the information processing apparatus is debugged or a failure occurs, the tracer control circuit 3 instructs the write circuit 8 and the trace write circuit 13 to perform write control of only branch instructions and write control of the microprogram. The tracer control signal 4 for instructing is output. Since the tracer writing circuit 8 is the master, it writes the trace information 7 instructed by the normal microprogram into the tracer memory 9 regardless of the mode in which only the branch instruction of the tracer control signal 4 is instructed. On the other hand, since the tracer writing circuit 13 is a slave, only the branch instruction in the tracer information 12 is extracted and written in the tracer memory 14 according to the mode instructing the writing of only the branch instruction by the tracer control signal 4. In this case, the control of writing the microprogram by the tracer control signal 4 is invalid.

As described above, the trace memory 9 can hold the normal trace information, and the trace memory 14 can hold the trace information of only the branch instruction including the trace information in which the writing to the trace memory is suppressed. .

In this embodiment, when a failure occurs that requires more trace information than the capacity of the tracer memory that can be held on the master side, or trace information that the master side inhibits writing to the trace memory by a sub routine or the like. When the required failure occurs, the slave side holds the trace information for each branch instruction, so that more trace information can be held and the failure analysis becomes very easy. Also, it is effective for grasping the outline of the operation even in the normal failure analysis, especially in the initial analysis.

It should be noted that instead of the branch instruction in the above embodiments, another instruction may be used to switch the trace mode.

Further, in the above embodiment, the tracer control signal 4 is used to instruct the write control of only the branch instruction, but instead of this, another mode, for example, the master side is the normal operation. It is also possible to continue the tracing in the same manner as at the time, stop the tracing at the occurrence of a failure on the slave side, and retain the trace information at that time. In such an embodiment, while the trace information at the time of debugging is obtained on the master side, the trace information up to the point of failure occurrence remains on the slave side, which is convenient for failure analysis.

Further, irrespective of the master side and the slave side, only one processor alternately performs tracing,
Embodiments in which other processors are waiting are readily conceivable. It is good to take over the trace when the capacity of the trace memory overflows.

Since this embodiment traces trace information over two trace memories, it is suitable for recording long trace information that exceeds the capacity of the trace memory.

[0019]

According to the present invention, the same trace information is traced by each processor during the normal operation to perform double check, while the traces in different modes are executed by the two processors at the time of debugging or when a failure occurs.
This has the effect of being able to obtain trace information according to the purpose of the failure analysis.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

 1 Master / Slave Control Circuit 2 Master / Slave Control Signal 3 Trace Control Circuit 4 Trace Control Signal 5 Processor 6 Trace Section 7 Trace Information 8 Tracer Writing Circuit 9 Tracer Memory 10 Processor 11 Trace Section 12 Trace Information 13 Tracer Writing Circuit 14 Tracer Memory .

Claims (6)

[Claims] 1. Two processors having the same configuration operate in the same manner including a trace of internal information to a trace memory at the time of normal operation, but in a predetermined case, the trace is performed by the two processors. An information processing apparatus adopting a duplication check method, which is characterized by mutually different modes. 2. The information processing apparatus according to claim 1, wherein the predetermined case is when the information processing apparatus is debugged or when a failure occurs. 3. The information processing apparatus according to claim 1, wherein the different mode is continuation of a trace similar to the trace during the normal operation and stop of the trace during the normal operation. 4. The different aspect is the continuation of a trace similar to the trace during the normal operation, the waiting of the trace memory overflow by the trace, and the takeover of the continuation, wherein the two processors are alternately arranged. The information processing apparatus according to claim 1, wherein the trace is executed during the normal operation. 5. A master / slave control circuit for outputting a master / slave control signal for instructing master / slave switching, wherein the two processors are in a master / slave relationship, and the mode is designated for each processor. As described above, the tracer control circuit for outputting the trace control signal for controlling the operation of the trace and the master / slave control signal and the trace control signal allow two processors to write the same trace information to the trace memory, or a slave. The information processing apparatus according to claim 1, wherein the processor includes a trace writing circuit that writes only the trace information corresponding to a predetermined instruction of the trace information to the trace memory. 6. The information processing apparatus according to claim 5, wherein the predetermined instruction is a branch instruction.