JPH09121122A - Signal generation method - Google Patents

Abstract

(57) Abstract: A signal generation method capable of improving frequency accuracy without increasing the circuit scale is provided. SOLUTION: Waveform data is stored in a waveform ROM and an address is given to the waveform ROM to generate a waveform.
The address for the waveform ROM is incremented based on the value N, the value L is accumulated, and when the value L reaches a predetermined value, the address is changed based on the address (N + 1). As a result, the accuracy can be improved without increasing the circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a signal generation method suitable for use in a numerically controlled oscillator whose oscillation frequency is controlled according to setting data.

[0002]

2. Description of the Related Art A numerically controlled oscillator is an oscillator whose oscillation frequency is controlled according to setting data. Such a numerically controlled oscillator is used, for example, when forming a signal synchronized with a carrier wave of a signal transmitted via a communication satellite.

That is, in FIG. 3, the antenna 41 receives radio waves from a communication satellite. The carrier wave frequency of the signal sent from this communication satellite may fluctuate due to the Doppler effect. The received signal is converted into a predetermined frequency by a converter 42 arranged near the antenna 41. Then, the signal from the converter 42 is supplied to the down converter 43. The down converter 43 converts this signal into an intermediate frequency signal having a predetermined frequency of several MHz.

The output of the down converter 43 is supplied to the phase comparison circuit 44. Further, the output of the numerically controlled oscillator 45 is supplied to the phase comparison circuit 44. Phase comparison circuit 44
Then, the carrier wave from the down converter 43 and the output signal of the numerically controlled oscillator 45 are compared in phase, and the phase comparison output is supplied to the A / D converter 47 via the low-pass filter 46. The output of the A / D converter 47 is supplied to the numerically controlled oscillator 45. The oscillation frequency of the numerically controlled oscillator 45 is controlled according to the output data of the A / D converter 47. As a result, a signal synchronized with the carrier frequency can be obtained from the numerically controlled oscillator 45.

FIG. 4 shows the configuration of a conventional numerically controlled oscillator used in such a PLL circuit.

In FIG. 4, reference numeral 51 is a controller for setting the frequency. The frequency setting value N is given to the controller 51. The frequency setting value N is supplied to the frequency setting register 52.

The output of the frequency setting register 52 is the adder 5
3 is supplied. The output of the adder 53 is supplied to the address register 54. The output of the address register 54 is supplied to the adder 53.

A clock having a frequency F _C is supplied from the clock generation circuit 55 to the address register 54. The output of the frequency setting register 52 is sequentially accumulated in the adder 53 and the address register 54.

The output of the address register 54 is the waveform generation R
It is supplied to the address of OM56. Waveform generation ROM56
For example, waveform data for one cycle is stored for an address of 2 ⁱ .

Waveform data is output from the waveform generation ROM 56 in accordance with the address from the address register 54. The output of the waveform generation ROM 56 is supplied to the D / A converter 57. The D / A converter 57 converts the waveform data from the waveform shaping ROM 56 into an analog waveform. This analog waveform is output from the output terminal 58.

When the frequency setting value is N, the address A _k generated from the address register 54 is advanced by the adder 53 and the address register 54 at the clock F _c for each frequency setting value N. Since the address A _k is the signal for one cycle when advanced until 2 ⁱ is generated, the address A _k is the time advanced until 2 ⁱ corresponding to the period of the oscillation output which is output from the output terminal 58. This period T _nco is

(Equation 1) Becomes

Therefore, the oscillation frequency F _NCO is F _NCO = F _c (N / 2 ⁱ ). Therefore, the frequency accuracy of the conventional numerically controlled oscillator Δ
F _NCO is ΔF _NCO = F _c × (1/2 ⁱ ).

[0013]

As described above, in the conventional numerically controlled oscillator, the accuracy of the oscillation frequency is ΔF _NCO = F _c × (1/2 ⁱ ). From the above equation, in order to improve the oscillation frequency accuracy, it is sufficient to increase the oscillation frequency F _{c of the} clock or increase the number i of bits of the address.

However, when the clock frequency F _c is increased, the set value N must be accumulated at high speed,
The delay time in the adder 53 has to be shortened. However, there is a limit to the reduction of the delay time of the adder 53. Further, if the number of bits i of the address is increased,
Along with this, the number of circuits increases.

Therefore, an object of the present invention is to provide a signal generation method capable of improving frequency accuracy without increasing the circuit scale.

[0016]

According to the present invention, in a signal generating method in which an address signal is applied to a memory in which waveform data is stored to generate a waveform, the address for the memory advances a first value. And the second value is accumulated, and when the second value reaches a predetermined value,
The signal generating method is characterized in that the address is changed by a predetermined number.

The frequency set value L is accumulated, and when the accumulated value B reaches or exceeds a predetermined value B _max , the frequency set value N is set to (N
A controller 1 is provided for executing the processing of +1). Therefore, the frequency accuracy can be set high.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, reference numeral 1 is a controller for setting a frequency. The controller 1 has
Frequency setpoints N and L are provided. Frequency set value N
Is for setting the main oscillation frequency. The frequency setting value L is for setting a highly accurate oscillation frequency. The frequency setting value N is the frequency setting register 2
Supplied to

When an interrupt signal is given from the M frequency divider 9 to the controller 1, the frequency set value L is accumulated, and when the accumulated value reaches a predetermined value, the frequency set value N is set to (N
A control program for setting +1) is provided.

That is, the clock generation circuit 5 generates a clock of frequency F _C. This clock is supplied to the interrupt terminal of the controller 1 via the M frequency divider 9. When this signal is supplied to the interrupt terminal of the controller 1, the controller 1 executes the interrupt processing as shown in FIG.

That is, in FIG. 2, the frequency setting value L is added to the cumulative value B so far to obtain a new cumulative value B (step 11). The cumulative value B is set to 0 in the initial state.

The obtained cumulative value B is a predetermined maximum value B _max.
It is determined whether or not (step 12).

If the cumulative value B is less than or equal to the maximum value B _max , the frequency setting value set in the frequency setting register 2 is set to N. Then, the normal processing routine is returned to.

[0024] If the accumulated value B is the maximum value B _max or more, the maximum value B _max from the accumulated value B is subtracted, the value (B-B _max)
Is set as a new cumulative value B (step 14).

Then, the frequency setting value set in the frequency setting register 2 is set to (N + 1), and the process returns to the normal processing routine.

In FIG. 1, the output of the frequency setting register 2 is supplied to the adder 3. The output of the adder 3 is supplied to the address register 4. The output of the address register 4 is supplied to the adder 3.

A clock having a frequency F _C is supplied from the clock generation circuit 5 to the address register 4. Adder 3
The output of the frequency setting register 2 is sequentially accumulated in the address register 4.

The output of the address register 4 is the waveform generation RO
It is supplied to the address of M6. The waveform generation ROM 6 contains
For example, one cycle of waveform data is stored for an address of 2 ⁱ .

Waveform data is output from the waveform generation ROM 6 according to the address from the address register 4. The output of the waveform generation ROM 6 is the D / A converter 7
Supplied to Waveform generation ROM in D / A converter 7
The waveform data from 6 is converted into an analog waveform. This analog waveform is output from the output terminal 8.

In one embodiment of the present invention, M
The controller 1 is provided with a program for accumulating the frequency setting value L for each output from the frequency divider 9 and setting the frequency setting value to (N + 1) when the accumulated value B reaches a predetermined value B _max. To be done. Therefore, the frequency accuracy can be set high.

That is, the address A _k generated from the address register 4 is advanced by the clock F _C for each frequency set value N by the adder 3 and the address register 4.
At the same time, the cumulative value B of the frequency setting value L is the predetermined value B
_The frequency setting value N is set to (N + 1) each time it reaches _max .

[0032] The waveform generating ROM6, 2 since ⁱ address in one cycle of the waveform data is stored, the time address A _k generated from the address register 4 is advanced until the 2 ⁱ is output from the waveform generating ROM6 Corresponding to the period of the signal being processed.

Therefore, the oscillation frequency F _NCO of the oscillation output output from the output terminal 8 is

(Equation 2) Becomes

Therefore, the accuracy of the frequency accuracy ΔF _NCO is

(Equation 3) Becomes

[0035]

According to the present invention, the frequency set value L is accumulated, and when the accumulated value B reaches or exceeds the predetermined value B _max ,
A controller 1 is provided which executes a process of setting the frequency setting value N to (N + 1). Therefore, (1
/ B _max ), and the frequency accuracy can be improved without increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a flowchart used to explain an embodiment of the present invention.

FIG. 3 is a block diagram used to describe a numerically controlled oscillator.

FIG. 4 is a block diagram of an example of a conventional numerically controlled oscillator.

[Explanation of symbols]

1: controller, 2: frequency setting register, 3: adder, 4: address register, 5: clock generation circuit

Claims (1)

[Claims] 1. A signal generating method in which an address signal is applied to a memory storing waveform data to generate a waveform, wherein an address for the memory is formed by stepping a first value, and The second value is accumulated, and when the second value reaches a predetermined value,
A signal generating method characterized in that the address is changed by a predetermined number.