JPH09146502A - Liquid crystal display automatic display adjustment method - Google Patents

Abstract

(57) Abstract: A flicker-free liquid crystal display method of a liquid crystal display device for A / D converting a video signal input from the outside and displaying the digitized image data on a liquid crystal panel. A CPU refers to designated line data of a video signal after A / D conversion, and in the data of the same line repeatedly generated by the line data, pixel data changes due to jitter of a sampling clock, An automatic display adjustment method for a liquid crystal display device, characterized in that if the change state of the pixel data is periodic, the division ratio is adjusted, and if the change state is overall, the phase is adjusted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display adjusting method for a color liquid crystal display device which A / D converts a video signal input from the outside and displays the digitized image data on a liquid crystal panel. More specifically, it is suitable for use in a multi-scan liquid crystal display, a computer projection panel, and a liquid crystal projector.

[0002]

2. Description of the Related Art In a conventional liquid crystal display device, a video signal sent from the outside and a video signal output from the computer of each maker and a video signal having a different frequency of the number of display screen dots are faithfully reproduced. It is intended to be reproduced and displayed in. In order to achieve the purpose, it is adjusted by a PLL circuit and a delay circuit. As shown in FIGS. 4 and 5, the delay value of the horizontal synchronizing signal 8 input from the outside can be continuously changed by the delay circuit 9. In the PLL circuit 26, the delayed horizontal synchronizing signal 10 and the sampling clock 14 output from the voltage controlled oscillator 29 are counted N times by the 1 / N counter 13 and 1 / N output signal 12 is output as 1 / N pulse.
The voltage of the voltage controlled oscillator 29 is controlled by the phase voltage conversion signal 28 so that the phases are matched by the phase comparator 27 which compares the phases with the frequency of the video signal transmitted. It was As shown in FIG. 5, the frequency is changed by changing the N (frequency division ratio) of the 1 / N count circuit, and the phase is changed by the delay circuit in order to sample and A / D convert one pixel of the video signal at the most stable timing. I was able to change it so that it could be adjusted to produce clear images without flicker. However, when the frequency division ratio and the phase are out of phase, the pixel is sampled near the boundary between the previous pixel and the next pixel, and the pixel data is not constant and flickers due to the influence of "jitter".

[0003]

In order to obtain a clear image without the above-mentioned flicker, the user finely adjusts the division ratio and adjusts the phase in order to make the frequency equal to that of the video signal while watching the display state. It was finely adjusted so that the display condition would be good. Therefore, it was difficult to adjust, and it was displayed without finding the optimum state.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the conventional problems, in which a CPU refers to designated line data of a video signal after A / D conversion to repeatedly generate the line data. In the same line of data, if the pixel data changes due to the jitter of the sampling clock and the change state of the pixel data is periodic, the dividing ratio is adjusted, and if it is overall, the phase is adjusted. It proposes a display adjustment method.

[0005]

According to the present invention, it is possible to reproduce a clear image free from flicker without requiring the user to make adjustments by connecting the input video signal.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION A method for automatically adjusting the display state of a color liquid crystal display device.

[0007]

An embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is an electrical block diagram showing the configuration of the present invention. 2 and 3 are float charts for processing the automatic adjustment. The configuration will be described with reference to FIG. The input video signal 1 is faithfully amplified by the video amplifier 2 and sent to the A / D converter 3 with a sufficient drive capability. A /
The D converter 3 samples the analog video signal at the rising edge of the sampling clock 14 sent from the PLL circuit 11, converts it into digital image data 4, and sends it to the image memory 5. The image memory 5 is a memory capable of writing and reading in parallel. Regarding the timing of writing the image data 4, a video signal which is repeatedly generated by the horizontal synchronizing signal 8, the vertical synchronizing signal 20 input to the memory controller 19 and the timing signal 18 generated by the sampling clock 14 is written.

In parallel, the memory controller 19
Timing signal 18 for reading data from the image memory 5
To display the image data 6 on the liquid crystal panel 7. Further, the memory controller 19 sends a timing signal 16 for writing the line data of the designated horizontal synchronization period to the line memory 15 to the line memory 15 by setting a designated line from the CPU 23 via the address / data bus 24.

Since the CPU 23 receives the horizontal synchronizing signal 8 and the vertical synchronizing signal 20, it can judge whether the designated line is written in the line memory 15. The CPU 23 can read the data in the line memory 15 via the memory controller 19 and the address / data bus 24. The read data is the work memory 2
5, and can be referenced and operated.

The horizontal synchronizing signal 8 input from the outside is also input to the delay circuit 9, and the horizontal synchronizing signal 10 delayed through the delay circuit 9 is input to the PLL circuit 11. The delay circuit 9 can freely set a delay value by a delay setting signal 22 sent from the CPU 23. The sampling clock 14 generated from the PLL circuit 11 is sent to the 1 / N counter 13, and the 1 / N frequency-divided 1 / N output signal 12 is compared in phase with the delayed horizontal synchronizing signal 10 so that the phases thereof match. The frequency changes, and the number of pixels in one line can be set by setting N (frequency division ratio) of the 1 / N counter 13.

The CPU 23 receives the input horizontal synchronizing signal 8,
By referring to the cycle of the vertical synchronizing signal 20, the approximate frequency division ratio is set in the 1 / N counter 13, so that fine display adjustment processing can be executed. With the above configuration, the CPU 23 freely refers to the line memory 15 and controls the delay circuit 9 and the 1 / N counter 13 to perform sampling at the same frequency as that of the input video signal 1 and the center position of the pixel. be able to.

Next, the automatic adjustment processing method will be described with reference to FIGS. The following conditions are required to execute the automatic adjustment processing. Must be a still image. When the contrast is high to some extent, a change in data from 00H to 0FFH occurs, which facilitates adjustment. First, the first line is designated, the same line is sampled several times, and compared with the previous data, the data value of the same pixel is, for example, 0B0H or more.
Focusing on the pixels having 0H or less, the adjustment process is executed for the line having the most pixels. (Step 1
~ Step 7)

The fact that the data is changed by sampling the same line has the following states. PL
The sampling clock 14 generated by the L circuit 11 has jitter (frequency fluctuation). When the video signal input to the A / D converter 3 is sampled in the vicinity of pixels between pixels, if there is a difference in level between pixels, the pixel data changes each time sampling is performed. Moreover, the symptom is different when the division ratio is not matched and when the phase is not matched. When the division ratio N is different from the true number of pixels, a data change point occurs. When comparing the frequency division ratio N with the phase, the frequency division ratio N must be adjusted first. If 1 is added to the frequency division ratio and the portion where the data largely changes is reduced, it means that the value approaches the true value. On the contrary, when the number increases, the number is decreased by one to get closer. By repeating this process, it can be determined that the value at which there is no periodicity in which the data greatly changes is a true value. (Step 8 to Step 14)

Next, a phase adjustment process is executed. When the frequency division ratio N matches the true value, the phase adjustment processing 2 is executed. First, the delay value is set to 0, the same line is sampled several times, and changes in data are observed (steps 15 to 16). If there is a change in the data, the phases are out of phase, so the delay value is added and the process is repeated until there is no change in the data (steps 17 to 20). If there is no change in data, it means that the phases have started to match, the set value is stored, and the addition is repeated until the change in data occurs (steps 21 to 24). If data change occurs, the intermediate value of the set values with no data change becomes the optimum phase, the delay circuit is set, and the automatic adjustment processing ends (step 25). Further, when the delay value is set to 0, the intermediate value cannot be obtained unless there is a change in the data. Therefore, the delay value is added and the process is repeated until a change in the data occurs (step 17, step 26 to step 2).
8). If a data change has occurred, the processing from step 18 onward is executed to obtain an intermediate value.

[0015]

As described above, by performing the automatic adjustment processing, the user can surely capture the input video signal and obtain the optimum display quality without making a difficult adjustment visually. .

[Brief description of the drawings]

FIG. 1 Electrical block diagram

[Fig. 2] Processing follow chart for adjusting the division ratio

[Fig. 3] Processing follow chart for adjusting the phase

FIG. 4 is an electrical block diagram of a conventional delay circuit and PLL circuit.

FIG. 5 is a sampling timing diagram of a conventional video signal.

[Explanation of symbols]

 1 Video Signal 2 Video Amplifier 3 A / D Converter 4 Image Data 5 Image Memory 6 Image Data 7 Liquid Crystal Panel 8 Horizontal Sync Signal 9 Delay Circuit 10 Delayed Horizontal Sync Signal 11 PLL Circuit 12 1 / N Output Signal 13 1 / N Counter 14 Sampling Clock 15 Line Memory 16 Timing Signal 17 1 Line Image Data 18 Timing Signal 19 Memory Controller 20 Vertical Sync Signal 21 Dividing Ratio Setting Signal 22 Delay Setting Signal 23 CPU 24 Address / Data Bus 25 Work Memory 26 PLL Circuit 27 Phase Comparator 28 Phase voltage conversion signal 29 Voltage controlled oscillator

Claims (1)

[Claims] 1. A CPU refers to specified line data of a video signal after A / D conversion, and in the data of the same line repeatedly generated by the line data, pixel data changes due to jitter of a sampling clock, An automatic display adjustment method for a liquid crystal display device, characterized in that if the change state of the pixel data is periodic, the division ratio is adjusted, and if it is overall, the phase is adjusted.