JPH09148367A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH09148367A
JPH09148367A JP7305356A JP30535695A JPH09148367A JP H09148367 A JPH09148367 A JP H09148367A JP 7305356 A JP7305356 A JP 7305356A JP 30535695 A JP30535695 A JP 30535695A JP H09148367 A JPH09148367 A JP H09148367A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
semiconductor integrated
wiring pattern
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7305356A
Other languages
Japanese (ja)
Inventor
Nobuo Fujiwara
信夫 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7305356A priority Critical patent/JPH09148367A/en
Publication of JPH09148367A publication Critical patent/JPH09148367A/en
Pending legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【課題】TABテープを絶縁体又は絶縁処理が施された
導電体に置き換えることによりキャリアを不要にしてコ
スト低減,製造工程の簡略化を可能とし、安価で製造効
率が高く、放熱効果の優れた半導体集積回路装置を提供
する。 【解決手段】熱伝導性の良い金属9にOLB用窓2とI
LB用窓3を設け、その表面に配線パターン5と試験用
パッド6を絶縁性の接着剤にて接着し、配線パターン5
の先端部と半導体チップ7を電気的に接続して表面をポ
ッティング樹脂にて封止する。
(57) 【Abstract】 PROBLEM TO BE SOLVED: To replace a TAB tape with an insulator or a conductor subjected to an insulation treatment to eliminate the need for a carrier, reduce the cost, and simplify the manufacturing process. Provided is a semiconductor integrated circuit device having excellent heat dissipation effect. SOLUTION: An OLB window 2 and I are formed on a metal 9 having good thermal conductivity.
The LB window 3 is provided, and the wiring pattern 5 and the test pad 6 are adhered to the surface thereof with an insulating adhesive to form the wiring pattern 5
The tip of the semiconductor chip 7 and the semiconductor chip 7 are electrically connected and the surface is sealed with potting resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体集積回路装置
に関し、特にTABテープを利用した半導体集積回路装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device using a TAB tape.

【0002】[0002]

【従来の技術】従来、TABテープを利用した半導体集
積回路装置(特にTape Carrier Pack
age)(以下、TPCと記す)ではテープを使用して
いるため、そのままでは、曲げ,ねじり等の強度が弱く
なっている。そのため、組立て,選別,出荷等の際に
は、キャリアと呼ばれるプラスチック性の枠に固定して
TPCを取り扱いする必要があった。
2. Description of the Related Art Conventionally, a semiconductor integrated circuit device using a TAB tape (especially Tape Carrier Pack)
Since a tape is used in "age" (hereinafter referred to as TPC), the strength of bending, twisting, etc. is weakened as it is. Therefore, at the time of assembly, selection, shipping, etc., it is necessary to fix the TPC to a plastic frame called a carrier and handle the TPC.

【0003】[0003]

【発明が解決しようとする課題】従来のTPCでは、T
ABテープの強度が弱いため、そのま組立て,選別,出
荷の作業を行うと、パッケージ変形,リード曲り等の不
具合が起り、半導体集積回路装置の品質が損なわれると
いう問題点があった。
In the conventional TPC, the T
Since the strength of the AB tape is weak, problems such as package deformation and lead bending occur when the assembling, sorting, and shipping operations are performed, and the quality of the semiconductor integrated circuit device is impaired.

【0004】また、この問題点を解決するためにキャリ
アに固定して取り扱いする方法が標準的であるが、キャ
リアにコストがかかること並びにTABテープをキャリ
アに固定する工程を要するという欠点があった。
In order to solve this problem, the standard method is to fix it to the carrier and handle it, but it has the drawback that the carrier is expensive and a step of fixing the TAB tape to the carrier is required. .

【0005】本発明の目的は、パッケージの変形やリー
ド曲り等の不具合がなく、キャリアが必要なくTABテ
ープをキャリアに固定する工程の必要がない半導体集積
回路装置を提供することにある。
An object of the present invention is to provide a semiconductor integrated circuit device which does not have a defect such as package deformation or lead bending and does not require a carrier and does not require a step of fixing a TAB tape to the carrier.

【0006】[0006]

【課題を解決するための手段】本発明の半導体集積回路
装置は、アウタリードボンディング用窓と、インナリー
ドボンディング用窓と、位置決め用穴が形成された絶縁
体か又は配線パターンと試験用パッドと絶縁された金属
の基体と、この基体表面に形成された配線パターンと、
試験用パッドと、前記配線パターンの先端部に電気的に
接合された半導体チップとを有することを特徴とする。
A semiconductor integrated circuit device according to the present invention includes an outer lead bonding window, an inner lead bonding window, an insulator having a positioning hole, or a wiring pattern and a test pad. An insulated metal base and a wiring pattern formed on the surface of the base,
It is characterized in that it has a test pad and a semiconductor chip electrically joined to the tip of the wiring pattern.

【0007】[0007]

【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0008】図1は本発明の第1の実施の形態の半導体
集積回路装置の平面図である。本発明の第1の実施の形
態の半導体集積回路装置は、図1に示すように、まず、
セラミックスやガラスエポキシ樹脂等の絶縁体1にOL
B(アウタリードボンディング)用窓2,ILB(イン
ナリードボンディング)用窓3及びICソケットとの位
置決め穴4をプレス等の方法にて設ける。次に、絶縁体
1の表面に接着剤を介して配線パターン5と試験用パッ
ド6を銅箔等をエッチングして形成する。次に、配線パ
ターン5の先端部と半導体チップを電気的に接続し、半
導体チップをポッティング樹脂8にて封止する。
FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention. The semiconductor integrated circuit device according to the first embodiment of the present invention, as shown in FIG.
OL for insulator 1 such as ceramics or glass epoxy resin
A B (outer lead bonding) window 2, an ILB (inner lead bonding) window 3, and a positioning hole 4 for the IC socket are provided by a method such as pressing. Next, the wiring pattern 5 and the test pad 6 are formed on the surface of the insulator 1 with an adhesive agent by etching a copper foil or the like. Next, the tip of the wiring pattern 5 and the semiconductor chip are electrically connected, and the semiconductor chip is sealed with potting resin 8.

【0009】半導体集積回路装置をこのように構成する
ことにより、絶縁体1による曲げ,ねじれ等の強度が大
幅に向上し、組立て,出荷,選別工程でのキャリアが不
要になり、安価に半導体集積回路装置を提供することが
できる。また、絶縁体1を使用しているので、リードフ
レームのように連続して構成でき、かつキャリアが不要
なので製造工程において作業の効率化を図ることが可能
となる。
By configuring the semiconductor integrated circuit device in this way, the strength of bending and twisting due to the insulator 1 is greatly improved, the carrier is not required in the assembly, shipping, and sorting steps, and the semiconductor integrated circuit is inexpensively manufactured. A circuit device can be provided. Further, since the insulator 1 is used, the structure can be continuously formed like a lead frame, and since a carrier is not required, it is possible to improve work efficiency in the manufacturing process.

【0010】図2は本発明の第2の実施の形態の半導体
集積回路装置の平面図である。本発明の第2の実施の形
態の半導体集積回路装置は、図2に示すように、図1に
示す第1の実施の形態の半導体集積回路装置の絶縁体1
の代りに銅のような熱伝導性の良い金属9を用い絶縁性
の接着剤を介して絶縁パターン5と試験用パッド6を銅
箔等をエッチングして形成する。
FIG. 2 is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention. The semiconductor integrated circuit device according to the second embodiment of the present invention is, as shown in FIG. 2, an insulator 1 of the semiconductor integrated circuit device according to the first embodiment shown in FIG.
Instead of the above, a metal 9 having a good thermal conductivity such as copper is used, and the insulating pattern 5 and the test pad 6 are formed by etching a copper foil or the like through an insulating adhesive.

【0011】半導体集積回路装置をこのように構成する
ことにより、熱伝導の良い金属9による曲げ,ねじれ等
の強度が大幅に向上するとともに半導体チップ7が発生
する熱をより効率良く実装基板,空中へと拡散させるこ
とが可能となる。
By constructing the semiconductor integrated circuit device in this way, the strength of bending, twisting and the like due to the metal 9 having good thermal conductivity is greatly improved, and the heat generated by the semiconductor chip 7 is more efficiently carried out on the mounting substrate and the air. It becomes possible to spread to.

【0012】[0012]

【発明の効果】以上説明したように本発明は、TCPの
TABテープの代りに絶縁体又は絶縁処理した伝導体を
用いてOLB用窓,ILB用窓を設け、金属の配線パタ
ーンの先端に半導体チップを接続することにより、従来
TABテープでは必要であったキャリアが不要となり、
またキャリアに固定する製造工程を削除することができ
るので、大幅なコストの低減が可能となる。
As described above, according to the present invention, an OLB window and an ILB window are provided by using an insulator or a conductor treated with an insulation instead of the TCP TAB tape, and the semiconductor is provided at the tip of the metal wiring pattern. By connecting the chips, the carrier that was necessary in the conventional TAB tape becomes unnecessary,
Further, since the manufacturing process for fixing to the carrier can be omitted, it is possible to significantly reduce the cost.

【0013】また、リードフレームのように数個にわた
って連結できるので製造効率を向上させることが可能と
なる。
Further, since a plurality of lead frames can be connected, the manufacturing efficiency can be improved.

【0014】さらに、熱伝導性の良好な金属を用いるこ
とにより、放熱効果の優れた半導体集積回路装置を提供
できるという効果がある。
Further, by using a metal having a good thermal conductivity, it is possible to provide a semiconductor integrated circuit device having an excellent heat dissipation effect.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態の半導体集積回路装
置の平面図である。
FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

【図2】本発明の第2の実施の形態の半導体集積回路装
置の平面図である。
FIG. 2 is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

【図3】従来の半導体集積回路装置の一例の平面図であ
る。
FIG. 3 is a plan view of an example of a conventional semiconductor integrated circuit device.

【符号の説明】[Explanation of symbols]

1 絶縁体 2 OLB用窓 3 ILB用窓 4 位置決め穴 5 配線パターン 6 試験用パッド 7 半導体チップ 8 ポッティング樹脂 9 熱伝導の良い金属 10 TABテープ 11 キャリア 1 Insulator 2 Window for OLB 3 Window for ILB 4 Positioning Hole 5 Wiring Pattern 6 Test Pad 7 Semiconductor Chip 8 Potting Resin 9 Metal with Good Thermal Conductivity 10 TAB Tape 11 Carrier

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 アウタリードボンディング用窓と、イン
ナリードボンディング用窓と、位置決め用穴が形成され
た基体と、この基体表面に形成された配線パターンと、
試験用パッドと、前記配線パターンの先端部に電気的に
接合された半導体チップとを有することを特徴とする半
導体集積回路装置。
1. An outer lead bonding window, an inner lead bonding window, a base body having positioning holes, and a wiring pattern formed on the surface of the base body.
A semiconductor integrated circuit device comprising: a test pad; and a semiconductor chip electrically bonded to a tip portion of the wiring pattern.
【請求項2】 前記基体が絶縁体であることを特徴とす
る請求項1記載の半導体集積回路装置。
2. The semiconductor integrated circuit device according to claim 1, wherein the base is an insulator.
【請求項3】 前記基体が配線パターンと試験用パッド
と絶縁された金属であることを特徴とする請求項1記載
の半導体集積回路装置。
3. The semiconductor integrated circuit device according to claim 1, wherein the substrate is a metal that is insulated from the wiring pattern and the test pad.
JP7305356A 1995-11-24 1995-11-24 Semiconductor integrated circuit device Pending JPH09148367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7305356A JPH09148367A (en) 1995-11-24 1995-11-24 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7305356A JPH09148367A (en) 1995-11-24 1995-11-24 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH09148367A true JPH09148367A (en) 1997-06-06

Family

ID=17944137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7305356A Pending JPH09148367A (en) 1995-11-24 1995-11-24 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH09148367A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214631A (en) * 1986-03-14 1987-09-21 Sanyo Electric Co Ltd Hybrid integrated circuit
JPH02172245A (en) * 1988-12-26 1990-07-03 Hitachi Ltd Semiconductor device
JPH04345039A (en) * 1991-05-22 1992-12-01 Toshiba Corp Semiconductor device
JPH0621156A (en) * 1992-07-03 1994-01-28 Nippon Steel Corp Multi-layer film carrier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214631A (en) * 1986-03-14 1987-09-21 Sanyo Electric Co Ltd Hybrid integrated circuit
JPH02172245A (en) * 1988-12-26 1990-07-03 Hitachi Ltd Semiconductor device
JPH04345039A (en) * 1991-05-22 1992-12-01 Toshiba Corp Semiconductor device
JPH0621156A (en) * 1992-07-03 1994-01-28 Nippon Steel Corp Multi-layer film carrier

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Effective date: 19971216