JPH09148564A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain a tunnel between bands and reduce a leak current, when an MOS transistor constituting a semiconductor device is very fined. SOLUTION: In an insulated gate field effect transistor, a gate electrode is constituted of a first gate electrode 3 and a second gate electrode 4 which are electrically continuous. The first electrode 3 exists on a channel part, via an gate insulating film 2. The second gate electrode 4 exists on source.drain regions, via the insulating film 2. The second gate electrode 2 is constituted of a polycrystalline semiconductor film whose conductivity type is opposite to that of the source.drain regions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a gate electrode structure of an insulated gate field effect transistor and a forming method thereof.

[0002]

2. Description of the Related Art Conventional LDD (Lightly Dop)
In an insulated gate field effect transistor (hereinafter referred to as a MOS transistor) having a source / drain having an ed drain structure, the gate is in an off state (MO
Method for preventing leakage current due to formation of a surface inversion layer in a drain region under a gate electrode and a resulting inter-hand tunneling phenomenon of electrons between a valence band and a conduction band, which occurs when an S transistor is in a non-conducting state) As a method of changing the work function of the gate electrode, Japanese Patent Laid-Open No. 1-242626 is known.
No. 4 publication. In this method, the gate electrode that covers the channel region of the MOS transistor through the gate insulating film and the gate electrode that covers the source / drain regions through the gate insulating film are made of different conductive materials. Here, the work functions of these different kinds of conductor materials are selected so as to be different from each other.

The technique disclosed in Japanese Patent Laid-Open No. 1-264264 will be described below with reference to the drawings.
FIG. 6 shows an n-channel M to which such a conventional technique is applied.
It is sectional drawing of an OS transistor.

As shown in FIG. 6, a gate insulating film 102 of a silicon oxide film of about 10 nm is formed on the surface of a silicon substrate 101 having a P conductivity type by a thermal oxidation method. Then, the first gate electrode 103 is formed of tungsten, molybdenum, or the like. Further, the second gate electrode 104 is formed on the side wall of the first gate electrode 103. Here, this second gate electrode 104 is composed of N-type polycrystalline silicon containing phosphorus impurities.

Then, an n ⁻ diffusion region 105 forming a part of the source / drain is formed on the surface of the silicon substrate 101 below the second gate electrode 104 via the gate insulating film 102. Further, the n ⁺ diffusion region 106 is formed to form the source / drain region of the MOS transistor.

Here, for the second gate electrode 104, a conductive material whose work function is smaller than that of the first gate electrode 103 is selected.

In the above case, the first gate electrode 103 whose Fermi level is located in the intermediate region of the band gap of the silicon substrate covers the channel region of the MOS transistor, and the Fermi level is close to the conduction band. Become second
Gate electrode 104 covers the source / drain of the MOS transistor. That is, the work function of the second gate electrode 104 is set to be smaller than that of the first gate electrode 103. By doing so, the amount of band bending (hereinafter referred to as band bending) on the surface of the n ⁻ diffusion region 105 when the gate of the MOS transistor is in the off state is relaxed, and the leak current due to the tunnel between the bands described above is relaxed. Is reduced.

On the other hand, when the MOS transistor is a p-channel type, the conductivity type of the source / drain diffusion regions is P-type, so that the second gate electrode has a conductivity type with respect to the first gate electrode. A conductive material having a large work function such as P-type polycrystalline silicon will be selected.

[0009]

However, when the semiconductor device is highly integrated and becomes a 256 megabit DRAM, for example, the thickness of the gate insulating film of the MOS transistor used is about 6 nm. Then, for example, in the case of an n-channel MOS transistor and the gate is in an off state, that is, 0 V is applied to the gate electrode and 3 V is applied to the drain.
When a voltage of about V is applied, this voltage of 3V is directly applied to the surface of the diffusion region of the source / drain. Then, this voltage easily causes band bending on the surface of the diffusion region, and the tunnel current between the bands increases. This is due to the capacitance and band
This is because when the capacitance due to the gate insulating film becomes larger than the capacitance at the bending portion, the voltage applied by connecting them in series is almost consumed by the band bending due to the capacitance division.

As described above, as the MOS transistor becomes ultra-miniaturized, it becomes difficult to prevent such band-to-band tunnel by the conventional technique.

An object of the present invention is to make it possible to suppress this band-to-band tunnel even when the MOS transistor is extremely miniaturized.

[0012]

For this purpose, in the insulated gate field effect transistor of the semiconductor device of the present invention, the first gate electrode and the second gate electrode whose gate electrodes are electrically connected to each other are provided.
The first gate electrode is present on the channel portion through the gate insulating film, and the second gate electrode
Exists on the source / drain regions via an insulating film, and the second gate electrode is formed of a polycrystalline semiconductor film having a conductivity type opposite to that of the source / drain regions. .

Alternatively, in the semiconductor device of the present invention, there is a third gate electrode which covers the first gate electrode and the second gate electrode and is electrically connected to these gate electrodes.

Here, the polycrystalline semiconductor film is a polycrystalline silicon film or a polycrystalline silicon-germanium film.

The insulating film is a gate insulating film.

The semiconductor device manufacturing method of the present invention is
Forming a gate insulating film on the surface of the semiconductor substrate; forming a polycrystalline silicon film of one conductivity type for covering the gate insulating film; and depositing a protective insulating film on the polycrystalline silicon film. And a step of processing the protective insulating film into a pattern shape of a gate electrode, and using the patterned protective insulating film as a mask, impurities of a reverse conductivity type are selectively introduced into the polycrystalline silicon film to form a reverse conductivity type. A step of converting, a step of processing the polycrystalline silicon film into a pattern shape of the gate electrode using the patterned protective insulating film as an etching mask, and a mask of the patterned protective insulating film and the polycrystalline silicon film Then, impurities of one conductivity type are introduced into the surface of the semiconductor substrate to form source / drain regions, and the polycrystalline silicon film of the opposite conductivity type is formed. Consisting of said source and drain regions to include, a step of overlapping via the gate insulating film.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of an n-channel MOS transistor for explaining the first embodiment of the present invention. As shown in FIG. 1, a gate insulating film 2 is formed on the surface of a silicon substrate 1 having a P conductivity type. Then, the first gate electrode 3 and the second gate electrode 4 are formed on the gate insulating film 2. Here, the first gate electrode 3 is composed of a polycrystalline silicon film containing phosphorus impurities. The second gate electrode is composed of a polycrystalline silicon film containing boron impurities. The phosphorus impurity content is about 10 ¹⁹ atoms / cm ³ and the boron impurity content is about 10 ¹⁸ atoms / cm ³ . Here, arsenic impurities may be used instead of phosphorus impurities.

Then, n ⁺ diffusion regions 5 and 6 serving as the source / drain of the MOS transistor are formed as shown in FIG. That is, n ⁺ diffusion regions 5 and 6 and the gate electrode, that is, second gate electrode 4 overlap each other with gate insulating film 2 interposed therebetween. And
The n ⁺ diffusion regions 5 and 6 are formed so as not to overlap with the first gate electrode 3. here,
The content of arsenic impurities in the n ⁺ diffusion region is 10 ²⁰ atoms / cm
It is set to about ³ . The source / drain diffusion region may have an LDD structure.

Next, a method of manufacturing the structure of the first embodiment will be described with reference to FIG. Here, FIG. 2 is a cross-sectional view in the order of manufacturing steps of the MOS transistor of the first embodiment.

As shown in FIG. 2A, an element isolation region is formed of a field oxide film (not shown) on the surface of a silicon substrate 1 having a conductivity type of P, and an active region of the silicon substrate 1 is formed. The gate insulating film 2 is provided on the surface. Here, the gate insulating film 2 is a SiON insulating film formed by thermally nitriding a silicon oxide film having a film thickness of about 6 nm formed by a known thermal oxidation method. Alternatively, the gate insulating film 2 is a SiON insulating film formed by thermal oxidation in an atmosphere gas containing nitrogen such as nitrous oxide.

Next, an N-type polycrystalline silicon film 3'covering the gate insulating film 2 is deposited by a known chemical vapor deposition (CVD) method. Here, the film thickness of the N-type polycrystalline silicon film 3'is set to about 200 nm. Further, phosphorus impurities are contained in the N-type polycrystalline silicon film 3 ′ at a concentration of about 1 × 10 ¹⁹ atoms / cm ³ .

Next, a protective insulating film 7 having a pattern of the gate electrode of the MOS transistor is provided on the surface of the N-type polycrystalline silicon film 3 '. Here, this protective insulating film 7 is a silicon oxide film formed by a CVD method, and its film thickness is set to about 300 nm. The pattern size is the size of the gate electrode and is 0.3
It is set to about μm.

Next, as shown in FIG. 2B, a sidewall insulating film 8 is formed on the sidewall of the protective insulating film 7. Here, the side wall insulating film 8 has a film thickness of 100 nm.
It is composed of a silicon nitride film. The sidewall insulating film 8 is first formed by a CVD method to a film thickness of 120 n.
A silicon nitride film of about m is deposited, and then the silicon nitride film is entirely etched by anisotropic reactive ion etching (RIE).

Next, as shown in FIG. 2 (c), boron ions 9 are ion-implanted. Here, this boron ion 9 is obliquely ion-implanted, and its inclination angle is set to about 45 degrees. The ion implantation energy is 50 to 100 keV, and the dose is 3 × 10 ¹⁴ ions /
Each is set to about cm ² . The range of boron ions in this ion implantation is about 200 nm, and the ions reach the vicinity of the gate insulating film 2. And
Further heat treatment is applied. In this way, the P-type polycrystalline silicon film 4'is formed.

In the P-type polycrystalline silicon film 4 ', the phosphorus impurity of 1 × 10 ¹⁹ atoms / cm ^{3 and} the concentration of 1.5 × 1 are added.
Boron impurities of 0 ¹⁹ atoms / cm ³ are mixed and apparently 5 × 10 ¹⁸ atoms / cm ³ of P-type impurities are contained.

Next, the sidewall insulating film 8 is selectively removed by etching. This etching is performed with a chemical solution such as hot phosphoric acid. Then, using the protective insulating film 7 as an etching mask, the N-type polycrystalline silicon film 3 ′ and the P-type polycrystalline silicon film 4 ′ described above are dry-etched by RIE.

Thus, as shown in FIG. 2D, the first gate electrode 3 is formed in the region of the N-type polycrystalline silicon film 3'described above, and the P-type polycrystalline silicon film 4'is formed. The second gate electrode 4 is formed in the region.

Next, arsenic impurities are ion-implanted and heat-treated on the entire surface to form n ⁺ diffusion regions 5 and 6. Here, n ⁺ diffusion regions 5 and 6 overlap with second gate electrode 4 via gate insulating film 2.

Finally, the protective insulating film 7 is removed to complete the MOS transistor having the structure of the present invention described with reference to FIG.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view of an n-channel MOS transistor similar to that described in the first embodiment.

As shown in FIG. 3, a gate insulating film 2 is formed on the surface of a silicon substrate 1 whose conductivity type is P type. Then, the first gate electrode 3 and the second gate electrode 4 are formed on the gate insulating film 2. Here, the first gate electrode 3 is composed of a polycrystalline silicon film containing phosphorus impurities. The second gate electrode is composed of a polycrystalline silicon film containing boron impurities. Then, in this case, the second gate electrode 4 is formed along the side wall of the first gate electrode 3. The content of the phosphorus impurity is about 102 ⁰ atoms / cm ^3, the content of boric impurities is about 10 ¹⁸ atoms / cm ^3.

Then, a third gate electrode 10 electrically connected to the first gate electrode 3 and the second gate electrode 4 is formed. Here, the third gate electrode 10 is formed of a refractory metal silicide film such as tungsten silicide or titanium silicide.

Then, n ⁺ diffusion regions 5 and 6 serving as the source and drain of the MOS transistor are formed as described in the first embodiment. That is, n ⁺
The diffusion regions 5 and 6 and the gate electrode, that is, the second gate electrode 4 overlap each other with the gate insulating film 2 interposed therebetween. The n ⁺ diffusion regions 5 and 6 are
Is formed so as not to overlap the gate electrode 3 of. Here, the content of arsenic impurities in the n ⁺ diffusion region is set to about 10 ²⁰ atoms / cm ³ .

Next, a method of manufacturing the structure of the second embodiment will be described with reference to FIG. Here, FIG. 4 is a sectional view of the MOS transistor of the first embodiment in the order of manufacturing steps.

As shown in FIG. 4A, in the same manner as described in the first embodiment, an element isolation region is formed of a field oxide film on the surface of the P type silicon substrate 1, The gate insulating film 2 is provided on the surface of the silicon substrate 1 which becomes the active region. Here, the gate insulating film 2 is a SiON insulating film having a film thickness of about 6 nm.

Next, an N-type polycrystalline silicon film 3'covering the gate insulating film 2 is deposited by the CVD method. Here, the film thickness of the N-type polycrystalline silicon film 3'is set to about 150 nm. Further, phosphorus impurities are contained in the N-type polycrystalline silicon film 3 ′ at a concentration of about 1 × 10 ²⁰ atoms / cm ³ .

Next, on the surface of the N-type polycrystalline silicon film 3 ', a third gate electrode 10 having a pattern shape of the gate electrode of the MOS transistor and a protective insulating film 7 are laminated and provided. Here, the third gate electrode 10 is a titanium silicide layer, and the protective insulating film 7 is a silicon oxide film formed by the CVD method. The thickness of the third gate electrode 10 is set to 150 nm, and the thickness of the protective insulating film is set to about 300 nm. Also,
The pattern size is set to about 0.3 μm.

Next, boron difluoride ions 11 are ion-implanted to form a boron impurity-implanted layer 12. Here, the implantation energy of this ion implantation is 50 keV, and the dose amount is 2 × 10 ¹⁵ ions / cm ² .
Then, heat treatment at a temperature of about 800 ° C. is performed, and FIG.
A P-type polycrystalline silicon film 4'as shown in (b) is formed. In this case, the size of the region where the P-type polycrystalline silicon film 4 ′ and the third gate electrode 10 overlap is 0.1 μm. Further, the apparent amount of boron impurities after the phosphorus impurities and the boron impurities are mixed is 5 × 10 5.
It is set to be ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 4C, the P-type polycrystalline silicon film 4'is dry-etched by RIE using the protective insulating film 7 and the third gate electrode 10 as an etching mask. In this way, the first gate electrode 3 is formed in the region of the N-type polycrystalline silicon film 3 ′ and the second gate electrode 4 is formed in the region of the P-type polycrystalline silicon film 4 ′. become.

Next, arsenic impurities are ion-implanted over the entire surface and heat-treated to form n ⁺ diffusion regions 5 and 6. Finally, the protective insulating film 7 is removed to complete the MOS transistor having the structure of the present invention described with reference to FIG.

Next, the effect of the present invention will be described in detail with reference to FIG. FIG. 5A is a cross-sectional view of an enlarged MOS transistor of the present invention, and FIG.
Shows the energy band structure between A and B shown in FIG. Note that FIG. 5C shows the same energy band structure as in the case of the conventional MOS transistor.

As shown in FIG. 5A, the gate insulating film 2, the first gate electrode 3, the second gate electrode 4, n of the n-channel MOS transistor are formed on the surface of the silicon substrate 1 whose conductivity type is P type. ⁺ Diffusion regions 5 and 6 are formed. Here, the n ⁺ diffusion region 5 becomes a source region and the n ⁺ diffusion region 6 becomes a drain region.

Here, the first gate electrode 3 and the second gate electrode 4, the n ⁺ diffusion region 5, and the silicon substrate 1 of such a MOS transistor are set to the ground potential, and the n ⁺ diffusion region 6 has a voltage of about 3V. The case where a positive voltage is applied will be described. This is the OFF state of the MOS transistor described above.

When a voltage is applied to the MOS transistor as described above, a voltage of 3 is applied between the first and second gate electrodes 3 and 4 and the n ⁺ diffusion region 6 which is a drain region.
A voltage of about V will be applied. Therefore, the depletion region 4a comes to be formed in the second gate electrode 4 made of P-type polycrystalline silicon. Further, the PN junction formed between the first gate electrode 3 made of N-type polycrystalline silicon and the second gate electrode 4 is applied in the forward direction. In this way, most of the voltage between the first gate electrode 3 and the n ⁺ diffusion region 6 is applied to the depletion region 4a.

This state will be described with reference to FIG. FIG.
As shown in (b), in the energy band 24 of the second gate electrode 4, the electron energy decreases in the depletion region 4a and becomes the energy band 24a. Then, the energy band 22 of the gate insulating film 2 slightly lowers to the right. Then, n ⁺ energy band 26a slight right edge of the n ⁺ diffusion region 6 surface by the band bending on the surface of the diffusion region 6 is formed. Then, the energy band 26 of the n ⁺ diffusion region 6 and the energy band 21 of the silicon substrate 1 having high electron energy are formed.

As described above, the gate insulating film 2 is thinned as the MOS transistor is miniaturized, and the impurity concentration in the n ⁺ diffusion region 6 is increased. Then, the gate insulating film 2
And the capacitance formed in the band-bent region increases. Therefore, the depletion region 4a
Since the capacitance formed in the capacitor is relatively small, when these are connected in series, a voltage drop occurs in the depletion region 4a. Then, the bending of the energy band 24a in the depletion region becomes large, and the band bending amount becomes small.

As described above, according to the present invention, the band bending amount is reduced and the band-to-band tunneling phenomenon of electrons is prevented.

On the other hand, for comparison, in the case of the conventional technique
Will be described with reference to FIG. In this case, the gate electrode
Since the depletion region as in the present invention is not formed,
There is no bend in the polar energy band 24. For this,
As shown in FIG. 5C, n⁺ Energy of surface of diffusion area 6
The change of the band 26a becomes large. I.e. the band
・ The amount of bending will increase. And this
From electron conduction band to valence band in band bending section
The band-to-band tunneling phenomenon becomes remarkable.

In the above embodiments, the n-channel MOS is used.
Although the case of a transistor has been described, it should be noted that a p-channel MOS transistor can be similarly formed by reversing its conductivity type.

Further, a polycrystalline silicon film is used as the first gate electrode material of the MOS transistor,
Besides, a refractory metal or a silicide film thereof can be similarly formed. Further, a polycrystalline silicon-germanium film may be used as the second gate electrode material.

In the MOS transistor of the present invention,
The second gate electrode and the source / drain region may overlap with each other via the gate insulating film, or may overlap with each other via an insulating film having a film thickness thicker than other gate insulating films.

Here, the second gate electrode and the channel region are formed so as not to overlap with each other. This is because such an overlap causes the threshold voltage of the MOS transistor to increase and deviate from the set value.

[0053]

According to the semiconductor device of the present invention, in the insulated gate field effect transistor, the gate electrode is composed of a first gate electrode and a second gate electrode which are electrically connected to each other, and the first gate electrode is The second gate electrode exists on the source / drain region via an insulating film, and the second gate electrode exists on the channel region via the gate insulating film;
Is formed of a polycrystalline semiconductor film having a conductivity type opposite to that of the source / drain regions.

Here, when a voltage is applied between the gate electrode and the drain region so that the insulated gate field effect transistor is turned off, a depletion region is formed in the second gate electrode, and the above-mentioned depletion region is formed in the depletion region. Most of the voltage will be applied.

Therefore, as described above, the band-to-band tunnel phenomenon due to band bending in the drain region is eliminated. Then, the leak current in the drain region is significantly reduced.

Thus, miniaturization of the insulated gate field effect transistor and high density or high integration of the semiconductor device are facilitated.

[Brief description of the drawings]

FIG. 1 is a MOSF illustrating a first embodiment of the present invention.
It is sectional drawing of ET.

FIG. 2 is a cross-sectional view of the MOSFET in the order of manufacturing steps.

FIG. 3 is a MOSF illustrating a second embodiment of the present invention.
It is sectional drawing of ET.

4A to 4C are cross-sectional views in the manufacturing process order of the MOSFET.

FIG. 5 is a cross-sectional view and a band diagram for explaining the effect of the present invention.

FIG. 6 is a sectional view of a MOSFET for explaining a conventional technique.

[Explanation of symbols]

1, 101 Silicon substrate 2, 102 Gate insulating film 3, 103 First gate electrode 3 ′ N-type polycrystalline silicon film 4, 104 Second gate electrode 4a Depletion region 4 ′ P-type polycrystalline silicon film 5, 6, 106 n ⁺ diffusion region 7 protective insulating film 8 sidewall insulating film 9, boron ions 10 third gate electrode 11 boron difluoride ions 12 boron impurity implantation layer 21,22,24,24a, 26,26a energy band 105 n ^- Diffusion area

Claims (5)

[Claims] 1. In an insulated gate field effect transistor, a gate electrode is composed of a first gate electrode and a second gate electrode which are electrically connected to each other, and the first gate electrode is a channel via a gate insulating film. And the second gate electrode is present on the source / drain region via an insulating film, and the second gate electrode has a conductivity opposite to the conductivity type of the source / drain region. 1. A semiconductor device characterized by being formed of a polycrystalline semiconductor film of the type. 2. The semiconductor device according to claim 1, wherein there is a third gate electrode which covers the first gate electrode and the second gate electrode and is electrically connected to these gate electrodes. 3. The semiconductor device according to claim 1, wherein the polycrystalline semiconductor film is a polycrystalline silicon film or a polycrystalline silicon-germanium film. 4. The semiconductor device according to claim 1, wherein the insulating film is a gate insulating film. 5. A step of forming a gate insulating film on a surface of a semiconductor substrate, a step of forming a polycrystalline silicon film of one conductivity type for covering the gate insulating film, and a protective insulating film on the polycrystalline silicon film. And a step of processing the protective insulating film into a pattern shape of a gate electrode, and using the patterned protective insulating film as a mask to selectively introduce impurities of opposite conductivity type into the polycrystalline silicon film. A step of converting to a reverse conductivity type, and a step of processing the polycrystalline silicon film into the pattern shape of the gate electrode using the patterned protective insulating film as an etching mask,
Using the patterned protective insulating film and the polycrystalline silicon film as a mask, impurities of one conductivity type are introduced into the surface of the semiconductor substrate to form source / drain regions, and the polycrystalline silicon film of the opposite conductivity type and the source are also formed. And a step of overlapping the drain region with the gate insulating film interposed therebetween, a method of manufacturing a semiconductor device.