JPH09148573A - Semiconductor integrated circuit - Google Patents

Abstract

Kind Code: A1 In a pair MOS transistor, variations in gate electrode length due to variations in exposure and etching in a photolithographic process are improved. SOLUTION: Two wirings G ₃ and G ₄ made of a gate electrode material are provided for paired MOS transistors M ₁ and M ₂ .
So as to sandwich the gate electrode G _10, G ₂₀ pair MOS transistors, arranged in parallel to the gate electrode G _10, G _20. When the layout of the circuit around the pair MOS transistor is asymmetric, the asymmetry of the optical and hydrodynamic conditions at the time of forming the gate electrode of the pair MOS transistor is blocked. When the two wirings G ₃ and G ₄ are arranged in the diffusion layer regions 1L and 2R on both sides of the pair MOS transistors M ₁ and M ₂ to form MOS transistors, the polysilicon wirings G ₃ and G 4 are formed. _Since the base state of _{No. 4 is the same as} the base state of the pair MOS transistors M ₁ and M ₂ , the effect is larger.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a circuit such as a differential amplifier circuit or a current mirror circuit which requires a transistor pair.
The present invention relates to the layout of the gate electrode when it is realized by using a positive field effect transistor.

[0002]

2. Description of the Related Art A current mirror circuit or a differential amplifier circuit of which an example is shown in FIG. 2 when a circuit is formed using a MOS field effect transistor (hereinafter referred to as a MOS transistor) on a semiconductor substrate. Paired MOS transistors are often used in circuits that require transistor pairs such as. As an example of the layout of such a pair MOS transistor, the layout of the n-channel type MOS transistors M ₁ and M _{2 in} the differential amplifier circuit shown in FIG.
As shown in FIG.

Referring to FIG. 3, these MOS transistors are so-called silicon gate MOS transistors. A part of the polysilicon wiring G ₁₀ serves as the gate electrode of the transistor M ₁ . Similarly, the polysilicon wiring G
A part of ₂₀ is the gate electrode of the transistor M ₂ . These two polysilicon wirings G ₁₀ and G ₂₀ are both bent in a U shape, and each of the transistors M ₁ and M ₂₀ is bent.
_{The two} gate electrodes are arranged in parallel. That is, the polysilicon wiring G ₁₀ and the polysilicon wiring G ₂₀ have a symmetrical layout with respect to the gate electrode portion. On both sides of each gate electrode, an n ⁺ diffusion layer region 1 is formed to serve as a source region or a drain region of each transistor. Each diffusion layer region 1 is connected to the aluminum wiring 3, 3 through the contact hole 6.
It is connected to 4,5. In the case of FIG. 3, the aluminum wiring 3 is a wiring that connects the source electrodes of the transistors M ₁ and M ₂ in FIG. 2 to the constant current source I. On the other hand, the aluminum wiring 4 is a wiring that connects the drain electrode of the transistor M ₁ to the resistor R ₁ . The aluminum wiring 5 is a wiring that connects the drain electrode of the transistor M ₂ to the resistor R ₂ .

[0004]

In the conventional layout pair MOS transistor described above, the transistor M ₁
And an electrical characteristic of the transistor M ₂ are likely to be unbalanced. This is a photolithographic process during manufacturing, and the dimension (hereinafter, gate) in the channel length direction of the transistors M ₁ and M ₂ (in this case, the left-right direction in FIG. 4) between the polysilicon wirings G ₁₀ and G ₂₀ . This is because there is a difference in the electrode length).

That is, in the semiconductor integrated circuit, various signal processing circuits are formed on the same substrate in addition to the differential amplifier circuit using the paired MOS transistors M ₁ and M ₂ . Therefore, although only the paired MOS transistors M ₁ and M ₂ are shown in FIG. 4, many other circuits exist around these paired MOS transistors. However, the circuits arranged around such paired MOS transistors are not always symmetrically arranged with the paired MOS transistors M ₁ and M ₂ interposed therebetween. In other words, before the gate electrode formation step, the optical state and hydrodynamic state around the pair MOS transistors M ₁ and M ₂ such as the three-dimensional unevenness of the substrate and the surface roughness are compared with the pair MOS. The transistors are not always symmetrical with respect to each other. As a result, in the gate electrode formation step, the polysilicon wirings G _1L and G _{2R on} both outermost sides of the pair MOS transistor are affected by the asymmetry of their adjacent regions, which causes a difference in gate electrode length. When the resist is exposed, the degree of light interference varies from place to place, and at the time of development, there is a difference in the supply amount of the developing solution or the amount of the resist dissolved in the development that leaves the spot. This is because the dimensions vary from place to place. Furthermore, during etching, a difference in the supply amount of the etchant gas or a difference in the discharge amount of the gas decomposed by the etching occurs, which causes a difference in the etching amount at each place.

Such variations in the size of the gate electrode of each transistor cause a difference in the electrical characteristics of the paired MOS transistors M ₁ and M ₂ . As a result, an offset occurs in the differential amplifier circuit using the paired MOS transistors, and the precision of the mirror ratio deteriorates in the current mirror circuit.

Therefore, according to the present invention, in a semiconductor integrated circuit having a pair MOS transistor, it is possible to improve the variation in the size of the gate electrode during exposure and etching in the photolithographic process and to improve the relative accuracy of the electrical characteristics of the pair MOS transistor. The purpose is.

[0008]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit including a transistor pair composed of two MOS field effect transistors in which respective gate electrodes are arranged in parallel with each other.
Two wirings made of the same gate electrode material as the gate electrode material of the OS type field effect transistor are arranged in parallel to the gate electrodes of the two MOS type field effect transistors so as to sandwich the gate electrode pair within the transistor pair. It is characterized by having done. As a result, when the layout of the circuit arranged around the transistor pair is asymmetric, the asymmetrical optical and hydrodynamic effects that the asymmetry has on the inside of the region of the transistor pair when the gate electrode is formed are blocked. Therefore, there is no variation in the gate electrode length.

According to the semiconductor integrated circuit of the present invention, in the above semiconductor integrated circuit, two wirings made of a gate electrode material are arranged in the diffusion layer regions on both sides of the transistor pair to form a MOS field effect transistor. It is characterized by being formed. As a result, the underlying state of the newly provided gate electrode wiring becomes the same as the underlying state of the original MOS field effect transistor forming the transistor pair, so that the variation in the gate electrode length in the photolithographic process is further reduced.

According to the semiconductor integrated circuit of the present invention, in the above semiconductor integrated circuit, a wiring made of a gate electrode material is connected to a potential point at which a MOS field effect transistor having the wiring as a gate electrode is in a cutoff state. It is characterized by When the gate electrode is left in a floating state, it may be electrically affected by other circuits on the same substrate and the conduction state may become unstable. However, in the present invention, since the gate potential is fixed, The operation of this MOS field effect transistor is stable. In addition, since the gate potential and the source potential are set to the same potential to cut off the transistor, it is not necessary to consider this transistor when designing the circuit.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a layout diagram of a pair MOS transistor according to an embodiment of the present invention. Referring to FIG. 1, the original pair MOS transistors M _1, that one by one new MOS transistors on both sides of the M ₂ M _3, M ₄ is provided with a conventional pair MOS transistor shown in FIG. 2 Is different. These MOS
The gate electrodes G ₃ and G ₄ of the transistors M ₃ and M ₄ are parallel to the gate electrodes G ₁₀ and G ₂₀ of the original pair MOS transistors M ₁ and M ₂ and are also the gate electrodes G ₁₀ and G 4.
It is arranged so as to sandwich ₂₀ . That is, the gate electrode G ₃ of the transistor M ₃ are, the more left outside the gate electrode G _1L of the gate electrode G ₁₀ of the transistor M _1, are arranged in parallel. Similarly, the gate electrode G ₄ of the transistor M ₄ is a further right outside the gate electrode G _2R of the gate electrode G ₂₀ of the transistor M _2, are arranged in parallel. These gate electrodes G ₃ and G ₄ are made of a polysilicon layer, and at the same time when the gate electrodes G ₁₀ and G ₂₀ are formed, a resist pattern is formed and etched.

[0012] polysilicon wiring for the gate electrode G ₃ of the transistor M ₃ are, through a contact hole connected to the aluminum wiring 7, and further connected to the n ⁺ diffusion layer regions 1L via the contact hole 6. The aluminum wiring 7 is normally connected to the lowest potential point V _SS (not shown) in the circuit. That is, the transistor M ₃ is a transistor in which the gate electrode and the source electrode are equalized to the lowest potential in the circuit and are in the cutoff state. Similarly, the polysilicon wiring for the gate electrode G ₄ of the transistor M ₄ is connected to the aluminum wiring 8 via the contact hole and further connected to the n ⁺ diffusion layer region 1R via the contact hole 6. The aluminum wiring 8 is connected to the lowest potential point V _SS in the circuit. Therefore, the transistor M ₄ is a transistor in the cutoff state in which the gate electrode and the source electrode are equalized to the lowest potential in the circuit.

As described above, the silicon gate MOS transistors M ₃ and M ₄ are further outside the pair MOS transistors M ₁ and M ₂ , the gate electrode G ₃ is parallel to the gate electrode G _1L , and the gate electrode G ₄ is the gate. By arranging so as to be parallel to the electrode G _2R , the polysilicon lines G ₁₀ and G ₂₀ for the gate electrodes of the pair MOS transistors M ₁ and M ₂ are always adjacent and parallel to both sides. There will be silicon wiring. Therefore, even if the concavo-convex state and the surface state around the pair MOS transistor are asymmetric, the gate electrodes G _1L and G _2R outside the original transistors M ₁ and M ₂ are not directly affected by the asymmetry. , No. Therefore, when forming the gate electrode, there is no difference between forming the resist pattern and etching for each part of the gate electrode.

In this embodiment, the original pair M
Although the silicon gate MOS transistors M ₃ and M ₄ are formed on both sides of the OS transistors M ₁ and M ₂ , they are not always required to be transistors according to the above description.
Obviously, it may be simply polysilicon wiring. However, when the gate electrode length of the MOS transistor is very small on the order of submicrons, there are subtle differences such as the unevenness around the gate electrode and the surface condition of the base on which the gate electrode is formed. It has a great influence on the etching amount, and the final MOS
The channel length of the transistor, in other words, the transistor characteristics are greatly varied. From this point of view, the polysilicon wirings G ₃ and G ₄ provided outside the gate electrodes G _1L and G _2R outside the original pair MOS transistors M ₁ and M ₂ are considered.
It is desirable that the underlying and peripheral states of the transistor are the same as the underlying and peripheral states of the transistors M ₁ and M ₂ , that is, the diffusion layer region is provided to form a transistor structure. In that case, if the gate electrode is left in a floating state, it may be electrically affected by other circuits on the same substrate and the conduction may become unstable. Therefore, it is better to fix the gate potential. good. If the gate potential and the source potential are set to the same potential, this MOS transistor will be in a cut-off state, which is convenient because there is no need to consider this transistor in the circuit design.

[0015]

As described above, in the semiconductor integrated circuit of the present invention, two wires made of the gate electrode material are sandwiched between the gate electrode pair of the pair MOS transistor in the semiconductor integrated circuit including the pair MOS transistor. In parallel with the gate electrodes of the pair MOS transistors,
It is arranged. As a result, according to the present invention, in the original paired MOS transistor, the optical and hydrodynamic influences received from the peripheral circuits at the time of forming the gate electrodes are equal in all the gate electrodes, so that the variation in the gate electrode length is reduced. Disappear.

In the semiconductor integrated circuit of the present invention, the two wirings made of the above-mentioned gate electrode material have the original pair MO.
The MOS field effect transistors are formed in the diffusion layer regions on both sides of the S transistor, respectively.
As a result, according to the present invention, the ground state of the newly provided gate electrode wiring becomes equivalent to the ground state of the original pair MOS transistor, so that the variation of the gate electrode length in the photolithographic process is further reduced.

In the semiconductor integrated circuit of the present invention, in addition to the semiconductor integrated circuit described above, a wiring made of a gate electrode material is connected to a potential point at which a MOS transistor having the wiring as a gate electrode is in a cutoff state. doing. As a result, according to the present invention, the newly provided MOS transistor for uniformizing the gate electrode size becomes a transistor in a cutoff state in which the gate potential is fixed, so that it does not disturb the operation of the circuit. It is not necessary to take this transistor into consideration when designing the circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout of a pair MOS transistor used in a semiconductor integrated circuit according to an embodiment of the present invention, and a circuit diagram of a differential amplifier circuit using the same.

FIG. 2 is a circuit diagram of an example of a differential amplifier circuit.

FIG. 3 is a diagram showing an example of a layout conventionally used for a pair MOS transistor used in the circuit shown in FIG.

[Explanation of symbols]

1, 1L, 1R n ⁺ Diffusion layer region 3, 4, 5, 7, 8 Aluminum wiring M ₁ , M ₂ , M ₃ , M ₄ MOS transistor G ₁₀ , G ₂₀ , G _1L , G _2R , G ₃ , G ₄ Polysilicon wiring R ₁ , R ₂ resistance I Constant current source

Claims (4)

[Claims] 1. A semiconductor integrated circuit including a transistor pair composed of two MOS field effect transistors in which respective gate electrodes are arranged in parallel with each other, wherein the same gate electrode material as that of the two MOS field effect transistors is used. A semiconductor integrated circuit, wherein two wirings made of an electrode material are arranged in parallel with the gate electrodes of the two MOS field effect transistors so as to sandwich the gate electrode pair in the transistor pair. 2. The semiconductor integrated circuit according to claim 1, wherein the two wirings made of the gate electrode material are provided in diffusion layer regions on both sides of the transistor pair to form MOS field effect transistors. A semiconductor integrated circuit characterized in that. 3. The semiconductor integrated circuit according to claim 2, wherein the wiring made of the gate electrode material is connected to a potential point at which the MOS type field effect transistor having the wiring as a gate electrode is in a cutoff state. And a semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 1, claim 2, or claim 3, wherein the gate electrode material is polycrystalline silicon.