JPH09149043A - Contention multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the wait time from occurrence of a transmission request till actual transmission. SOLUTION: Each buffer section 10 (N) stores fixed length data 17 (N) sent from a corresponding terminal T (N) and sends the data according to a scheduled transmission time by a scheduler 12. Furthermore, each buffer section 10 (N) stores one set of fixed length data 17 (N) or over, then sets a transmission request signal 14 (N) to be active. When the plural signals 14 (N) are simultaneously active, an encoder 11 selects any of them according to prescribed priority and selects it when the signal 14 (N) of any of them is set active. The shceduler reserves a transmission time of the buffer section 10(N) every time the signal 14 (N) is selected. The reservation is made in such a way that the transmission interval of the fixed length data 17 (N) is not less than the allowable minimum data transmission interval.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a competitive multiplexing apparatus for sending a plurality of data output asynchronously from a plurality of data sources to one multiplex transmission line so as not to overlap each other.

[0002]

2. Description of the Related Art In recent years, communication systems have been actively developed. This communication system is a many-to-one communication system in which a plurality of communication devices according to one main communication device are connected to perform communication. A typical example of this many-to-one communication system is a communication system in which a plurality of terminals are connected to a host computer.

In such a communication system, the communication data transmitted from each terminal is usually multiplexed and then supplied to the processing unit of the host computer. Therefore, when the communication data is sent out asynchronously from each terminal, a contention multiplexer for preventing collision due to contention of the communication data sent from each terminal is required.

In the case where the communication data is fixed length data, a competitive multiplex device for preventing this collision has hitherto been known.
A competitive multiplex system of a priority system and a fixed scheduling system is considered.

Here, the priority system contention multiplexing apparatus is provided with a buffer unit for temporarily holding fixed length data transmitted from the corresponding terminal for each terminal, and the fixed length is composed of a plurality of buffer units. When data transmission requests are generated simultaneously, one transmission request is selected from these transmission requests in accordance with a predetermined priority order, and fixed length data is transmitted from the buffer unit that has generated the selected transmission request. Is.

Further, the fixed-scheduling contention multiplexer is provided with a buffer unit for temporarily holding the fixed-length data transmitted from the corresponding terminal for each terminal, and is held in each buffer unit. This is a device that sends fixed-length data according to a predetermined schedule.

According to the priority-based contention multiplexer, even when transmission requests are simultaneously generated in a plurality of buffer units,
Since one transmission request can be selected from these in accordance with a predetermined priority order, even if a plurality of fixed length data conflict, these collisions can be prevented.

Further, according to the fixed scheduling type competitive multiplexer, the fixed length data held in each buffer unit is sent out according to a predetermined schedule, so that even when a plurality of fixed length data competes with each other, These collisions can be prevented.

[0009]

However, in the contention multiplexer of the priority order system, the winner is determined in accordance with a predetermined priority order every time a conflict occurs, and therefore, it is transmitted from each terminal. If the statistical characteristics of the amount of information (average value, maximum value, or variance of the number of fixed-length data that occur within a unit time) differ greatly from terminal to terminal, then the terminal with a large amount of information has a low priority. However, there is a problem that the waiting time for the fixed length data transmitted from this terminal becomes long and the delay fluctuation of the fixed length data becomes large.

Thus, when this competitive multiplex device is applied to a competitive multiplex device of a multimedia communication system that handles voice, image, data, etc. as fixed length data, voice and image can be reproduced normally. There was a risk of disappearing.

That is, when transmitting voice and images,
Delay fluctuations that occur in the communication system have a great influence on the transmission quality, and if this delay fluctuation exceeds the allowable range,
It becomes impossible for the receiving side to properly play back the sound or image. Therefore, when transmitting voice or images, it is necessary to reduce delay fluctuation.

However, voice and images usually have a large amount of information. Therefore, when the priority-based contention multiplexer is applied to a contention multiplexer of a multimedia communication system,
If the priority of voice or image is low, the waiting time becomes long and the delay fluctuation becomes large. as a result,
In this case, there is a possibility that the sound or the image cannot be reproduced normally.

Further, in the fixed-scheduling contention multiplexer, fixed-length data is transmitted according to a predetermined schedule regardless of the generation time of the fixed-length data transmission request. There is a problem that the waiting time for the fixed length data becomes long and the delay fluctuation becomes large, depending on the generation time of the transmission request.

[0014]

In order to solve the above-mentioned problems, the present invention provides a plurality of data holding means provided for each data generation source and holding fixed length data output from the corresponding data generation source. And, for each data holding means,
When a predetermined number of fixed length data is held in the data holding means, a sending request output means for outputting a sending request for the fixed length data and a plurality of sending requests are simultaneously output from the sending request output means. And, from the plurality of transmission requests, one transmission request is selected in accordance with a predetermined priority order, and when one transmission request is output, the transmission request selection means and the transmission request selection means. A transmission time reservation means for reserving the data transmission time of the data holding means which has generated the transmission request selected by so as to satisfy the allowable minimum data transmission interval defined in the data holding means,
Based on the data transmission time reserved by the transmission time reservation means, there is provided data transmission means for transmitting the fixed length data held in the plurality of data holding means to the multiplex transmission line, and a plurality of transmission request output means are provided. When the transmission requests are output simultaneously, one transmission request is selected from the plurality of transmission requests according to a predetermined priority order, and when one transmission request is output, this is selected and selected. The data transmission time of the data holding means that generated the specified transmission request is reserved so as to satisfy the allowable minimum data transmission time interval defined in this data holding means, and a plurality of data is stored based on the reserved data transmission time. The fixed length data held in the holding means is sent to the multiplex transmission line.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

[One Embodiment] [Overall Structure of One Embodiment] FIG. 1 is a block diagram showing the structure of one embodiment of the present invention. In the following description, the present invention will be described as (N + 1) terminals T (0).
~ In a host computer to which T (N) is connected, fixed length data transmitted asynchronously from each terminal T (n) (n = 0, 1, ..., N) should not overlap each other. A case where the present invention is applied to a competitive multiplex device that sends data to one multiplex bus will be described as a representative.

The illustrated competitive multiplexer has (N + 1) buffer units 10 (0) to 10 (N), a cyclic priority encoder 11, and a dynamic scheduler 12.

Here, each buffer unit 10 (n) has fixed length data 17 transmitted from the corresponding terminal T (n).
It has a function of holding (n). In addition, each buffer unit 1
0 (n) has a function of transmitting the held data to the multiplex bus 13 according to a transmission time reserved by the scheduler 12 described later. Furthermore, each buffer unit 10 (n)
For example, when one or more pieces of fixed length data 17 (n) are held, it has a function of setting the transmission request signal 14 (n) to the active state.

The encoder 11 has a plurality of transmission request signals 1
4 (n) are simultaneously set to the active state, the plurality of transmission request signals 14
When one transmission request signal 14 (n) is selected from among (n) and one transmission request signal 14 (n) is set to the active state, a function of selecting this transmission request signal 14 (n) is provided. Have. Further, the encoder 11 has a function of cyclically changing the priority order at a predetermined cycle.

Each time the scheduler 32 selects the transmission request signal 14 (n) by the encoder 31, the scheduler 32 holds the transmission request signal 14 (n) in the buffer unit 10 (n) which is set in the active state. It has the function of reserving the time to send long data. This reservation is performed so that the transmission interval when transmitting the fixed length data from the buffer unit 10 (n) does not become smaller than the allowable minimum data transmission interval T0 (n).

Here, the allowable minimum data interval T0 (n) is the minimum allowable data transmission interval when a plurality of fixed length data is continuously transmitted from each buffer unit 10 (n). The allowable minimum data transmission interval T0 (n) is set for each buffer unit 10 (n).

[Operation] The operation of the above configuration will be described.

The fixed length data 17 (n) transmitted from each terminal T (n) asynchronously with each other is stored in the corresponding buffer unit 1.
0 (n). The fixed length data 17 (n) supplied to the buffer unit 10 (n) is stored in the buffer unit 10 (n).
The data is written in the internal memory (hereinafter referred to as “buffer memory”) by (n).

When one or more pieces of fixed length data 17 (n) are accumulated in this buffer memory, the buffer unit 10 (n)
Causes the send request signal 14 (n) to be set to the active state. As a result, the encoder 11 is notified that the fixed length data 17 (n) to be transmitted to the multiplex bus 13 exists in the buffer memory of the buffer unit 10 (n).

The transmission request signal 14 (n) set to the active state is selected by the encoder 11. In this case, when a plurality of transmission request signals 14 (n) are simultaneously set to the active section state, the transmission request signals 14 set to the active state according to a predetermined priority order.
One transmission request signal 14 (n) is selected from among (n). On the other hand, when only one transmission request signal 14 (n) is set to the active state, this transmission request signal 14 (n) is selected.

The priority order is cyclically changed in a predetermined cycle. This is to maintain fair competition multiplexing.

When the transmission request signal 14 (n) is selected,
Information indicating the selected transmission request signal 14 (n) is supplied to the scheduler 32. As a result, a process of reserving the transmission time of the fixed length data held in the buffer unit 10 (n) which sets the selected transmission request signal 14 (n) to the active state is executed. In this process, the data transmission interval of the buffer unit 10 (n) is
Allowable minimum data transmission interval T0 set to 0 (n)
It is executed so as not to be smaller than (n).

As a result, the transmission time of the fixed length data 17 (n) is not the generation order of the transmission requests, but the generation order, the allowable minimum data transmission interval T0 (n), and the vacant time (reservable time). Determined according to the presence or absence.

The data indicating the reserved sending time is sequentially read by the scheduler 12 at a predetermined cycle. This read output is supplied to the buffer units 10 (0) to 10 (N) as the transmission permission signal 16. As a result, each buffer unit 10 is read according to the read out time.
The fixed length data 17 (n) held in (n) is sent to the multiplex bus 13.

[Structure of Encoder 11] FIG. 2 is a circuit diagram showing an example of a concrete structure of the encoder 11.

The encoder 11 shown in the figure includes a selection unit 111.
It has an encoder 112, a counter 113, and a decoder 114.

Here, when a plurality of sending request signals 14 (n) are simultaneously set to the active state, the selecting section 111 sets one sending request signal 14 according to a predetermined priority.
When (n) is selected and only one transmission request signal 14 (n) is set to the active state, this transmission request signal 14
It has a function of selecting (n).

The encoder 112 decodes the transmission request signal 14 (n) selected by the selecting unit 111 to generate a buffer identifier B (n), and outputs a buffer identifier signal 15 including this buffer identifier B (n). Has a function to output. In addition to the buffer identifier B (n), a 1-bit flag indicating whether or not this is valid is inserted in the buffer identifier signal 15.

The counter 113 and the decoder 114 have a function of generating a signal indicating a priority order and a function of cyclically changing the priority order at a predetermined cycle. Here, the counter 113 has a function of cyclically counting up by counting the clock signal CK1. Also, the decoder 114 decodes the count output of the counter 113 to obtain (N + 1) priority order signals 18
It has a function of generating (0) to 18 (N).

The priority signals 18 (n) are set to the active state periodically without overlapping with each other and for a time corresponding to the cycle of the clock signal CK1. When one priority signal 18 (n) is set to the active state, one priority is designated. Now, assuming that the priority orders designated by the priority order signals 18 (0) to 18 (N) are P (0) to P (N), these are expressed as follows, for example.

P (0): 14 (0) → 14 (1) → ... → 14 (N) P (1): 14 (1) → 14 (2) → ... → 14 (0) N): 14 (N) → 14 (0) → ... → 14 (N-1) However, the priority becomes lower toward the arrow direction.

The selecting unit 111 determines that each transmission request signal 1
(N + 1) logic circuits 11 provided every 4 (n)
It has 1 (0) to 111 (N). Each logic circuit 111
(N) is a 2-input AND circuit a1 (n), a3 (n)
, An inverter circuit a2 (n), and a 2-input OR circuit a4
Have (n).

[Operation of Encoder 11] The operation of the above configuration will be described. First, the operation of selecting the transmission request signal 14 (n) will be described.

(N + 1) transmission request signals 14 (0) to
14 (N) is supplied to the selection unit 111. Selector 11
1 selects one transmission request signal 14 (n) from the transmission request signals 14 (n) set in the active state according to the priority order P (n) being set.

This will be described using a specific example. First, the case where the transmission request signals 14 (0) to 14 (N) are set to the active state and the priority order P (0) is set will be described. In this case, the transmission request signal 14
(0) has the highest priority. So, in this case,
The transmission request signal 14 (0) is selected.

Next, the transmission request signals 14 (1) to 14
(N) is set to the active state and the priority order P
The case where (0) is set will be described. In this case, the transmission request signal 14 (0) has the highest priority. However, in this case, the transmission request signal 14 (0) is set to the inactive state. Therefore, in this case, the transmission request signal 14 (1) having the next highest priority is selected.

From the above, when the priority order P (0) is set and the sending request signal 14 (0) is set to the inactive state, the priority is the sending request signal 1
4 (0) is transferred to the transmission request signal 14 (1).

Transmission request signal 1 selected by the selection unit 111
4 (n) is supplied to the encoder 112. The transmission request signal 14 (n) supplied to the encoder 112 is converted into the identifier B (n) of the buffer unit 10 (n) which sets the transmission request signal 14 (n) in the active state. When this conversion is completed, a buffer identifier signal 15 including this identifier B (n) and a 1-bit flag indicating whether or not this is valid is generated.

Here, the flags included in the buffer identifier signal 15 are the transmission request signals 14 (0) to 14 (N).
If at least one of these is set to the active state, it is set to "1". On the other hand, when all are set to the inactive state, they are set to "0".

In this case, if the flag is "1", it indicates that the buffer identifier is valid, and if the flag is "0", it indicates that it is invalid. In other words, when the flag is "1", the buffer identifier is represented by the original B (n), and when it is "0", it is represented by a value other than B (n).

The above is the operation of selecting the transmission request signal 14 (n). Next, the priority changing operation will be described.

The counter 113 counts up the clock signal CK1 to increment from 0 by 1. This count output is supplied to the decoder 114. The decoder 114 sequentially sets the priority signals 18 (0) to 18 (N) one by one in the active state based on the count output of the counter 113.

In this case, if the count output of the counter 113 is "0", for example, the priority signal 18 (0) is set to the active state, and if it is "1", the priority signal 18 (1) is set. Set to active state. Less than,
Similarly, if the count output is "N", the priority signal 18 (N) is set to the active state. As a result, the priority order is sequentially changed in synchronization with the counting operation of the counter 113.

The above is the priority changing operation. Next, the internal operation of the selection unit 111 will be described using a specific example. In the following description, it is assumed that the signal active levels are all “1”.

First, the transmission request signals 14 (0) -14
A case where (N) and the priority signal 18 (0) are set to the active state will be described. In this case, the output signal of the 2-input AND circuit a1 (0) of the logic circuit 111 (0) becomes "1". Thereby, the inverter circuit 2a
The output signal of (0) becomes "0". As a result, the 2-input AND circuit a of the other logic circuits 111 (1) to 111 (N)
The output signals of 1 (1) to a1 (N) are all "0". As a result, in this case, the transmission request signal 14 (0)
Will be selected.

Next, the transmission request signals 14 (1) to 14
(N) and the priority signal 18 (0) are set to the active state, and the transmission request signal 14 (0) is set to the inactive state. In this case, the output signal of the 2-input AND circuit a1 (0) of the logic circuit 111 (0) becomes "0". As a result, the inverter circuit 2
The output signal of a (0) becomes "1".

As a result, the output signal of the 2-input OR circuit 4a (1) of the logic circuit 111 (1) becomes "1". As a result, the output signal of the 2-input AND circuit a1 (1) is "1".
Becomes As a result, the output signal of the inverter circuit 2a (1) becomes "0". As a result, the other logic circuit 111
The output signals of the 2-input AND circuits a1 (2) to a1 (N) and a1 (0) of (2) to 111 (N) and 111 (0) are
All become "0". As a result, in this case, the transmission request signal 14 (1) is selected.

From the above, when the priority signal 18 (0) is set to the active state, the transmission request signal 14
If (0) is in the inactive state, the priority is transferred from the transmission request signal 14 (0) to the transmission request signal 14 (1).

Similarly, the transmission request signals 14 (0) to 14 (0)-
When any one or more of 14 (N) is set to the active state, one of the output signals of the 2-input AND circuits 1a (0) to 1a (N) is set to the active state.

On the other hand, the transmission request signals 14 (0) to 1
When all 4 (N) are set to the inactive state, all output signals of the 2-input AND circuits 1a (0) to 1a (N) are set to the inactive state.

[Configuration of Scheduler 12] FIG. 3 is a block diagram showing an example of a specific configuration of the scheduler 12.

The illustrated scheduler 12 includes a schedule memory unit 121, a counter 122, and a management memory unit 1.
23, a reservation search start address determining unit 124, a reservation address determining unit 125, and a timing generating unit 126.

Here, the schedule memory unit 121 is
For example, it has a schedule memory composed of a random access memory. The reservation of the transmission time of the fixed length data 17 (n) is performed by writing the buffer identifier B (n) extracted from the buffer identifier signal 15 into this schedule memory.

FIG. 4 is a diagram showing an example of the schedule memory. As shown, the schedule memory has a plurality of areas b (0), b (1), .... Each area b
The buffer identifier B (n) included in the buffer identifier signal 15 is written in (m) (m = 0, 1, 2, ...). In addition, each area b (m) has one address A
(M) is given.

The schedule memory unit 121 has a function of sequentially reading the buffer identifiers B (n) written in the schedule memory one by one in a predetermined cycle TS. This read output is supplied to the buffer units 10 (0) to 10 (N) as the transmission permission signal 16. Here, the period T
S corresponds to the time when one fixed length data 17 (n) occupies the multiplex bus 13.

The schedule memory unit 121 also has a function of writing the buffer identifier B (n) included in the buffer identifier signal 15 into the schedule memory. As a result, the transmission time of the fixed length data 17 (n) held in the buffer memory of the buffer unit 10 (n) is reserved. Note that this writing is performed based on the above-described allowable minimum data transmission interval T0 (n), which will be described in detail later.

The counter 122 has a function of counting the clock signal CK2 of the cycle TS to generate a read address for reading the buffer identifier B (n) from the schedule memory.

The management memory section 123 has a management memory composed of, for example, a random access memory. Reserved address determination data is stored in this management memory for each buffer unit 10 (n). Here, the reserved address determination data is data required to determine a reserved address when writing the buffer identifier B (n) of the buffer unit 10 (n) in the schedule memory.

FIG. 5 shows the configuration of the management memory. As shown, the management memory has (N + 1) areas c
(0) to c (N). Each area c (n) has a buffer section 10
(N). One address is assigned to each area c (n). Each address is represented by a buffer identifier B (n).

The reserved address determination data of the corresponding buffer unit 10 (n) is stored in each area c (n). This address determination data includes the data indicating the allowable minimum data transmission interval T0 (n) and the previous data transmission time TR.
^-1 (n) data and the previous data transmission time TR
^-1 (n) has a flag F (n) indicating whether it is valid or not.

Here, the previous data transmission time TR ^-1 (n)
Is the transmission time of the fixed length data 17 (n) reserved in the schedule memory unit 121 according to the previous transmission request of the fixed length data 17 (n). The last data transmission time TR ^-1 (n) is a time when the delivery request of the next fixed length data 17 (n) is generated, the previous data transmission time TR ^-1
If (n) has not passed, it is validated, and if it has passed, it is invalidated.

The management memory unit 123 has a function of reading the reserved address determination data from the address corresponding to the buffer identifier B (n) included in the buffer identifier signal 15.

Further, the management memory unit 123 is used by a reserved address determining unit 125, which will be described later, in the buffer identifier B.
When the reserved address of (n) is determined, this is set to the corresponding address of the management memory, and the previous data transmission time TR
^-1 (n), and the transmission time TR ^-1
It has a function of setting a flag F (n) indicating that (n) is valid.

Further, the management memory unit 123 has a flag F indicating that the sending time TR ^-1 (n) is valid.
After setting (n), the read address of the schedule memory generated by the counter 122 is monitored, and when this read address exceeds the reserved address, it is confirmed that the previous data transmission time TR ^-1 (n) is invalid. It has a function of setting the flag F (n) shown.

Reservation search start address determination unit 124
Has a function of determining a search start address when determining a reserved address. This search start address is set to the address next to the read address generated by the counter 122.

The reserved address determination unit 125 has a function of determining a reserved address based on the reserved address determination data read from the management memory of the management memory unit 123 while searching the schedule memory.

The timing generator 126 has a function of generating various timing signals required by the scheduler 12 based on the clock signal CK3. Here, the clock signal CK3 is generated by multiplying the frequency of the clock signal CK2.

[Operation of Scheduler 12] The operation of the above configuration will be described. First, the operation of reserving the transmission time of the fixed length data 17 (n) stored in the buffer memory of the buffer unit 10 (n) in the schedule memory will be described.

The buffer identifier signal 15 output from the encoder 11 is supplied to the schedule memory unit 121 and the management memory unit 123. Schedule memory unit 12
1 indicates that the flag included in the buffer identifier signal 15 is "
If it is "1", the reservation operation is executed, and if it is "0", the reservation operation is not executed.

When executing the reservation operation, the schedule memory unit 121 writes the buffer identifier B (n) included in the buffer identifier signal 15 into the reservation address determined by the reservation address determination unit 125. In this case, the reserved address is determined as follows.

The counter 122 counts the clock signal CK2 to generate a read address of the schedule memory. The read address is supplied to the schedule memory unit 121 and the reservation search start address determining unit 124.

On the other hand, the management memory 123 reads the reserved address determination data from the area c (n) of the management memory whose address is the buffer identifier B (n) included in the buffer identifier signal 15. The read reserved address determination data is held in an internal register (not shown).

The reserved address determining data held in the internal register is supplied to the reserved address determining unit 125.
The latching clock signal of the internal register is set to the same TS as the cycle of the clock signal CK2. The latch clock signal is output from the timing generator 126.

Reservation search start address determination unit 124
Determines the address next to the read address currently generated by the counter 122 as the search start address. The reserved address determination unit 125 determines a reserved address based on the determined search start address and the reserved address determination data read from the management memory.

This determining operation will be described with reference to FIG. Now, in the encoder 11, the transmission request signal 14 (2)
Is selected, and the counter 122 reads the read address A.
It is assumed that (3) has been generated.

In this case, the reserved search start address determining unit 124 determines A (4) as the search start address. Data indicating the determined start address A (4) is supplied to the reserved address determination unit 125.

Further, the management memory unit 123 reads the address determination data of the buffer unit 10 (2) as the address determination data. The read address determination data is supplied to the reserved address determination unit 125.

First, the reserved address determination unit 125 determines whether or not the previous data transmission time TR ^-1 (2) is valid based on the flag F included in the address determination data. If it is valid, the address at which the buffer identifier B (2) is stored is detected according to the previous transmission request for the fixed length data 17 (2). This detection is the previous data transmission time TR ^-1.
It is performed according to (2). In this case, the address corresponding to the previous data transmission time TR ^-1 (2) is the target address. By this detection processing, the address A (5) is detected in the example of FIG.

Next, the reserved address determination unit 124 detects an address separated from the address A (5) by the number of addresses corresponding to the allowable minimum data transmission interval T0 (2). Now, the allowable minimum data transmission interval T of the buffer unit 10 (2)
If 0 (2) is set to 3TS, an address separated by 3 addresses from address A (5) is detected. As a result, in the example of FIG. 4, the address A (8) is detected.

Next, the reserved address determination unit 124 has already assigned another buffer identifier B (n) to the address A (8).
Is stored. If not stored, this address A (8) is determined as the reserved address. On the other hand, already another buffer identifier B
If (n) is stored, the buffer identifier B
Writing in (2) is not performed. In the example of FIG. 4, since the buffer identifier B (0) is already stored in the address A (8), the writing of the buffer identifier B (2) is not executed.

In this case, the reserved address determining unit 124
Addresses after the address A (8), which is next to the address A (9), are searched for empty addresses. Then, when this empty address is detected, this empty address is determined as a reserved address. In the example of FIG. 4, the address A (9) is an empty address. Therefore, in this case, this address A (9) is determined as the reserved address. As a result, the contents of the schedule memory are updated as shown in FIG.

If the previous data transmission time TR ^-1 (2) is invalid, the reserved address determination unit 125 reserves the first empty address among the addresses after the search start address A (4). Determine as address.

The data indicating the determined reserved address is
It is supplied to the schedule memory 121 and the management memory unit 123. The management memory unit 123
When this data is received, the determined reserved address is registered in the management memory as data indicating the new previous data transmission time TR ^-1 (2), and the content of the flag F (2) is set to "valid". After that, the management memory unit 123 monitors the read address output from the counter 122, and when the read address exceeds the previous data transmission time TR ^-1 , the content of the flag F (2) is made "invalid".

The above is the reservation operation for the schedule memory. Next, the operation of reading the buffer identifier B (n) from the schedule memory will be described.

The counter 122 counts the clock signal CK2 to generate a read address of the schedule memory. This read address is supplied to the schedule memory unit 121. The schedule memory unit 121 reads the buffer identifier B (n) from the area of the schedule memory corresponding to this read address. This read output is supplied to the buffer units 10 (0) to 10 (N) as the transmission permission signal 16.

[Effect] According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, when a plurality of transmission request signals 14 (n) are simultaneously set to the active state, the plurality of transmission request signals 14 (n) are set in accordance with a predetermined priority. ), One transmission request signal 14
When (n) is selected and one transmission request signal 14 (n) is set to the active state, this transmission request signal 14 (n)
Every time the transmission request signal 14 (n) is selected, the transmission time of the buffer unit 10 (n) in which the selected transmission request signal 14 (n) is set to the active state is reserved in the schedule memory. Therefore, each time a request for sending the fixed length data 17 (n) is issued, the sending time can be reserved. As a result, fixed length data 1
Since the waiting time of 7 (n) can be shortened, the delay fluctuation can be reduced.

(2) Further, according to this embodiment, the priority order is cyclically changed in a predetermined cycle, so that fair competition multiplexing can be ensured.

(3) Further, according to this embodiment, the previous data transmission time TR ^-1 of the fixed length data 17 (n) is registered in the management memory, so that the reserved address can be quickly obtained. You can decide.

[Other Examples] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment.

For example, in the above embodiment, the case where the priority order is cyclically changed in a predetermined cycle has been described. However, in the present invention, the priority may be fixed. In addition to this, it goes without saying that the present invention can be variously modified and implemented without departing from the scope of the invention.

[0097]

According to the present invention described in detail above, when a plurality of transmission requests are generated at the same time, one transmission request is selected from the plurality of transmission requests according to a predetermined priority, and one transmission request is selected. When this occurs, this transmission request is selected, and each time the transmission request is selected, the transmission time of the data holding means that generated the selected transmission request is reserved, so that a fixed-length data transmission request is generated. Every time you,
The sending time can be reserved. As a result, the waiting time for fixed length data can be shortened,
The delay fluctuation can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a specific configuration of an encoder 31 according to an embodiment.

FIG. 3 is a circuit diagram showing an example of a specific configuration of a scheduler 32 according to an embodiment.

FIG. 4 is a diagram showing a configuration of a schedule memory according to an embodiment.

FIG. 5 is a diagram showing a configuration of a management memory according to an embodiment.

FIG. 6 is a diagram for explaining an update operation of the management memory according to the embodiment.

[Explanation of symbols]

10 (0) to 10 (N) ... Buffer unit 11 ... Cyclic priority encoder 12 ... Dynamic scheduler 13 ... Multiplex bus 111 ... Selection unit 112 ... Encoder 113 ... Counter 114 ... Decoder 121 ... Schedule memory unit 122 ... Counter 123 ... Management Memory unit 124 ... Reserved search start address determination unit 125 ... Reserved address determination unit 126 ... Timing generation unit 111 (0) to 111 (N) ... Logic circuit a1 (0) to a1 (N), a3 (0) to a3 ( N) ... 2
Input AND circuit a2 (0) to a2 (N) ... Inverted circuit a4 (0) to a4 (N) ... OR circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Tsutomu Kobayashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] 1. A competitive multiplex device for sending a plurality of fixed length data output asynchronously from a plurality of data generation sources to one multiplex transmission path so as not to overlap each other, and provided for each data generation source. A plurality of data holding means for holding the fixed length data output from the corresponding data generating source, and a predetermined number of fixed length data is held in the data holding means for each data holding means, When a plurality of transmission requests are simultaneously output from the transmission request output means for outputting the transmission request for the fixed length data, one of the plurality of transmission requests is output in accordance with a predetermined priority order. When a transmission request is selected and one transmission request is output, a transmission request selection means for selecting this and a data transmission request selected by this transmission request selection means are generated. The data transmission time of the data holding means is reserved based on the transmission time reservation means which reserves the data transmission time to satisfy the allowable minimum data transmission interval defined in the data holding means, and the transmission time reserved by the transmission time reservation means, And a data sending unit for sending the fixed length data held in the plurality of data holding units to the multiplex transmission path.