JPH09153549A - Wiring layout method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify wiring and prevent the generation of an extra space by extending the wiring from one end to the other end by one gate on the basis of net information and repeating the treatment of disposing and connecting a terminal by the number of a gate when needed. SOLUTION: Net information is captured from a memory device 41, thereby recognizing the connection information of an IIL layout in which the row of a gate is fixed therefrom (S1). In the net information, the number of a gate and the number of a collector terminal in each gate are constituted of the net number of a base terminal and a collector terminal. In the treatment, the terminal of a left end gate is first disposed, thereby determining the terminal position of the left end gate (S2). The wiring is extended by one gate from left to right from the terminal of the left end gate on the basis of the net information (S3). At that time, when the next gate of a gate in which a terminal is already disposed requires a terminal, a terminal is disposed (S4).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring arrangement method for a semiconductor device, and more particularly to, for example, CAD (Computer Aided D).
IIL (Integrated Injection Logic) using esign)
The present invention relates to layout placement and wiring.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional terminal placement and wiring method.
First, all gate cells are arranged 51 with respect to the IIL layout pattern in which the gate arrangement is determined. The collector terminal is arranged in advance in each gate cell. Attach net information to each terminal in this gate cell 5
2. In FIG. 6, after arranging a plurality of gate cells 17, a net number 1 is assigned to the collector terminal 11 and the base terminal 12 in the gate.
The state where 3 is attached is shown. After that, wires are connected between the terminals with a corresponding net. That is, as a general rule, terminals to which the same net information is attached are connected by one-layer wiring. If the wirings cross each other if only one-layer wiring is used, raise one wiring on the interlayer insulating film through the through hole.
The wiring at the intersection is formed by using the two-layer wiring.
FIG. 7 shows a pattern obtained as a result of connecting the terminals with the single-layer wiring 15 and the double-layer wiring 16 based on FIG.

[0003]

In the prior art, since the placement process of the gate cell 17 and the wiring process between the terminals 11 and 12 are performed separately, the terminal position of the gate cell 17 is fixed. Moreover, since the pieces of net information having the same number are connected to each other, the terminals cannot be arbitrarily selected at the wiring stage. As a result, there is a tendency that the wiring cannot be made or the through holes are used so much that the wiring is taken into consideration, an extra space is generated, and the wiring area becomes large.

[0004] The present invention is to solve the above problems,
It is an object of the present invention to provide a wiring arrangement method for a semiconductor device in which wiring is simple and wiring can be prevented by allocating and arranging terminal positions while wiring.

[0005]

[Means for Solving the Problem] The gate arrangement has been determined I
Net information is fetched from the IL layout pattern, the wiring is extended by the number of gates, and terminals are allocated on the gates when necessary. By arranging the collector terminals while wiring from one end to the other, wiring can be simplified and an extra space can be suppressed.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those in FIGS. 6 and 7 are designated by the same reference numerals. FIG. 4 shows an apparatus applied to the present invention. This device is a storage device 41 that stores net information and the like, an arithmetic processing device 42 that is connected to this storage device 41 and performs wiring processing and the like based on the net information, and is connected to this arithmetic processing device 42 and inputs commands and the like. And a display device 44 for displaying the processing result and the like.

FIG. 1 shows an embodiment of the present invention and shows the operation of the arithmetic processing unit 42. Also,
FIG. 2 shows a pattern obtained as a result of the processing proceeding from the left end to the fourth gate in the terminal arrangement and wiring method of the present invention. First, the net information is fetched from the storage device 41, and the connection information of the IIL layout in which the gate arrangement is determined is recognized from this net information (S1). The net information includes the number of gates, the number of collector terminals in each gate, and the net numbers of the base terminal and collector terminal in each gate. In the process, first, the terminal position of the left end gate is determined by arranging the terminal of the left end gate (S2). For example, the leftmost gate in FIG. 2 requires two collector terminals with net numbers 1 and 2 according to the net information, and therefore such collector terminals are arranged respectively. In FIG. 2, with respect to the left end gate, the net numbers are 1 for the upper collector terminal and 2 for the lower collector terminal, but they may be reversed. In addition, the base terminal of net number 500 is also arranged. From the terminal of these left edge gates, wire from left to right based on net information 1
Extend the gate (S3). That is, in FIG. 2, the wires from the terminals of net numbers 1 and 2 extend to the right. At this time, if the gate next to the gate on which the terminal has already been arranged requires the terminal, the terminal is arranged (S4). For example, the second gate from the left requires the collector terminal of net number 2, so the collector terminal is installed at the intersection of the gate and the wiring of net number 2. The above processing is repeated for the number of gates (S5).

The case of using through holes will be described. For example, in the second S3 process, in the base terminal 12 of the second gate from the left, the wiring of the net numbers 1 and 2 extends toward the third gate from the left,
Moreover, it is not connected to the base terminal of the third gate. Therefore, the wiring extending from the base terminal 3 must cross the wiring of the net numbers 1 and 2. Therefore,
The through gate 14 and the two-layer wiring 15 are used to cross over the wirings of the net numbers 1 and 2, and the wiring of the net number 3 is formed next to these wirings.

FIG. 3 is a pattern diagram of a result obtained by finishing the processing up to the last rightmost gate. Further, the present invention is not limited to the above method of arranging the wiring and the terminal for each gate, and includes a method of arranging the wiring and the terminal for every predetermined number of gates. For example, it is conceivable that wiring and terminals are arranged every time 4 gates are arranged.

In the prior art, as shown in FIG. 7, the use of through holes 14 is increased and the area occupied by the wirings 15 and 16 is increased, whereas in the present invention, as shown in FIG. 3, the number of used through holes is increased. There is less, and the area occupied by the wiring becomes smaller.
Further, the process according to the present invention is not limited to the process performed from the left end as described above, and the process is performed in any direction and is included in the present invention.

[0011]

As described above, according to the present invention,
Since the terminals are arranged while forming the wiring, the terminals can be arranged arbitrarily, the number of through holes used is small, and the wiring arrangement of the IIL semiconductor device having a small wiring occupation area becomes possible.

[Brief description of the drawings]

FIG. 1 is a flow chart of a terminal placement and wiring method of the present invention.

FIG. 2 is a diagram showing a state in which processing has proceeded from the left end and processing has proceeded to the fourth gate in the terminal arrangement and wiring method of the present invention.

FIG. 3 is a pattern diagram of a result obtained by ending the processing up to the last rightmost gate.

FIG. 4 is a configuration diagram showing an apparatus applied to the present invention.

FIG. 5 is a flowchart of a conventional terminal placement and wiring method.

FIG. 6 is a diagram of a stage in which net information is attached to each terminal in the gate after the gate cell is arranged in the conventional terminal arrangement and wiring method.

FIG. 7 is a pattern diagram of a result of wiring between the terminals based on FIG. 3 in the conventional terminal arrangement wiring method.

[Explanation of symbols]

 11 ... Collector terminal, 12 ... Base terminal, 13 ... Net number, 14 ... Through hole, 15 ... 1 layer wiring, 16 ... 2 layer wiring, 17 ... Gate cell.

Claims (2)

[Claims] 1. A base terminal and a collector terminal of a gate at one end are arranged with respect to an IIL layout pattern in which a gate arrangement is determined, and wiring is arranged from one end to the other end based on net information.
If it is necessary to extend only the gate and connect the wiring to the base terminal or collector terminal of the gate next to the gate where the terminal is already placed based on the net information, place the terminal and connect it. A wiring arrangement method for a semiconductor device, characterized in that the above-mentioned processing is repeated for the number of gates. 2. The wiring arrangement method for a semiconductor device according to claim 1, wherein the extending of the wiring and the arrangement of the base terminal or the collector terminal are performed for two or more gate cells.