JPH09160521A - Image display device - Google Patents

Abstract

(57) [Abstract] [Problem] Dot clock frequency data table PL
By providing those having different overlap ratios of the L pull-in range, a two-step search of a rough search and a main search is performed, and the time required for locking is shortened. A display circuit section 7 determines the frequency of a horizontal synchronizing signal from a terminal 1, sends data to a CPU 9,
The display circuit section is switched by means of the above, and at the same time, a signal is sent to the clock generator 5 so that the signal from the VCO 4 is converted and output to a required frequency based on the discrimination of the horizontal frequency. The CPU reads the dot clock frequency data table in which the overlap ratio of the PLL pull-in range is set low from the storage unit 8, controls the clock generator, and reads the data table of the standard overlap ratio by pull-in to include the frequency. The data in the pull-in range is determined and the clock generator is controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for inputting various kinds of horizontal frequency video signals, and more particularly to a device for shortening the adjustment time of the pull-in range of a PLL (phase locked loop) circuit.

[0002]

2. Description of the Related Art In an image display device in which display pixels have a one-to-one correspondence with video data, for example, an image display device using a plasma display panel (PDP) or a liquid crystal display element (LCD), a horizontal input video signal is used. It is necessary that the frequency (horizontal frequency) and phase of the synchronization signal match the frequency and phase of the dot clock that serves as the reference for the display timing of the display device. This is because when the phase of the input sync signal and the phase of the dot clock are deviated, the sampling position of the display data is deviated, and, for example, a repeating pattern of white and black dots is displayed in gray, or the repeating cycle is disturbed. Or, when a character is displayed, a phenomenon such as a vertical line being double displayed may occur, and a normal image display may not be performed. Also, when the horizontal frequency of the input signal and the frequency of the dot clock are different, data is thinned out or added in the horizontal direction due to the difference in the sampling number of image data per unit time, and it becomes impossible to display a normal image. If the phase exceeds the pull-in range of the phase of the dot clock and the horizontal sync signal, there may occur a case where the sync is lost.

At present, there are innumerable types of small computer devices and the like, and the horizontal frequency of the signal output from them is various, for example, 15 KHz, 24 KHz, 31 KHz, 37 KHz, etc. There are variations in these frequencies among devices. Therefore, an image display device that switches and inputs such a signal needs to be able to select an optimum dot clock frequency according to the horizontal frequency (including variation) of the input video signal and the number of display pixels of the display device. In terms of hardware, the frequency range of the dot clock that should be supported for each horizontal frequency is set, and this frequency range is continuously covered by multiple pull-in ranges, and the dot clock of the required frequency is generated. In addition to providing a clock generator that controls the input video signal, a control circuit that samples the input video signal for a required period and assigns it to a physical position (pixel) on the display device is provided. Judge the status, control the dot clock so that it corresponds to the input video signal, and turn off the display circuit. It is provided with the function of performing the example and the like. For this reason, the clock generator must be compatible with the serial interface, and if the phase of the dot clock is not locked, the frequency of the dot clock is gradually changed to a PLL (phase locked loop).
It is designed to fit within the pull-in range of the circuit.

By the way, the pull-in range of the PLL circuit has temperature dependency (the width of the pull-in range or the upper and lower limits vary depending on the temperature). For this reason, it may be necessary to shift to an adjacent drawing range due to a change in temperature. At that time, in order to prevent the lock from being disengaged at a discontinuous part of the drawing range, for example, as shown in FIG. A method is used in which the pulling ranges are set to overlap each other by about 50%. The PLL circuit is powered on,
Alternatively, when the input is switched, etc., within a dot clock frequency range corresponding to the horizontal frequency of the input video signal, for example, the pull-in range of the lowest frequency (in the figure) is sequentially searched from the pull-in range to the higher frequency, and the range that locks normally ( (In the figure) is searched. Therefore, when the number of pull-in ranges is large (for example, 60) and the range to be locked is in a high frequency region, it takes time to lock.

[0005]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention has a function for coarse search which is set by overlapping the pull-in ranges of the PLL circuits at a low rate and a function for standard search which is set by the standard overlap rate. Function is provided, the rough search function is first used to estimate the pull-in range, and then the standard function is searched to find the optimum pull-in range, thereby shortening the time required to lock the PLL circuit. is there.

[0006]

In order to solve the above problems, the present invention provides a clock generator that oscillates a dot clock, and an output signal of the clock generator that is input via a frequency divider to obtain the phase of a horizontal synchronizing signal. A phase comparator for comparison, a voltage controlled oscillator that oscillates at a frequency based on the signal from the phase comparator, a horizontal frequency determination unit that determines the frequency of the horizontal synchronization signal, and a horizontal frequency determination for the signal from the voltage controlled oscillator. A CPU for controlling so as to convert and output to a required frequency based on a discrimination signal from the unit and a storage unit for storing a dot clock frequency data table are provided, and a plurality of data tables having different dot clock frequency intervals are provided in the storage unit. To be stored, and by the CPU,
An image display device is provided in which a plurality of data tables are switched and read from a storage unit to control a clock generator.

[0007]

With the above construction, the image display device according to the present invention detects the frequency of the horizontal synchronizing signal,
A data table having a low overlap rate corresponding to the horizontal frequency is read from the storage unit, frequency data is serially transmitted to the clock generator via the CPU, the clock generator is controlled to change the dot clock frequency, and the PLL circuit The lock is searched, and the dot clock frequency in the pull-in range is determined by the lock. This completes the search with the low overlap rate data table, then reads the standard overlap rate data table from the storage unit, from which the dots within the pull-in range (plural) in which the dot clock frequency exists. The clock frequency data is serially transmitted to the clock generator, the optimum pull-in range is determined, the corresponding dot clock frequency data is determined, and the clock generator is controlled by this data.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the image display device according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a main part of an embodiment of an image display device according to the present invention. In the figure, reference numeral 1 is an input terminal for a horizontal synchronizing signal (H-sync), which inputs a horizontal synchronizing signal of, for example, 15 KHz, 24 KHz, 31 KHz or 37 KHz. A phase comparator 2 compares the phases of the horizontal synchronizing signal from the terminal 1 and the signal from the frequency divider 6 and outputs a signal corresponding to the phase difference. An LPF (low-pass filter) 3 integrates the signal from the phase comparator 2 to extract a DC component. A VCO (voltage controlled oscillator) 4 oscillates at a frequency corresponding to the voltage from the LPF 3. A clock generator 5 converts a signal from the VCO 4 into a desired frequency based on a signal from a CPU 9 which will be described later, and outputs the frequency.
The frequency divider 6 divides the signal from the clock generator 5 and inputs it to the phase comparator 2. These phase comparators 2, L
A PLL circuit is configured by the PF 3, the VCO 4, the clock generator 5, and the frequency divider 6.

Reference numeral 7 denotes a display circuit section, which is a horizontal frequency discriminating section for discriminating the frequency of the horizontal synchronizing signal from the terminal 1, and PL.
A lock discriminating unit for discriminating lock / unlock of L is built in, and a discrimination signal of a horizontal frequency is sent to the CPU 9,
The display counter is switched by the signal from 9 or the horizontal / vertical display position of the image is switched, and the dot clock from the clock generator 5 is compared with the horizontal synchronizing signal from the terminal 1 by the lock discriminating unit to perform PLL. The lock / unlock of is determined and the data is sent to the CPU 9.
Reference numeral 8 denotes a storage unit, which is the frequency of the horizontal synchronization signal (15 KHz,
Store the dot clock frequency data table corresponding to 24KHz, 31KHz, 37KHz, etc.). The CPU 9 reads a corresponding data table from the storage unit 8 according to the horizontal frequency from the display circuit unit 7 and serially transmits this data to the clock generator 5. The dot clock frequency table may be stored in the internal ROM of the CPU 9. The clock generator 5 is the CPU 9
The signal from the VCO 4 is converted and output to a required frequency based on the signal (horizontal frequency), and when the unlock is determined by the display circuit unit 7, the data in the adjacent pull-in range is read from the data table, The frequency of the clock generator 5 is switched to output a dot clock having a frequency corresponding to the input video signal.

The storage unit 8 stores each horizontal frequency (15 above).
KHz, 24KHz, 31KHz, 37KHz, etc.), and a dot clock frequency data table for low overlap rate and a dot clock frequency data table for standard overlap rate are provided. FIG. 2 is a partial view of this example (high frequency region is omitted), where (A) shows a low overlap rate (approximately 10%), and (B) shows a standard overlap rate (approximately 50%). Each pull-in range (A (1),
(2) Store dot clock frequency data corresponding to ... And B.

Next, the operation of the image display device according to the present invention will be described. The horizontal synchronizing signal from the terminal 1 is input to the display circuit unit 7, the horizontal frequency determining unit incorporated therein determines the horizontal frequency, and the data is sent to the CPU 9. The CPU 9 reads the control data corresponding to this signal from the storage unit 8, serially transmits it to the display circuit unit 7, switches the display counter, and preliminarily determines the horizontal position, vertical position, horizontal size, or vertical size of the image for each horizontal frequency. Switch to the set state.

At the same time, the CPU 9 sends a horizontal frequency discrimination signal to the clock generator 5, and the clock generator 5 converts the signal from the VCO 4 into a required frequency based on this signal. Then, first, for the horizontal frequency determined by the horizontal frequency determination unit from the storage unit 8,
The data table (A) in Fig. 2 with the overlap rate set to a low value (10%) is read and the pull-in range with the lowest frequency is read.
The dot clock frequency data corresponding to (1) is sent to the clock generator 5 to control the dot clock frequency. When the desired dot clock frequency is, for example, “a” shown in FIG. 2, the lock determination unit of the display circuit unit 7 determines unlock, and based on this determination, the data of the next pull-in range (2). Is sent to the clock generator 5, the unlock is discriminated even at this frequency, and the operation of ... Is repeated in sequence, the lock is discriminated in the pull-in range (5), and the data table (A) is searched by the discrimination of the lock. To finish.

Then, the data table (B) of the standard overlap ratio (50%) is read, the pull-in range and the pull-in range corresponding to the above-mentioned "a" are discriminated, and the dot clock frequency data corresponding to this pull-in range and the pull-in range are supplied to the clock generator 5. Serially transmit to and switch the dot clock frequency. Then, the lock discriminating unit of the display circuit unit 7 discriminates that the dot clock frequency according to the data of the pull-in range is optimum, whereby the clock generator 5 has the frequency corresponding to the frequency of the horizontal synchronizing signal from the terminal 1. It will output the dot clock.

When the frequency of the dot clock is "a", the number of times the pull-in range is searched is determined in the data table (A).
There are a total of 7 times, 5 times from (1) to (5) and 2 times of and in the data table (B). Compared to 8 times when using only the data table (B), there is a difference. Is small. However, the actual data table (B)
Has about 60 pull-in ranges in consideration of variations in signal sources (computer devices, etc.). For example, if the input signal falls within the 40th pull-in range, only the data table (B) is searched. In this case, the frequency is searched 40 to 41 times, but since this frequency corresponds to the 22nd vicinity in the data table (A), the frequency of the data table (A) is calculated 22 times by using the method of the present invention. In B), a total of 24 to 25 searches is required, which is 2-3 times, and the search time is greatly reduced.

The reason why the overlap ratio of the data table (B = standard) is about 50% is that the pull-in range of the PLL circuit is temperature-dependent, and the upper and lower limits of the pull-in range are set by the CPU 9 at room temperature. It is balanced about the same frequency centered around the frequency, but at high temperature the lower limit side of the pulling range narrows and at the same time the upper limit side widens, and at low temperature both the upper and lower limits of the pulling range narrow, and This is to prevent the pull-in range from changing due to the secular change of the device or the circuit parts, and to prevent discontinuity in the pull-in range.

[0016]

As described above, according to the image display device of the present invention, the pull-in range of the PLL circuit is searched using the data table in which the overlap ratio is set low, and the frequency to be locked is determined. After that, the standard overlap ratio data table is searched for the pull-in range that includes the above frequencies, and the optimum data is determined.Therefore, the dot clock frequency that should be supported in order to support signals of various horizontal frequencies In the case where the range is set wide and the frequency range is covered by a large number of pull-in ranges, the pull-in range can be searched a small number of times, and the time to lock can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of an embodiment of an image display device according to the present invention.

FIG. 2 is a conceptual diagram of a pull-in range of a PLL for explaining the operation of the image display device according to the present invention.

[Explanation of symbols]

 1 Horizontal sync signal (H-sync) input terminal 2 Phase comparator 4 Voltage controlled oscillator (VCO) 5 Clock generator 6 Frequency divider 7 Display circuit section 8 Storage section 9 CPU

Claims (6)

[Claims] 1. A clock generator that oscillates a dot clock, a phase comparator that inputs an output signal of the clock generator through a frequency divider and compares the phase with a horizontal synchronizing signal, and a signal based on the signal from the phase comparator. A voltage-controlled oscillator that oscillates at a specified frequency, a horizontal frequency determination unit that determines the frequency of the horizontal synchronizing signal, and a signal that is output from the voltage-controlled oscillator that is converted to a required frequency based on the determination signal from the horizontal frequency determination unit. And a storage unit for storing a dot clock frequency data table,
An image display device in which a plurality of data tables having different dot clock frequency intervals are stored in the storage unit, and the CPU switches the plurality of data tables from the storage unit and reads the data tables to control a clock generator. 2. The dot clock frequency data table stored in the storage unit is the clock generator,
PL consisting of frequency divider, phase comparator and voltage controlled oscillator
The pull-in range of the L circuit is set to be continuous with the adjacent pull-in range at the first overlap rate, and the pull-in range of the adjacent L-circuit is higher than the first overlap rate. The image display device according to claim 1, wherein the image display device is set to be continuous. 3. The dot clock frequency data table of the first overlap ratio stored in the storage unit sets the overlap ratio to 10%, and the dot clock frequency data table of the second overlap ratio overlaps. The image display device according to claim 2, wherein the ratio is set to 50%. 4. The first CPU from the storage unit by the CPU.
Reads the dot clock frequency data table of the overlap ratio of, controls the clock generator, and
The dot clock frequency at which the circuit is drawn is determined, and thereafter, the dot clock frequency data table of the second overlap rate is read out, and the clock generator is controlled by the data corresponding to the dot clock frequency determined by the CPU. Claim 2 or Claim 3
The image display device as described in the above. 5. A lock discriminating unit for discriminating lock / unlock of the PLL circuit is provided, and the CPU uses the unlock signal from the lock discriminating unit to detect the dot clock frequency data of another data table. The image display device according to claim 2, 3 or 4, wherein the clock generator is controlled. 6. The CPU according to claim 2, wherein the CPU serially transmits the dot clock frequency data read from the storage unit to the clock generator in order of increasing frequency, and varies the dot clock frequency.
The image display device according to claim 4 or 5.