JPH09160836A - Memory parity error monitoring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable discovering a memory error in an early stage by making it possible to confirm even the parity check error of a memory which has not been read, by means of one memory read. SOLUTION: When a read signal with a low level to a memory part 1 is inputted to an AND circuit 7 with a chip select 14, the output of the AND circuit 7 becomes a low level and the memories 1 and 4 are parity-checked by parity check parts 2 and 5. Since the chip select 14 is connected to an input/ output control part 3, data buses 11 and 13 are connected when the read signal with a low level is inputted and the input/output of data in the memory part 1 is enabled. In the meantime, since the level of the chip select 16 for the memory 4 is high one, the data buses 15 and 13 are interrupted by the input/output control part 6 and data of the memory part 4 is not inputted/outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory parity error monitoring device, and more particularly to a memory parity error monitoring device for monitoring parity errors of a plurality of memories.

[0002]

2. Description of the Related Art In a conventional memory parity error monitoring device, an error is monitored only in a memory area read from a memory.

Further, for example, JP-A-1-263854 and JP-A-63-187741 disclose techniques for monitoring parity errors in two memory areas, but the same applies to these techniques. It was

[0004]

However, with such conventional devices and techniques, it is not possible to monitor a memory that has not been read, so an error in the relevant memory is detected until the relevant memory is actually read. This was one of the causes of delaying the discovery of memory errors.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a memory parity error monitoring device which can detect a memory error at an early stage.

[0006]

In order to solve the above problems, the present invention provides a first storage means and a parity check of the first storage means by accessing the first storage means. The first parity check means, the first opening / closing control means for controlling opening / closing of the input / output data line to / from the first storage means, the second storage means, and the second storage means are accessed. Second parity check means for performing parity check of the second storage means, second opening / closing control means for controlling opening / closing of an input / output data line to / from the second storage means, and the first or Second
Both storage means are accessed by accessing either one of the storage means, and the opening / closing control means of the accessing side closes the input / output data line of its own, and the opening / closing control means of the one that has not accessed is Access control means for opening the input / output data line of its own.

[0007]

According to the present invention, when the first storage means is accessed, the access control means also accesses the second storage means, and both storage means are parity-checked by their respective parity check means. To be done. Also,
At the same time, the access control means closes only the input / output data line to / from the first storage means via the first opening / closing control means, so that the input / output of data is performed only to the first storage means.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. 1 is a block diagram of a first embodiment of a memory parity error monitoring device according to the present invention.

The memory parity error monitoring device comprises a memory unit 1, a parity check unit 2, an input / output control unit 3, a memory unit 4, a parity check unit 5, an input / output control unit 6 and an AND circuit 7.

The memory unit 1 includes an address bus 10, a data bus 11 and a common chip select (common access line) 1.
2 is connected to write and read data.

The parity check unit 2 has an address bus 1
0, data bus 11 and common chip select 12, create and save a parity bit at memory write to memory unit 1, read data from memory unit 1 at memory read to memory unit 1 and save at memory write Check the parity bit that is set to detect an error.

The input / output control unit 3 is connected to the data buses 11 and 13 and the chip select 14 (access signal line of the memory unit 1), and passes data only when the memory unit 1 is read and written, and does not pass other than that.

The memory section 4 includes an address bus 10, a data bus 15 and a common chip select (common access line) 1.
2 is connected to write and read data.

The parity check unit 5 uses the address bus 1
0, a data bus 15 and a common chip select 12, and creates and saves a parity bit at the time of memory write to the memory unit 4, and saves read data from the memory unit 4 at the time of memory read to the memory unit 4 and at the time of memory write. Check the parity bit that is set to detect an error.

The input / output control unit 6 is connected to the data buses 13 and 15 and the chip select 16 (access signal line of the memory unit 4), and passes data only when the memory unit 4 is read and written, and does not pass other than that.

The AND circuit 7 has its input side connected to the chip selects 14 and 16 and its output side connected to the common chip select 12.

Next, the operation of this monitoring device will be described. Explaining the case where the memory section 1 is read, a low-level access signal is input to the input / output control section 3 and the AND circuit 7 via the chip select 14.

As a result, the input / output control unit 3 first connects the data buses 11 and 13. Therefore, the memory unit 1
The read data from can be output to the outside through the input / output control unit 3. On the other hand, since the memory section 4 is not accessed, a high level signal is input to the input / output control section 6 via the chip select 16, so that the data buses 15 and 13 are cut off. Therefore, the read data from the memory unit 4 is not output to the outside.

Further, since one input of the AND circuit 7, that is, the chip select 14 becomes low level, the output of the AND circuit 7 also becomes low level. Therefore, since the low-level access signal is input to all the memory units 1 and 4 and the parity check units 2 and 5 via the common chip select 12, the memory unit 4 is read together with the memory unit 1. As a result, the parity check unit 2 detects an error by the read data of the memory unit 1 and the parity check data at the time of memory write, and at the same time, the parity check unit 5 performs the error detection by the read data of the memory unit 4 and the parity check data at the time of memory write. Error detection is performed.

Even when the memory section 1 is written (written), a low level access signal is input to the input / output section 3 and the AND circuit 7 via the chip select 14.

That is, the read or write determination signal is separately input to the memory section 1 together with the access signal. The same applies to the memory unit 4.

It should be noted that it is obvious that the same can be applied to the case where the memory section 4 is read, and the description thereof will be omitted.

Next, a second embodiment will be described. FIG.
FIG. 6 is a configuration diagram of a second embodiment. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

This embodiment shows a configuration in which three or more memory units are provided. That is, the memory unit 21 is the last memory unit, the parity check unit 22 is the parity check unit of this memory unit 21, and the input / output control unit 23 is the input / output control unit of this memory unit 21.

Then, the memory unit 21 and the input / output control unit 23
A data bus 31 is connected in between, and a chip select 32 is connected to the input / output control unit 23. Also, the memory unit 2
1, the input / output control unit 23, and other connections to the input / output control unit 23 are common.

Further, as many chip selects as the number of memory units are connected to the input side of the AND circuit 24.

With this configuration, by reading any one of the memory units, all the memory units are parity-checked via the AND circuit 24, and only the data bus requested to be read by each input / output control unit is read. Connected,
Since the others are cut off, only the data in the necessary memory section is read.

[0028]

According to the present invention, the two storage means each have a parity check means, and by accessing either one of these storage means, both storage means are accessed and accessed. Since the access control means for inputting / outputting only the data of the other storage means is provided, it is possible to confirm the parity check error of the memory which is not read by one memory read, and it is possible to detect the memory error early.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a memory parity error monitoring device according to the present invention.

FIG. 2 is a configuration diagram of a second embodiment of the same memory parity error monitoring device.

[Explanation of symbols]

 1, 4, 21 Memory unit 2, 5, 22 Parity check unit 3, 6, 23 Input / output control unit 7, 24 AND circuit

Claims (3)

[Claims] 1. To a first storage means, a first parity check means for performing a parity check of the first storage means by accessing the first storage means, and to the first storage means. A first opening / closing control means for controlling the opening / closing of the input / output data line, a second storage means, and a second parity check of the second storage means by accessing the second storage means. Parity check means, second opening / closing control means for controlling opening / closing of the input / output data line to / from the second storage means, and access to either of the first or second storage means The storage means is accessed, the opening / closing control means of the accessing side closes its own input / output data line, and the opening / closing control means of the non-accessing side opens its own input / output data line. Memory Parity error monitoring device comprising an access control means, to have a that. 2. The first and second storage means are configured to be accessed by a memory access means corresponding to each of the storage means, and the access control means,
2. The memory parity error monitoring device according to claim 1, wherein said first and second storage means are simultaneously accessed in response to said access. 3. The storage means, the parity check means, and the opening / closing control means are provided in three sets or more, and all the storage means are accessed by accessing any one storage means, and the accessed storage means side is the above-mentioned. 2. The opening / closing control means has an access control means for closing the input / output data line of its own, and the other opening / closing control means not accessed has an access control means for opening the input / output data line of itself. A memory parity error monitoring device as described.