JPH0916409A - Microcomputer - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide a microcomputer that switches tasks at high speed without increasing costs. [Structure] The CPU 4 has a task schedule table 2
The task is switched according to the execution order of, and the task is executed using one register set of the register file 3. Further, every time the task is switched, the register set used for the task execution of the CPU 4 is switched alternately.
Each time the task is switched, the transfer unit 5 uses the empty bus cycle of the CPU 4 to save and restore the register set, respectively. As a result, high-speed task switching can be realized simply by adding one register set and transfer means as hardware.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for executing a plurality of tasks while switching them.

[0002]

2. Description of the Related Art In recent years, microcomputers have been used in all kinds of equipment, and have been applied to more complicated control in a wider field with the improvement of processing capacity. Even in microcomputers for embedded applications, more sophisticated functions such as multitask management are desired so that more complicated control can be handled.

FIG. 6 is an explanatory diagram of a computer having a multitask function in the first conventional technique. In the figure, the CPU 10 includes an arithmetic unit 11 and a register set 12.
Consists of The calculation unit 11 executes the tasks one by one. The register set 12 holds data required for task execution.

The memory 13 has a context block 14 which is an area for saving contexts (register set data, PC contents, PSW contents, etc.) for each task. In the figure, the context save area for tasks 1 to 3 is shown in the context block 14. The task management in the first conventional example is performed by software (OS). For example, when switching from task 1 to task 2, when the OS receives an event (timer interrupt or the like) instructing task switching, first, C
The context of the task 1 is saved from the PU 10 to the memory 13, then the context of the task 2 is restored from the memory 13 to the CPU 10, and the execution of the task 2 is started.

As described above, in the first conventional example, since multitasking is realized by software (OS),
There is an advantage that the hardware scale can be small. FIG. 7 is an explanatory diagram of a computer having a multitasking function in the second conventional technique. In the figure, the CPU 20
Is composed of an arithmetic unit 21, a register file 22, a register set switching unit 23, and a control unit 24.

The calculation unit 21 executes tasks one by one. The register file 22 is composed of a plurality of register sets that hold data required for task execution. The register set switching unit 23 enables the register set corresponding to the currently executing task. Only this valid register set is used for the arithmetic unit 21.

The control unit 24 controls switching of tasks. The memory 25 has a context save area excluding register set data. The task management in the second conventional example is performed by hardware. For example, when switching from task 1 to task 2, the control unit 24
When receiving an event (timer interrupt or the like) instructing the task switching, the command instructs the register set switching unit 23 to validate the register set corresponding to the task 2, and the contents of the PC of the operation unit 21, the PSW Save the contents, etc. in the memory 25 and save the contents of the PC of task 2 and PS
The contents of W and the like are returned to the arithmetic unit 21. As a result, the arithmetic unit 21 executes the task 2 using the valid register set 2.

As described above, in the second conventional example, since multitasking is realized by hardware, there is an advantage that tasks can be switched at high speed.

[0009]

However, according to the above-mentioned prior art, there is a problem that it is not suitable for multitask management in a microcomputer for embedded use. More specifically, according to the first conventional example, the context save and restore are realized by software (OS) at the time of task switching, so that the switching speed is slow, and the microcomputer for embedded use for performing control requiring real-time performance is realized. Is not suitable. Also,
According to the second conventional example, since a register set having the same number of tasks is required and the control unit for switching tasks is realized by hardware, the hardware scale becomes large.
As a result, the cost is high, and the microcomputer is not suitable for embedded microcomputers.

In view of the above problems, it is an object of the present invention to provide a microcomputer that switches tasks at high speed without increasing costs.

[0011]

In order to solve the above-mentioned problems, the invention of claim 1 is a microcomputer which executes a plurality of tasks while switching them in order, and has the same register configuration, and one of them can execute a task. Two register sets used, a switching means for switching the register set used for task execution to the other simultaneously with task switching, and an internal bus connected to the register set,
And a detection means for detecting an empty cycle of each memory bus connected to the memory, and an empty cycle of the detected bus is used every time the task is switched, and the data of the register set not used for task execution is stored in the memory. And a transfer unit that saves and restores data for a task to be executed after the next switching from the memory to the register set.

According to a second aspect of the present invention, in the first aspect, the transfer means reads register data of a register set which is not used for task execution in an empty cycle of the internal bus, and an empty cycle of the memory bus. In, memory writing means for writing the data read by the register reading means to the memory,
After the writing by the memory writing means is completed, in the empty cycle of the memory bus, the memory reading means for reading the data for the task to be executed next from the memory and the data read by the memory reading means in the empty cycle of the internal bus , Register writing means for writing to a register set that is not used for task execution.

According to a third aspect of the present invention, there is provided a microcomputer which executes a plurality of tasks while sequentially switching the tasks.
A memory that stores a plurality of task programs and has a data save area corresponding to each task, a table means that stores the execution order of a plurality of tasks, two register sets that have the same register configuration, and the execution of the table means. A central processing unit that switches the tasks according to the order and executes the tasks using one of the register sets; and a switching unit that alternately switches the register set used for the task execution of the central processing unit at each task switching.
Detecting means for detecting empty cycles of the internal bus connected to the register set and the memory bus connected to the memory, and the empty cycle of the detected bus is used for each task switching and used for task execution. The data in the register set that has not been switched is saved in the data save area corresponding to the task before switching, and after being saved by the save means, the detected empty cycle of the bus is used to execute it by the central processing unit. And a restoring unit that restores the data in the data save area corresponding to the task next to the task to the register set that is not used for executing the task.

According to a fourth aspect of the present invention, in the third aspect, the memory has the data save area in a stack area for each task, and the table means corresponds to an execution order of tasks and each task. And the contents of the stack pointer to be stored. According to a fifth aspect of the present invention, in the third or fourth aspect, the evacuation unit is an empty cycle of the internal bus,
Register reading means that sequentially reads the register data of the register set that is not used for task execution, and the data read by the register reading means in the empty cycle of the memory bus in order to the data save area corresponding to the task before switching. And a memory writing unit for writing, wherein the restoring unit writes data in a data save area corresponding to a task next to the task being executed by the central processing unit in an empty cycle of the memory bus after the writing by the memory writing unit is completed. Memory reading means for reading from the memory in order, and data read by the memory reading means in an empty cycle of the internal bus,
Register writing means for writing to a register set not used for task execution.

According to a sixth aspect of the present invention, in addition to the third, fourth or fifth aspect, a clock supply means for supplying an operation clock to the central processing means, and the central processing means during the returning operation by the returning means. When task switching occurs, a stop means for stopping the supply of the operation clock of the clock supply means until the restoration operation is completed.

[0016]

By the above means, in the microcomputer according to the first aspect of the invention, the switching means switches the register set used for task execution at the same time as the task switching. Each time the task is switched, the transfer means uses the detected empty cycle of the bus to save the data of the register set not used for task execution to the memory,
After the next switching, the data for the task to be executed is restored from the memory to the register set. As a result, high-speed task switching can be realized simply by adding one register set and transfer means as hardware.

According to a second aspect of the present invention, in the transfer means of the first aspect, the register reading means and the memory writing means perform saving, and the memory reading means and the register writing means perform restoration. . At that time, register reading means,
The register writing means accesses the register in the empty cycle of the internal bus, and the memory reading means and the memory writing means access the memory in the empty cycle of the memory bus. As a result, saving and restoring can be realized without hindering task execution.

In the microcomputer according to the third aspect of the present invention, the central processing unit switches the task according to the execution order of the table unit and executes the task using one of the register sets. The switching means alternately switches the register set used for task execution of the central processing unit each time the task is switched. Each time the task is switched, the save means and the restore means perform save and restore, respectively, by utilizing the detected empty cycle of the bus. As a result, high-speed task switching can be realized simply by adding one register set and transfer means as hardware.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the data save area is provided in a stack area for each task in the memory, and the table means sets the execution order of the tasks. The contents of the stack pointer corresponding to each task are stored. As a result, the task occupancy rate in the central processing unit can be easily controlled by simply specifying one task as the task execution order.

According to a fifth aspect of the present invention, in the microcomputer according to the third or fourth aspect, the saving is performed by the register reading means and the memory writing means, and the restoration is performed by the memory reading means and the register writing means. At this time, the register reading unit and the register writing unit access the register in the empty cycle of the internal bus, and the memory reading unit and the memory writing unit access the memory in the empty cycle of the memory bus. As a result, saving and restoring can be realized without hindering task execution.

In the microcomputer according to the sixth aspect of the invention, the stopping means supplies the clock until the returning operation is completed when the central processing unit switches the task during the returning operation by the returning means. The supply of the operating clock of the means is stopped. This saves
Even if a task switching request is made in a cycle shorter than that required for restoration, the task can be switched appropriately, so that the task switching cycle can be set broadly.

[0022]

1 is a block diagram showing the main schematic configuration of a microcomputer according to an embodiment of the present invention.
This microcomputer has a memory 1, a task schedule table 2, a register file 3, a CPU 4, and a transfer unit 5. The memory 1 stores programs and data including a plurality of tasks, and has a save area for each task. In this save area, the context including the contents of the register set, the contents of the program counter, the contents of the processor status word, etc. is saved.

The task schedule table 2 is physically provided in the memory 1 and holds the execution order of tasks. The register file 3 includes a register set A and a register set B. These two register set A,
B is alternately switched every time the task is switched, and one of them is always used for task execution by the CPU 4.

The CPU 4 executes a plurality of tasks while sequentially switching them. The task executed by the CPU 4 is switched according to the contents of the task schedule table 2 each time an event instructing task switching occurs.
Here, the event is, for example, a periodic timer interrupt,
These include task switch instructions and specific port (serial port etc.) interrupts.

Each time the task is switched, the transfer unit 5 saves the data in the register set which is not used by the CPU 4 to the memory independently of the task execution by the CPU 4, and the data for the task to be executed next. From the memory to the register set. FIG. 2 is a block diagram showing a more detailed configuration of the microcomputer shown in FIG.

As shown in the figure, the microcomputer includes a ROM 101, a RAM 102, and an incrementer 4.
01, selector 402, instruction address buffer 403,
Instruction fetch buffer 405, processor status word (hereinafter abbreviated as PSW) 406, instruction buffer 40
7, instruction register 408, status register 409,
PLA410, micro instruction register 411, ALU4
12, ALOB413, operand address buffer 4
14, store buffer 415, load buffer 416,
Selector 417, transfer control unit 501, PLA 502, microinstruction register 503, TSTB 504, TSTP
505, an operand address buffer 506, a store buffer 507, a load buffer 508, an adder 509,
The ROM 101 and the RAM 102, which are composed of the constant generator 510, correspond to the memory 1 shown in FIG. 1, and have a program including a plurality of tasks, a task schedule table 2, and a task save area. This program is R
Task schedule table 2 stored in OM101
Are provided in the ROM 101 or the RAM 102, and the task save area is provided in the RAM 102.

Register set 301 and register set 3
02 has the same register configuration, and each has a data register (D1, D0) and an address register (A1,
A0), a stack pointer (SP), and a selector for selectively outputting data from these. A circuit portion including the incrementer 401, the selector 402, the instruction address buffer 403, and the instruction fetch buffer 405 is an instruction preparation unit that sequentially prefetches instructions from the ROM 101.

The status register 406 is a register having various flags indicating the operating state of the CPU 4. The circuit portion including the instruction buffer 407 is an instruction queue that holds a plurality of instructions prefetched by the instruction preparation unit. Instruction register 408, status register 40
The circuit portion including the PLA 410 and the micro instruction register 411 is an instruction control unit that decodes the instruction supplied from the instruction preparation unit or the instruction queue and controls its execution. In addition, this instruction control unit performs control for switching tasks according to the contents of the task schedule table 2 and control for alternately switching register sets each time an event for instructing task switching occurs. In this embodiment, the above event is 200 ms by a timer (not shown).
It is a periodic interrupt for each. The instruction control unit also controls the input / output of data to / from the internal bus 418.

The circuit portion including the ALU 412, the ALOB 413, the operand address buffer 414, the store buffer 415, the load buffer 416, and the selector 417 is an instruction execution unit that executes an instruction under the control of the instruction control unit. The internal bus 418 is composed of two buses and mainly transfers data to be read from and written to the register file 3.

The memory bus 419 is composed of an address bus and a data bus, and mainly includes the ROM 101 and the RAM 10.
2. Transfer addresses and data to peripheral circuits. The bus controller 420 arbitrates the bus usage when the accesses using the memory bus 419 compete, for example, when the prefetch by the instruction preparation unit and the load / store of operand data by the instruction execution unit compete. The bus controller 420 outputs various control signals for inputting / outputting data to / from the memory bus 419 by this arbitration.

The clock supply unit 421 supplies an operation clock to the CPU 4 and the transfer unit 5. Transfer control unit 50
1 includes a PLA 502 and a microinstruction register 503, and immediately after the task switching is performed by the instruction control unit, the contents of the register set not used by the CPU 4 are executed immediately before the switching. Of the task to be executed next to the currently executed task is restored to the register set.

The PLA 502 issues a microinstruction for realizing the save and restore. Micro instruction register 5
03 outputs a control signal corresponding to the micro instruction from the PLA 502. TSTB (Task Schedule Table Ba
se) 504 is a register that holds the start address of the task schedule table provided in the RAM 102.

TSTP (Task Schedule Table Pointe)
r) 505 is the task schedule table
This is a register that holds a pointer that points to a task to be executed next to the task that is currently being executed when a task switching request is issued. Operand address buffer (hereinafter D
An OAB (abbreviated as OAB) 506 holds a memory address at the time of saving and restoring and outputs it to the memory 1 via the address bus in the memory bus.

Store buffer (hereinafter abbreviated as DSTB)
Reference numeral 507 holds the data to be saved at the time of saving, and the data is stored in the memory 1 via the data bus in the memory bus 419.
Output to Load buffer (abbreviated as DSTB below)
At the time of the restoration, the data 508 inputs and holds the data to be restored read from the memory 1 via the data bus in the memory bus 419.

The adder 509 adds the contents of the DOAB 506 and the constant from the constant generator 510, and the addition result is D
Output to OAB506. As a result, the addresses of the individual data storage locations in the respective save areas are sequentially generated from the beginning at the time of saving and returning. FIG. 3 shows an example of a task schedule table and a memory map of a task save area.

In the figure, “TSTB” is a pointer that points to the start address of the task schedule table and is held in the TSTB 504. “TSTP” is a pointer that points to the task that should be executed next to the task that is currently being executed when the task switching request is issued.
Held at 505. "Task schedule table"
Holds the address indicating the stack pointer save location for each task in the order in which the tasks are executed, with x'FF at the end.
Holds (hexadecimal number). In the example of the figure, four tasks 1 to 4 are specified to be executed in the order of 1 → 2 → 3 → 1 → 4. In this example, task 1 is specified twice, so the CPU occupancy of each of tasks 1 to 4 is 4
It becomes 0%, 20%, 20%, 20%.

The "task save area" includes a "context save area" and a "stack pointer save area". The “context save area” is provided in the stack area for each task in this embodiment. That is, the stack area is used not only as a normal stack but also as a context save area. In the figure, the contexts of tasks 1 to 4 are A1 and A, respectively.
0, D1, D0, PSW, PC (This PC is IAB40
3 or the contents of the PFC 404).

The "stack pointer save area" stores the contents of the stack pointer for each task. In the figure, the contents of each stack pointer of tasks 1 to 4 are stored. The value of the stack pointer saved in this area indicates the start position of the context saving area for each task that is not currently executed. For example, when the value of the saved stack pointer for task 3 is immediately after switching from task 3 to task 1,
It indicates the top position of the stack area used in the execution of, but after the context save of task 3 is completed, it indicates the start position of the context save area. After that, after the context of task 3 is completely restored, the start position of the stack area of task 3 is indicated. It has no meaning during the execution of task 3.

In the figure, the context of task 3 is saved immediately after switching from task 3 to 1, and the context of task 4 to be executed is restored after the next task switching request is issued. At this time, the address of the context save area is designated by the DOAB 506, the save data is output to the memory 1 by the DSTB 507, and the restore data is input from the memory 1 by the DLDB 508.

FIG. 4 is a block diagram showing the functional configuration of the transfer control unit 501. The transfer control unit 501 is physically composed of the PLA 502 and the micro instruction register 503 shown in FIG. 2, but can be functionally represented as shown in FIG. The transfer control unit 501 includes an internal bus vacancy detection circuit 51, a memory bus vacancy detection circuit 52, a register read control unit 53, a memory write control unit 54, a memory read control unit 55, and a register write control unit 56.

The internal bus vacancy detection circuit 51 uses the internal bus 4
18 is empty (not used by CPU)
Detect cycles. More specifically, the internal bus vacancy detection circuit 51 determines that the internal bus control field of the micro instruction register 411 is vacant when the internal bus control field indicates NOP (no operation), and controls the register read control when it is vacant. The unit 53 and the register write control unit 56 are permitted to access the register. Here, the internal bus control field refers to a field of control signals for instructing data input / output to / from the internal bus among various control signal groups output from the micro instruction register 411. Further, NOP means a state in which all control signals in the field are inactive.

The memory bus empty detection circuit 52 detects a cycle in which the memory bus 419 is empty (not used by the CPU). More specifically, the memory bus vacancy detection circuit 52 determines that the memory bus control field of the bus controller 420 is vacant when the memory bus control field indicates NOP, and when it is vacant, the memory write control unit 54 and the memory read control. The unit 55 is allowed to access the memory. Here, the memory bus control field is a field including control signals for instructing data input / output to / from the memory bus among all control signal fields output from the bus controller 420.

When the internal bus vacancy detection circuit 51 permits access to the registers, the register read control unit 53 sequentially reads individual register data from the register set that is not used for CPU task execution, and the DSTB 507. To store. The memory write control unit 54 causes the memory bus availability detection circuit 52 to execute the memory 1
Access to DSTB 507 when access is allowed
The data stored in 1 is sequentially written in the context save area of the memory 1. At that time, the memory write control unit 54
First, the head address of the context save area of the task immediately before the currently executing task is set in the DOAB 506, and thereafter, the DOAB 506 is updated every time data is written.

After the context saving is completed, the memory read control unit 55, when the access to the memory 1 is permitted by the memory bus availability detection circuit 52, the memory 1
Data in sequence from the context save area of
Store in LDB 508. At that time, the memory read control unit 55 first sets the start address of the context save area of the task next to the currently executing task in the DOAB 506, and thereafter updates the DOAB 506 every time data is written.

The register write control unit 56 transfers the data of the DLDB 508 to the corresponding register of the register set which is not used for the task execution of the CPU when the access to the register is permitted by the internal bus vacancy detection circuit 51. Write in order. FIG. 5 is a flowchart showing task switching processing by the CPU 4 and detailed context saving / restoring processing by the transfer unit 5.

First, the task switching process will be described. When the task switching request is issued, the CPU 4
The contents of AB403 or PFC404 are saved in the stack area of the task as a return PC value at the time of task recovery, and the contents of PSW are also saved (step 501).
The register set used for task execution is switched to the other register set, and the transfer control unit 501 is activated (step 502). At this time, since the context of the task to be executed next has been restored to the new register set, the CPU 4 sets P from the stack area of the next task.
The execution of the next task is started by restoring the SW and the return PC value (step 503).

Then, the transfer unit 5 saves the context
The return process will be described. Note that each step marked "I" in the flowchart is executed in a cycle in which the internal bus vacancy detection circuit 51 detects that the internal bus is vacant, and each step marked "M" is a memory. This indicates that the processing is executed in the cycle in which the bus vacancy detection circuit 52 detects that the memory bus is vacant.

After the transfer unit 5 is activated, the register read control unit 53 reads the contents of the SP of the register set that is no longer used by the CPU due to the switching of step 502 and stores it in the DOAB 506 (step 504). At this time, the contents of DOAB 506 represent the start address of the context save area provided in the stack area. The register read control unit 53 and the memory write control unit 54 save the contents of each register of the register set in the context save area (steps 505 to 508).
Further, the memory read control unit 55 and the memory write control unit 54 save the contents of the DOAB 506 at this point in the stack pointer save area (steps 509 to 5).
11). As a result, the start address of the context saving area after saving is saved in the stack pointer saving area.
This completes saving the context.

Next, the memory read control unit 55 causes the TS
The contents of the TP 505 are updated to point to the next task to be executed currently (step 512), the start address of the context save area of the next task is read from the stack pointer save area, and stored in the DOAB 506 (step 513). . At this time, the content of DOAB506 is x '.
If it is FF (hexadecimal number), it indicates the end of the table, so the contents of TSTP 505 are updated to the start address held in TSTB 504, and then steps 513 are performed again (steps 514 and 515).

Further, the memory read control unit 55 and the register write control unit 56 restore each data in the context save area of the next task to the register set (steps 516 to 519). Further, the register write control unit 56 writes the contents of the DOAB 506 at this point in the SP of the register set (step 520). As a result, the start address of the stack area of the next task is set to SP. This completes the restoration of the context of the next task.

The task switching operation of the microcomputer according to the embodiment of the present invention configured as above will be described. Now, task schedule table 2
As shown in FIG. 3, the four tasks 1-4 are 1 → 2.
It is assumed that the execution is specified in the order of → 3 → 1 → 4 and that task 3 is being executed. If a timer interrupt occurs as an event requesting task switching in this state, the CPU 4 causes the task 3
The task 3 is switched to the task 1 by saving the return PC and PSW, switching the register set, and restoring the task 1 PSW and the return PC (steps 501 to 503 in FIG. 5).

The transfer unit 5 is started at the same time as the register set is switched, and while the task 1 of the CPU 4 is executing, the transfer unit 5 uses an empty cycle of the internal bus 418 and the memory bus 419,
As shown in FIGS. 3 and 5, the context saving process of the task 3 and the context restoring process of the task 4 are performed. As described above, according to the microcomputer of the present invention, the CPU 4 can switch the task only by saving / restoring the return PC and PSW and switching the register set. Realize fast task switching with very few. In addition, the hardware configuration required for task switching has an advantage that it can be realized with a smaller hardware scale because only one register set and a transfer unit are added. In this respect, it is particularly suitable for a one-chip microcomputer for embedded applications.

Further, since the transfer unit 5 saves and restores the context by utilizing the empty cycles of the internal bus and the memory bus during the task execution of the CPU 4, it does not hinder the task execution of the CPU at all. Can make the most of. Further, since the two register sets are alternately assigned to the tasks, there is no limit to the number of tasks executed by the CPU. Since the number of tasks is based on the provision of the context save area, the number of tasks can be increased as long as the memory capacity permits.

Further, by describing a plurality of the same tasks in the task schedule table 2, it is possible to easily control the CPU occupation time of the tasks. For example, in the example of FIG. 3, task 1 is described only in two places in the table, and the occupied time (40 times) of other tasks 2, 3, and 4 (40
%) Is secured. In the above embodiment, the event requesting task switching is a timer interrupt with a cycle of 200 mS. In the event cycle, since the transfer unit 5 transfers (saves / restores) the context by utilizing an empty cycle of the bus behind the task execution of the CPU 4, only a sufficient number of empty cycles of the bus are generated in the task execution. It is necessary to secure time. In the configuration of this embodiment, it is desirable that the event cycle be several hundreds μS to several mS or more.

In the above embodiment, the event is the timer interrupt, but other than this, it may be a task switch command, a specific port (serial port, etc.) interrupt, or the like. In the above embodiment, the task save area is divided into the SP save area and the context save area as shown in FIG. 3, but may be combined into one area. Although the task schedule table 2 is configured to store the address of the SP save area for each task, it may be configured to store the task number. In this case, a table may be provided for obtaining the address of the SP save area corresponding to the task number.

FIG. 8 is a block diagram not occupying a detailed configuration of a microcomputer in another embodiment of the present invention. The configuration of the figure is similar to that of FIG.
The difference is that a clock supply unit 422 is provided instead of the above, and a stop circuit 511 is added.
Except for these points, it is the same as the previous embodiment, and only different points will be described.

The clock supply unit 422 is the same in that the operation clock is supplied to the CPU 4 and the transfer unit 5, but
It differs from the CPU 4 in that the supply of the operation clock is stopped in accordance with an instruction from the stop unit 511. The stop unit 511 is
When an event requesting task switching occurs during the transfer operation of the transfer unit 5, the clock supply unit 422 stops the clock supply to the CPU 4 until the transfer operation ends. Specifically, the transfer unit 5 internally has a transfer flag indicating that the transfer operation is in progress, and the transfer flag is set at the start of saving and reset at the end of return. Further, the stop unit 511 instructs the clock supply unit 422 to stop the supply of the operation clock to the CPU 4 when the timer interrupt signal indicating the event is active and the flag is set. After that, when the flag is reset, the stop instruction is released.

The operation of the microcomputer of this embodiment constructed as described above will be described below. The save / restore operation by the transfer unit 5 is exactly the same as in the previous embodiment. During this save / restore operation, it is assumed that a timer interrupt requesting task switching occurs. In this case, the stop 511
Instruction, the clock supply unit 422 stops the supply of the operation clock to the CPU 4. This causes the CPU 4 to
Stop the operation. Since the operation clock is supplied to the transfer unit 5, the flag is reset after the restoration operation is completed. As a result, the stop unit 511 releases the stop instruction, and the operations of task switching and task execution by the CPU 4 are restarted.

As described above, in the present embodiment, when an event requesting task switching occurs before the transfer operation by the transfer unit 5 is completed, the operation of the CPU 4 is stopped to complete the transfer, and then the CPU 4 Restart the operation of. Accordingly, when the transfer time of the transfer unit 5 is shorter than the event occurrence interval, task switching can be appropriately executed. For example, if the event is an interrupt that occurs irregularly rather than a periodic interrupt, or if the internal bus 4
18. If there is a task (a task in which memory data is mostly transferred) in which a free cycle of the memory bus 419 hardly occurs, the processing capacity of the CPU 4 is reduced by the amount of the operation stopped, Appropriate task switching can be performed.

[0060]

As described above, according to the first aspect of the present invention, high-speed task switching can be realized only by adding one register set and transfer means as hardware. effective. Especially in a microcomputer for embedded use, high-speed switching of tasks can be realized even if there is a restriction on the hardware scale, and thus real-time control is possible in the device at the embedded destination.

According to the second aspect of the present invention, in addition to the effect of the first aspect, there is an effect that the saving and restoring can be realized without hindering the task execution at all. According to the invention of claim 3, there is an effect that high-speed task switching can be realized only by adding one register set and transfer means as hardware. Especially in a microcomputer for embedded use, high-speed switching of tasks can be realized even if there is a restriction on the hardware scale, and thus real-time control is possible in the device at the embedded destination.

According to the invention of claim 4, in addition to the effect of claim 3, the task occupancy rate in the central processing unit can be easily controlled only by specifying a plurality of tasks as the task execution order. There is an effect. According to the invention of claim 5, in addition to the effect of claim 3 or 4, there is an effect that the saving and restoring can be realized without obstructing the task execution at all.

According to the invention of claim 6, in addition to the effect of claim 3, 4 or 5, the task can be switched appropriately even if a task switching request is generated in a cycle shorter than that required for save / restore. Therefore, the task switching cycle can be set widely.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main schematic configuration of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a more detailed configuration of the microcomputer in the embodiment.

FIG. 3 shows an example of a task schedule table and a memory map of a task save area in the embodiment.

FIG. 4 is a block diagram showing a functional configuration of a transfer control unit 501 in the embodiment.

FIG. 5 is a flowchart showing a task switching process by the CPU 4 and a detailed context save / restore process by the transfer unit 5 in the embodiment.

FIG. 6 is an explanatory diagram of a computer having a multitask function according to a first conventional technique.

FIG. 7 is an explanatory diagram of a computer having a multitask function according to a second conventional technique.

FIG. 8 is a block diagram showing a detailed configuration of a microcomputer according to another embodiment of the present invention.

[Explanation of symbols]

 1 memory 2 task schedule table 3 register file 4 CPU 5 transfer unit 51 internal bus vacancy detection circuit 52 memory bus vacancy detection circuit 53 register read control unit 54 memory write control unit 55 memory read control unit 56 register write control unit 422 clock supply unit 501 transfer control unit 502 PLA 503 micro instruction register 504 TSTB 504 step 505 TSTP 506 DOAB 507 DSTB 508 DLDB 509 adder 510 constant generator 511 stop unit

Front page continuation (72) Inventor Masahiko Matsumoto 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (6)

[Claims] 1. A microcomputer for executing a plurality of tasks while switching them in order, and two register sets having the same register configuration, one of which is used for task execution, and the other of which is used for task execution simultaneously with task switching. Switching means for switching the registered register set to the other, detecting means for detecting an empty cycle of each of the internal bus connected to the register set and the memory bus connected to the memory, and a detected bus for each task switching. A transfer means for saving data of a register set that is not used for task execution to a memory by utilizing an empty cycle and restoring data for the task to be executed from the memory to the register set after the next switching is provided. Microcomputer characterized by. 2. The transfer means reads register data of a register set which is not used for task execution in an empty cycle of the internal bus and register read means in an empty cycle of the memory bus. Memory write means for writing the data to the memory, and memory read means for reading the data for the next task from the memory in the empty cycle of the memory bus after the completion of the writing by the memory write means, and memory read in the empty cycle of the internal bus 2. The microcomputer according to claim 1, further comprising register writing means for writing the data read by the means to a register set that is not used for task execution. 3. A microcomputer for executing a plurality of tasks while switching them in order, storing a plurality of task programs, a memory having a data save area corresponding to each task, and an execution order of the plurality of tasks. A table means, two register sets having the same register configuration, a central processing unit for switching tasks according to the execution order of the table means and executing the task using one of the register sets, and a central processing unit for each task switching. Switching means for alternately switching the register set used for executing the task of the arithmetic processing means, detection means for detecting an empty cycle of each of the internal bus connected to the register set and the memory bus connected to the memory, and task switching Each time, the empty cycle of the detected bus is used to execute the task execution. A central processing unit that saves the data of the register set that is not used for saving to the data saving area corresponding to the task before switching and the detected empty cycle of the bus after saving by the saving unit. And a restoring means for restoring the data in the data save area corresponding to the next task of the task under execution to the register set not used for task execution. 4. The memory has the data save area in a stack area for each task, and the table means stores an execution order of tasks and contents of a stack pointer corresponding to each task. The microcomputer according to claim 3, wherein 5. The saving means reads the register data of a register set which is not used for task execution in order in the empty cycle of the internal bus, and the register reading means in the empty cycle of the memory bus. Memory recovery means for sequentially writing the stored data to the data save area corresponding to the task before switching, and the recovery means is a central processing unit in an empty cycle of the memory bus after the writing by the memory writing means is completed. The memory read means for sequentially reading the data in the data save area corresponding to the next task of the task under execution from the memory from the memory and the data read by the memory read means in the empty cycle of the internal bus are used for the task execution. Cash register to write to no register set Claim 3 or 4 microcomputer wherein a and a data writing means. 6. The microcomputer further comprises a clock supply means for supplying an operation clock to the central processing means, and a recovery operation when the central processing means switches the task during the recovery operation by the recovery means. 6. The microcomputer according to claim 3, further comprising stop means for stopping the supply of the operation clock of the clock supply means until the operation is completed.