JPH0916441A - Memory dump system - Google Patents

Abstract

(57) [Summary] [Purpose] If one CPU system in a triplicated operation in a redundant configuration of three CPU systems is disconnected due to a failure, etc., that CPU
This makes it possible to read the memory contents of the system and execute a memory dump for transferring the memory contents of the CPU system separated to another system without providing a common global memory or the like as a reading means. [Composition] A dump source start address register 133, a dump destination start address register 134, and a dump end address register 135 are provided in an input / output control unit in each CPU.
Sequential +1 counter to the address stored in register 133
Data is read from the local memory while counting up by 137. At this time, the address stored in the register 134 is sequentially counted up by the +1 counter 141 and sent to the other system memory together with the read data. The memory dump is performed by continuing this process until the address stored in the register 135 is reached.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory dump system, and more particularly to a memory dump system in an information processing system for improving the reliability of the entire system by providing a plurality of CPUs (central processing units) in a redundant configuration. It is about.

[0002]

2. Description of the Related Art A conventional redundant information processing system of this type is a so-called fault tolerant computer (F
TC) system, for example, Japanese Patent Laid-Open No. 2-
202637, JP-A-3-015946,
JP-A-3-050916 and JP-A-64-046
A CPU having a redundant configuration, which is disclosed in Japanese Patent No. 844, etc.
This is a technique for improving the reliability of the entire system by taking a majority decision of a plurality of outputs (also called an information processing subsystem) and selectively adopting an output that matches the majority decision.

For example, referring to the technique disclosed in Japanese Patent Laid-Open No. 2-20637, FIG. 8 shows the entire system configuration, and three CPU subsystems (CPU-a,
b, c), two global memories (global memories # 1, # 2), a plurality of I / O processors (I / O processors # 1, # 2, # 3), and a plurality of I / O controllers. It consists of

Each CPU subsystem has a local memory inside, and each local memory cannot be directly accessed from other CPU subsystems. These three CPU subsystems are stored in the local memory. It has a core OS program,
The three CPU subsystems operate by independent clocks CK.

Fault tolerant is realized by causing three CPU subsystems, which originally operate independently, to perform the same operation in synchronization with each other and to majority the behavior of the CPU subsystem.

Due to this majority decision, global memory #
1 and # 2 are provided, and global memory has 3 CPs.
It is accessible from the U subsystem and page swaps to and from local memory. Specifically, the user program and data used by the user program are stored. The majority access to the global memory from the 3CPU subsystem is decided by the global memory.

Each of the two global memories has a plurality of I's.
The I / O processor is connected by a bus, and the bus between the global memory and the I / O processor is duplicated.

The DMA operation of the peripheral device (disk device under the I / O controller) is performed by the I / O processor and the I / O processor.
Only via the / O controller to global memory, no DMA operation from peripherals to each local memory in the CPU subsystem.

Each access to a register in the global memory, a register in the I / O processor, and a register in the I / O controller is performed, and these accesses are largely decided by the port circuit in the global memory. ing.

The global memory is duplicated and has a 1: 2 connection configuration with each CPU subsystem, and one is defined as "primary" and the other is defined as "backup". Writes to the global memory from the CPU subsystem are made to both, and reads from the global memory are made from the primary. At the time of reading, the backup side internally performs the read operation, but does not output the read data and returns only the status to the CPU subsystem.

The write operation from the I / O processor to the global memory is performed for both the primary and backup by using the duplicated bus. For the read operation, data from both memories is received and the data on the primary side is used.

Here, the memory copy between the two global memories is executed in a two-step process. As an example, when performing a memory copy from global memory # 1 to # 2, global memory # 1 is used as the first step.
Are read by the processor and written to both the global memories # 1 and # 2. The global memories # 1 and # 2 are defined as primary and backup, respectively, even in normal operation. Reads are read from whichever is defined as the primary, and writes are written to both the primary and backup. Be seen. In the first step, all writes originating from the IO bus are ignored.

The second step is the same as the first step, except that a write from the IO bus is also executed. When this second step is designated from the beginning to the end of the address of the global memory, the global memories # 1 and # 2 have the same contents. The first and second steps are designed to be inserted into the task being executed while the normal operation is in progress.

The local memory of each processor does not have a memory copy function between these local memories.
By copying the contents of the local memory of two normal processors to the global memories # 1 and # 2 and then resetting each processor, the contents of the local memory are cleared. When all the processors are synchronized after the reset, the contents copied to the global memories # 1 and # 2 are copied back to the local memory, so that the contents of the local memory of each processor become the same.

[0015]

In the conventional configuration as described above, in order to make a memory copy of the contents of the local memory in the stage preceding the majority logic circuit, the stages after the majority logic circuit are accessed from all of the triplexing modules. It is necessary to provide possible global memory.

In memory copying, the contents of normal local memory are once copied to global memory, the contents of all local memories are cleared, and then the contents copied to global memory are returned to all local memories. Therefore, it is impossible to transfer the contents of one local memory to another local memory.

Here, the memory dump function targeted by the present invention is a function of transferring a part of the memory contents of a certain CPU subsystem system to the memory of another CPU subsystem system. This memory dump function is necessary for some C
This is a case where when a failure occurs in the PU subsystem system, the CPU subsystem system is separated from the system, and information necessary for failure analysis of the CPU subsystem system is collected.

However, C which is separated from normal operation
The memory contents of the PU subsystem system cannot be directly confirmed. Further, it is not possible to access the file device or the like connected to the peripheral control device and store the memory contents. Therefore, the function of copying the memory contents of the CPU subsystem that is separated to the memory of another system that is operating normally, that is, the memory dump function, collects the necessary information and collects the collected data in the file device. It becomes possible to store.

The memory dump function transfers a part of the memory data from the faulty CPU subsystem system which is separated from the normal operation to the CPU subsystem system which is normally operating. It becomes the transfer of data.

When performing such a memory dump operation,
The above conventional technique has a problem in that the contents of the local memory of one CPU subsystem cannot be directly transferred to the local memory of another.

An object of the present invention is to provide a memory dump system in an information processing apparatus capable of directly transferring the contents of one local memory to another local memory with a simple structure without requiring a global memory. Is.

[0022]

According to the present invention, at least three redundant information processing subsystems, an input / output bus, and a plurality of peripheral control devices connected to the input / output bus are provided. These information processing subsystems are provided in common to a plurality of peripheral control devices, and the input / output buses are connected to each other to execute the majority logic of the output from each of the information processing subsystems to the peripheral control device. Each system of the information processing subsystem, including a bus interface device, includes an arithmetic processing unit that executes arithmetic processing, a memory that stores program data, a transaction that accesses the peripheral control device from the arithmetic processing unit, and A memory in an information processing device having an input / output control unit for controlling a transaction for accessing the memory from the peripheral control device And an instruction means for instructing the start and end of a memory dump for transferring the contents of the memory of its own system to the memory of another system, and a start instruction of the memory dump. Until the end instruction, the memory dump control means for sequentially reading the contents of the own system memory and sending the contents to the bus interface device, wherein the bus interface device has the contents of the memory sent from the input / output control unit. A memory dump system is provided which has a sending control means for sequentially sending the data to the memory of the other system.

The instructing means has means for holding a memory dump source start address, a memory dump destination start address, and a memory dump end address, which have been instructed in advance, respectively, and the memory dump control means has the Means for reading data from the own system memory while sequentially updating the memory tamping source start address to the memory dump end address, means for sequentially updating the memory dump destination start address, and the updated memory dump destination address and read data Is sent to the bus interface device.

[0024]

When dumping the contents of the memory in a certain 1-system information processing subsystem to the memory of another system, the I / O control unit in the 1-system information processing subsystem transfers the contents of its own memory to another system. The start and end of the memory dump to be transferred to the memory is instructed, and from the start to the end of this memory dump, the contents of the own system memory are sequentially read out and sent to the bus interface device. By sequentially controlling the sending of the memory contents to the memories of other systems, data transfer between the memories becomes possible directly.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention. In FIG. 1, arithmetic processing units (EPU) 100a, 100b, 100c for executing arithmetic processing and memories 101a, 101b, 1 for storing program data.
01c, an IO transaction for accessing the peripheral control unit (PCU) from the EPU, and a DMA (direct memory access) transaction for accessing the memory from the PCU (I / O control unit (B)
3 including IU) 103a, 103b, and 103c, respectively.
A system information processing subsystem (hereinafter, simply referred to as CPU) is configured.

Each of these EPUs, memories, and BIUs has an MP bus 102a, 10 having a cache coherency function.
2b and 102c are connected to each other. These three systems of redundantly configured CPUs operate synchronously with a synchronous clock and execute the same program to perform a triplicate operation.

The plurality of PCUs are connected to the bus interface adapter (BIA) 10 via the IO buses 108 to 111, respectively.
4 to 107 and these BIA 104 to 1
07 has a function of taking a majority logic for access from each tripled CPU system to the PCU. As long as there is no failure, the access from each CPU system is the same, but if a failure occurs in any of the CPU systems, the failure is found by the majority logic and the access is different from the other two normal CPU systems. CPU system is considered to be faulty.

Access from each CPU system to the PCU is BI
It becomes one by the majority logic in A and accesses the PCU. Access to the memory from the PCU is executed as a transaction from the BIA to all CPU systems. To this end, each BIA has three input / output ports for the CPU system.

In the above structure, the BIUs 103a, 103b, 10 having important functions related to the memory dump.
3c will be described in more detail. The BIU has an NA bus, which is an intermediate bus, inside, and the interface control between the MP bus and the NA bus is performed by an IAC (interface address controller) and an IDB (interface data buffer: IO cache). Under the NA bus, a plurality of TIUs (triple redundancy interface units) for controlling the interface with the BIA and the interface with the NA bus are connected. Each TI
Us are connected to different BIAs, and the same TIUs are connected to the same BIA as the system configuration of each CPU system.

In this system, when a failure occurs in the CPU system, it is detected by BIA, the failed CPU system is disconnected, and the remaining two CPU systems continue to operate. In the CPU system where the failure occurs, after the cause of the failure is removed,
It is designed to be installed in the system again and return to triple operation.

The memory dump function of the present invention is an I in BIU.
This IAC will be described with reference to the block diagram of FIG. NA bus slave control unit 120 is NA
IAC receives from bus 121 (ie TIU to I
Control transactions (issued to AC). N
Transactions received from the A bus include DMA read / write transactions, IO read response transactions, and interrupt transactions. IO
In the case of a read response transaction or an interrupt transaction, the internal request control unit 123 is instructed to make an internal request of the IAC for issuing the transaction to the MP bus 122.

In the case of a DMA read / write transaction, control is transferred to the DMA controller 124. This is because the IAC is provided with an IO cache in order to improve the efficiency of memory access, and therefore a cache hit check is performed for a DMA transaction. D
The MA control unit 124 sends DM to the IO cache control unit 125.
Instruct to perform hit check of A transaction.

When the IO cache controller 125 misses a DMA transaction, it is necessary to execute an MP bus transaction for making a read request to the memory in order to read the data required for cache. Therefore, the internal request control unit 123 is instructed to make an internal request to execute the MP bus transaction.

In this way, in the case of a mishit, new data is read into the cache. Therefore, if all entries in the cache are used (all entries are valid), some of the entries must be invalidated. If the cached data for the entry selected to be invalidated has already been modified, it must be written back to memory. Therefore, in the above case, the internal request control unit 1 executes an internal request to issue an MP bus transaction for writing back the data of the selected cache.
Give instructions to 23.

The internal request control unit 123 arbitrates each internal request, and the MP for the selected internal request as a result is arbitrated.
A bus transaction request is sent to the MP bus master controller 1
Go to 26. The MP bus master control unit 126 issues the MP bus transaction requested by the internal request control unit 123 onto the MP bus.

When the IO cache controller 125 has a cache hit in the DMA write transaction, the DMA write data is written in the entry of the hit cache. When the DMA read transaction hits the cache, the data response is executed on the NA bus 121.

A transaction that misses a cache in a DMA read / write transaction waits for data to be replied from the memory. When the MP bus slave control unit 127 receives the data reply from the memory, the control is transferred to the IO cache control unit 125, and I
The O-cache control unit 125 stores the reply data from the memory in the cache.

In the case of a DMA write transaction,
Thereafter, the DMA write data is written in the cache entry storing the reply data, and the DMA write transaction is completed. In the case of a DMA read transaction, the DMA response control unit 128 is instructed to make a response to the DMA read transaction, and the DMA response control unit 128 issues a DMA read response transaction to the NA bus to the NA bus master control unit 129. Give instructions. The NA bus master control unit 129 issues a DMA read response transaction to the NA bus, and the DMA read transaction ends.

When the MP bus slave controller 127 receives the IO read / write transaction, it transfers control to the IO controller 130, and the IO controller 130 instructs the NA bus master controller 129 to execute the IO transaction. N for IO write transaction
When the A bus master control unit 129 issues an IO write transaction to the NA bus, the process is completed.

N for IO read transaction
When an IO read transaction is issued to the A bus, I
Wait for the O read response transaction to come back. When the NA bus slave control unit 120 detects the IO read response transaction, it makes an internal request to the internal request control unit 123, and the internal request control unit 123 makes the IO request.
M is the MP bus transaction for read response
Request to the P bus master control unit 126. When the MP bus master control unit 126 issues a response transaction for IO read on the MP bus, a series of IO read transactions is completed.

The above is a description of the normal functions of the IAC.
The description of the memory dump control unit 131 of FIG. 2 will be given below with reference to FIG.
The block diagram of FIG. The memory dump control unit includes a memory dump control register 132, a dump source start address register 133, a dump destination start address register 134, and a dump end address register 135 that can be set by software.

The memory dump control register 132 is a register for instructing the start and stop of the memory dump. This register is the last one to be set by the above software.

The dump source start address register 133 is a register indicating an address at which the dump source memory dump is started. Since the IAC has an IO cache,
The dump source start address is given by the block address in consideration of the block size of the cache. The output of the dump source start address register 133 is stored in the dump source address register 136, and is incremented by +1 by the +1 counter 137 and the selector 138 so as to advance by the IO cache block size each time the memory dump operation is performed once. It The control of this count-up is controlled by the counter control unit 139. As a result, the memory dump is executed at consecutive addresses from the dump source memory dump start address.

The dump-destination start address register 134 is a register indicating the address at which the dump-destination memory dump is started. The dump destination start address is also given as a block address for the same reason as the dump source start address register 133. The output of the dump-destination start address register is stored in the dump-destination address register 140 and is incremented by +1 by the +1 counter 141 and the selector 142 each time a memory dump is executed, like the dump-source address register. The control for counting up is controlled by the counter control unit 143. As a result, the memory dump is executed at consecutive addresses from the dump destination memory dump start address.

The dump end address register 135 is a register indicating an address at which the dump source memory dump is ended. The dump end address is also given as a block address for the same reason as the dump start source address register. Here, the memory dump end operation will be described.

The value of the dump end address register which can be set by software and the value of the dump source address register which is incremented by +1 each time the memory dump operation is performed are compared by the dump end detection circuit 144 and coincide with each other. When the end of the memory dump is detected,
The memory dump ends.

Below, a schematic operation in the IAC of the memory dump requested by the memory dump control unit 131 is shown in FIG.
This will be described below. The memory dump is executed by using the control circuit of the DMA read transaction. Since the CPU system that is executing the memory dump is a system that has stopped due to a failure, only the own IAC is operating. Therefore,
The IAC prohibits all requests from the agent side on the NA bus and does not release the NA bus to the agent.

Therefore, from the memory dump control unit 131 to N
When a memory dump request is instructed to the A bus master control unit 129, the NA bus master control unit 129 causes the NA bus 12
Get 1 When the NA bus 121 is acquired, the DMA control unit 12 can receive the DMA read transaction as in the case of receiving the DMA read transaction.
Control is transferred to 4.

Like the DMA read at the time of a cache miss, the MP cache master control unit 126 issues an instruction to the internal request control unit 123 from the IO cache control unit 125 to read the data of the memory dump source address from the memory. A coherent block read (CR) transaction (reading while keeping each cache consistent) is issued on MP bus 122. If there is a data reply from the memory, it is executed at this time as well as the DMA read transaction.

However, since the address actually issued to the NA121 bus is the value of the dump destination address register 140, the DMA controller 124 reassigns the address. Therefore, the DMA control unit 124 holds the dump source address issued to the MP bus 122 and the dump destination address issued to the NA bus 121 as a pair.

The transaction executed by the NA bus master control unit 129 on the NA bus 121 through the DMA response control unit 128 is not a DMA read response transaction but an IO transaction having a data length of 64 bytes. This is because an IO transaction having a data length of 64 bytes is defined as a memory dump transaction, and is distinguished from other transactions by the TIU under the NA bus and the BIA ahead of it.

The maximum data length of an IO transaction is O
Depends on S or EPU, but currently 64
The maximum is 8 bytes of bit architecture. Since an IO write transaction with a data length of 64 bytes is a transaction that does not actually exist, this transaction is defined as a memory dump transaction.

The operation of BIA will be described with reference to the block diagram of FIG. As is clear from the system configuration diagram of FIG. 1, there is a TIU between the IAC and the BIA, but this TIU only has a relay function.
The IU has no special function related to the present invention, and thus its operation description is omitted.

In BIA, CPU0 system, CPU1 system, C
Upon receiving the requests from the PU2 systems, the requests are held in the request 0 register 145, the request 1 register 146, and the request 2 register 147, respectively.
The output of each request register is received by the arbitration circuit 148,
The arbitration circuit 148 arbitrates each request.

In the arbitration result register 149, the arbitration circuit 1
Based on the output of 48, the CPU system that holds the request is held. Finally, the memory dump destinations are the two CPU systems for which no request has come. In the normal function, the information in the arbitration result register is also used for voting (majority decision).

Transaction data from the CPU0 system, the CPU1 system, and the CPU2 system are held in the down data 0 register 150, the down data 1 register 151, and the down data 2 register 152, respectively. The meaning of transaction data is different in each phase and is transferred in the order of access code, address, and data.

The outputs of the down data 0, 1, 2 registers are compared and checked by the comparison circuits 153-155, and V is determined by the result and the output of the arbitration result register 149.
The majority decision logic is taken by the starting decision circuit 156. Normally, during the triplicate operation, the arbitration result register 149
Indicates that there are requests from all three CPU systems, and all outputs of the down data 0, 1, 2 registers are valid.

However, at the time of the memory dump, the arbitration result register 149 indicates that there is a request from only one CPU system, and as a result, in the voting determination circuit 156, only the CPU system that has made the request is subject to the voting. The voting determination circuit 156 is
As a result, the data selection circuit 157 is instructed to select the data of the CPU system selected. The data selection circuit 157 selects and outputs the output of the down data register of the CPU system instructed by the voting determination circuit 156.

The down control unit 158 first determines whether it is a memory dump transaction or a normal transaction based on the access code received from the data selection circuit 157 in the first phase. In the case of a memory dump transaction, that is, an IO write transaction having a data length of 64 bytes, the data buffer is instructed to store the address and data following the next phase and thereafter. In the case of a normal transaction, the output buffer 166 is instructed to store the address and data following the next phase and thereafter.

In the case of a memory dump transaction,
The down control unit 158 instructs the memory dump destination determination circuit 159 to determine the memory dump destination, and the memory dump destination determination circuit 159 determines the memory dump destination based on the content of the arbitration result register 149. The memory dump destination is the CPU system that has not received the request in the arbitration result register. That is, the memory dump is automatically executed from the CPU system that has output the data to the CPU system that has not output the data. The memory dump destination determined by the memory dump destination determination circuit 159 is held in the memory dump destination register 160.

The data buffer 161 has a down controller 15
The address and the data are stored according to the instruction from 8, and it is output to the access code conversion circuit 162. The access code conversion circuit 162 converts an access code, which was an IO write with a 64-byte length in the memory dump transaction, into a DMA write with a 64-byte data length. The execution destination CPU system of the DMA write is executed only for the CPU system specified by the memory dump destination register 160.

Updater 0 register 163, updater 1 register 164, updater 2 register 165
The data length 64 from the access code conversion circuit 162 to the CPU system updater register specified in
A byte DMA write is executed, and a write to the memory for that CPU system is executed. After that, the DMA write is processed as usual.

The IAC will be described in detail with reference to the block diagrams of the IAC shown in FIGS. Prior to this explanation, the correspondence with FIG. 2 is shown below. However, one function in FIGS. 5 and 6 does not necessarily correspond to one function in FIG. 2 on a one-to-one basis. For example, the SW (software) visible register group 20 in FIG. It corresponds to the department.

NA bus slave controller: 1 to 4, 5, 5, 6, 8, 9, 20 DMA controller: 7, 9, 20, 50 IO cache controller: 10, 11, 20, 31, 32, 76 Internal Request control unit: 12, 13, 17, 20 MP bus master control unit: 14 to 16, 20 to 26, 45 MP bus slave control unit: 18 to 20, 27 to 30, 33 to 44, 46 IO control unit: 20, 47-49, 54, 55 DMA response control unit: 20, 51-53, 65, 75 NA bus master control unit: 20, 56, 58-64, 66-74 memory dump control unit: 20, 57

The register 1 stores the transaction type from the NA bus, and the registers 2 and 3 store the address from the NA bus. The NA bus has 36 bits, the register 4 stores the upper 4 bits, and the register 3 stores the lower 32 bits. Register 4 has N
Split ID of read transaction from A bus
Is stored. In the case of IAC, it does not receive a response to the DMA read from the NA bus.
The split ID is stored only at the time of the response transaction for the read.

The signals received from the NA bus in each of the registers 1 to 4 are checked for irregularities such as parity, and if there is no error, they are stored in the registers 5 to 8 respectively. Here, the addresses of the registers 2 and 3 are combined and stored in the register 7. Further, the register 7 stores the memory dump source address when executing the memory dump.

The register 6 stores the interrupt data transferred by the address of the NA bus. In the interrupt transaction, the interrupt data is stored in the next cycle in which the address is stored in the register 3. The register 6 stores this interrupt data.

The NA bus slave control unit 9 judges what transaction the NA bus transaction is based on the transaction type stored in the register 1, and sets a factor for starting the MP bus transaction corresponding to the transaction. Then, the MP bus request factor control unit 12 is instructed.

For example, if the NA bus transaction is an interrupt transaction, an instruction to set the cause of the interrupt transaction is issued, and if it is a DMA read transaction, an instruction to set the cause of the coherent block read is issued. In the case of a memory dump, the instruction to set the cause of coherent block read is issued as in the DMA read transaction.

The addresses from the NA bus held in the register 7 are hit-checked with the addresses stored in the buffers 11 and 31 by the comparison circuits 76 and 10, and the result is sent to the MP bus request factor control unit 12. Be notified.

In the IAC, there may be two DMA transactions at the same time, and the buffer 11 exists for managing them. The NA bus is a splittable bus. Therefore, there are cases where two DMA read transactions are registered and cases where two transactions, DMA read and DMA write, are registered.

However, the DMA transaction registered in the buffer 11 is registered when the cache misses and the MP bus transaction requesting data to the memory is being executed. When the DMA write transaction hits the cache, the write is executed to end the DMA write transaction, and when the DMA read transaction hits the cache, a data response is immediately sent to the NA bus and the DMA read transaction ends. . Therefore, the DMA transaction that hits the cache is not registered in the buffer 11.

When the comparison circuit 76 hits, it indicates that the transaction of the same cache block address has already been issued on the MP bus by the previous DMA transaction, and is required for the current transaction in the response data from the memory of the previous DMA transaction. Since the current transaction contains the data, even if the current transaction misses in the cache, M that requests the data from the memory
It is not necessary to issue a Pbus transaction. Therefore, the transaction hit by the comparison circuit 76 is only registered in the buffer 11, and the MP bus request factor control unit 12 does not set the factor for starting the MP bus transaction.

The buffer 31 is an address tag of the cache, and hitting the address of the buffer 31 indicates that data exists in the cache. The data in the cache is held by the IDB chip. Since the cache has 4 entries, the buffer 31 is also an address tag of 4 entries.

When the address of the register 7 matches the address of the buffer 31 in the comparison circuit 10 during the DMA read transaction, the DMA read cache hit controller 65 is instructed to start the data response to the NA bus. DMA read cache hit controller 6
Reference numeral 5 outputs the split ID of the NA bus indicating that the DMA read is not split and the data response is made. The split ID is selected by the selection circuit 68 and stored in the register 69. The register 69 outputs the stored split ID on the NA bus.

The MP bus request factor control unit 12 determines the NA
According to the instruction from the bus slave control unit 9, the factor for starting the MP bus transaction is set. However, DM
In the case of the A transaction, the factor for starting the MP bus transaction is set only when there is no hit in the comparison circuit 76 and the comparison circuit 10.

Further, if the coherent block read or the coherent block read exclusive for reading data to the cache by the own IAC is successfully issued by the register 36 storing the arbitration result of the MP bus, the cache becomes empty. The cache data may be written back to the memory to prepare the entry. If there is a write back to memory,
It is necessary to issue a block write (BW) transaction to the MP bus.

The block write (BW) check circuit 17 checks whether the block write is necessary. When it is determined that the block write is necessary, the factor for starting the block write transaction is set in the MP bus request factor control unit 12.

Further, the comparison circuit 30 hit-checks the address of the register 37 which stores the address of the slave transaction of the MP bus (transaction issued by other than the own IAC) and the address of the buffer 31 of the address tag portion of the cache. Slave transaction is coherent read transaction (CR / CE)
If there is a hit at the time of, it is necessary to make a block data response to the MP bus. Therefore, the comparison circuit 30 instructs the MP bus request factor control unit 12 to set a factor for starting the block data response.
The MP bus request factor control unit 12 instructs the MP bus request internal request control unit 13 to set the MP bus request.

The MP bus request internal request control unit 13 sets an MP bus internal request requesting execution of an MP bus transaction according to the MP bus request factor control unit 12, and outputs the MP bus internal request to the MP bus internal arbitration circuit 14. . However, in the case of a read transaction, M that has already been issued and has no response yet
When there is a read transaction of the same address as the P bus read transaction, in order to maintain the coherency of the cache, it is not possible to issue it on the MP bus until the data response of the already issued read transaction of the same address is completed. Can not.

Therefore, the address registered in the buffer 19 for managing the read transaction of the MP bus and the address stored in the register 7 are compared by the comparison circuit 1
If they match with each other, the MP bus request internal request control unit 13 does not set the MP bus request of the read transaction. It waits until the data response of the MP bus read transaction with the matching address is completed and is deleted from the buffer 19. The split ID of the read transaction on the MP bus is equal to the entry number registered in the buffer 19.

The MP bus internal arbitration unit 14 arbitrates the MP bus request from the MP bus request internal request control unit 13, and the arbitration result is stored in the register 15.
As shown in FIG. 7, the MP bus is a bus having 4 states as one cycle. Of the first four states, the request is output in state I, and the address, command, and split ID are output in state III.

The request generation circuit 23 generates a request based on the arbitration result stored in the register 15,
The selection circuit 25 selects the output of the request generation circuit 23 and stores it in the register 26. Then, the register 26 outputs the request to the MP bus in the state I.

The IAC takes in requests from all nodes of the MP bus and stores them in the register 33. The MP bus arbitration circuit 34 arbitrates the request stored in the register 33, and judges from the arbitration result whether any of the requests stored in the register 15 has acquired the MP bus.
The result is stored in the register 35.

The register 36 stores the output of the register 35 when the transaction issued by the own IAC stored in the register 35 is not retried on the MP bus. The command generation circuit 21 generates an MP bus command from the output of the register 15, and the register 22 outputs the M bus command.
Stores the P bus command.

The interrupt data generation circuit 16 outputs the output of the register 6 for storing the interrupt data received from the NA bus and the SW visible register group 2 during the interrupt transaction.
The output from the register at 0 generates an interrupt code to the MP bus and outputs it to the selection circuit 24.

The selecting circuit 24 selects the output of the interrupt data generating circuit 16 at the time of an interrupt transaction, selects the address from the buffer 31 in the case of the block write by the replacement of the cache, and otherwise, the register 7 The address stored in is selected and output to the selection circuit 25. After selecting the request from the request generating circuit 23, the selecting circuit 25 selects the address of the selecting circuit 24 and stores it in the register 26.

The command stored in the register 22 and the address stored in the register 26 correspond to a read transaction such as a coherent block read in which a transaction acquired in the MP bus stored in the register 35 or a block write. It is output to the MP bus only in the case of such a write transaction.

In the case of the response transaction to the read transaction, the split ID selected by the MP bus output split ID selection circuit 45 is stored in the register 42, and the split ID is set in the state III.
Is output (see FIG. 7 (2)). In the case of an IO read transaction to the NA bus, the MP bus output split ID selection circuit 45 uses the NA bus split ID stored in the register 8 and the IO read transaction information stored in the buffer 48 to determine the MP
Select a split ID for the bus.

In the case of the response due to the cache hit of the slave read transaction of the MP bus, the buffer 19 in which the slave read transaction is registered
Since the entry number of is the split ID on the MP bus, the registration ID generation circuit 29 generates the split ID on the MP bus, and the split ID is selected by the MP bus output split ID selection circuit 45.

The register 27 stores the lower byte of the address in order to determine which SW visible register is to be written. The register 28 stores the data to be written in the SW visible register. The SW visible register group 20 is a set of SW visible registers, and also includes a SW visible register having a memory dump function.

The register 33 fetches the request in the MP bus state I and fetches the address in the state III. The address fetched in the state III is checked by the address space check circuit 38 for which address space the transaction is. If it is a transaction for the IO space under its own IAC, it instructs the IO transaction control unit 47 to start the IO transaction.

The register 39 takes in the split ID in the MP bus state III. Register 40 is register 39
Capture the output of. The comparison circuit 41 checks the split ID stored in the register 40 and the split ID registered in the buffer 11 to see if the response is for a transaction waiting for a data response from the memory registered in the buffer 11.

If they match, it indicates that the data of the transaction waiting for a data response registered in the buffer 11 has been replied, and the information of the transaction for which the data reply of the buffer 11 has been made is stored in the register 32. . When the data is stored in the cache, the buffer 31 which is the address tag part of the cache
The address is registered in.

In the case of DMA read transaction or memory dump, it is necessary to issue a transaction to the NA bus. The selection circuit 75 selects the output of the buffer 32 in the case of a normal DMA read transaction, and selects the information from the buffer 11 in order to change the dump source address and the dump destination address in the case of a memory dump.

When the transaction in which the data is replied is stored in the register 32, the selecting circuit 51 selects the output of the selecting circuit 75, and the transaction registered in the buffer 11 is the other entry of the buffer 11. If it is a DMA read transaction that hits the transaction and the data response of the hit transaction is confirmed,
The output of the buffer 11 is selected.

The transaction selected by the selection circuit 51 is stored in the buffer 52. DM in the buffer 52
Execution of an A read response transaction or memory dump is awaited. When there is a transaction waiting to be executed in the buffer 52, the DMA read response control unit 53 issues a bus acquisition request to the NA bus internal arbitration unit 64,
An IO write transaction by a DMA read response transaction or a memory dump is started.

The register 43 fetches a command in the MP bus state III. The register 44 captures the output of the register 43. The command stored in the register 43 is decoded by the command decoding circuit 46, and it is determined what transaction the transaction is.

In the case of single read or single write, an instruction is issued to the IO transaction control unit 47 to issue an IO transaction. The IO transaction control unit 47 starts an IO transaction when instructed by both the command decode circuit 46 and the address space check circuit 38. If it is a read transaction, an IO read transaction is registered in the buffer 48, and if it is a write transaction, a write transaction is registered in the register 49.

When the command decode circuit 46 determines that the transaction is an interrupt clear transaction, the interrupt clear controller 56 starts the interrupt clear transaction according to the information in the SW visible register group 20. The memory dump control unit 57 starts the memory dump according to the instruction of the SW visible register group 20.

The NA bus internal arbitration circuit 64 includes a DMA read response control section 53 and an IO read / write control section 5.
5, interrupt clear control unit 56, memory dump control unit 57
Arbitrates each request from the NA bus arbitration circuit 6
Issue a request for NA bus acquisition to 7.

The NA bus arbitration circuit 67 arbitrates by including the request of the own IAC from the NA bus internal arbitration circuit 64 in the request from the other node of the NA bus received by the register 74, and outputs the request. One wins the NA bus. The arbitration result is stored in the register 73 and notified to each node of the NA bus.

The selection circuit 58 selects the NA bus split ID of the transaction selected by the NA bus internal arbitration circuit 64 from the outputs of the DMA read response control unit 53, the IO read / write control unit 55, and the memory dump control unit 57. Select.

The selection result is stored in the register 61. The selection circuit 68 selects the output of the register 61 unless it is a cache hit at the time of DMA read, and the split ID of the NA bus stored in the register 61 is stored in the register 69. After that, the split ID stored in the register 69 is output to the NA bus.

The selection circuit 59 determines the transaction type indicating what the transaction of the NA bus is, the DMA read response control section 53 and the I type.
O read / write controller 55 and interrupt clear controller 56
And the output of the memory dump controller 57, the transaction type of the transaction selected by the NA bus internal arbitration circuit 64 is selected.

The selection result is stored in the register 62, then stored in the register 70, and then the transaction type is output to the NA bus.

The selection circuit 60 uses the DMA for memory dump.
The address of the transaction selected by the NA bus internal arbitration circuit 64 is selected from the output of the read response control unit 53, the output of the IO read / write control unit 55, and the output of the interrupt clear control unit 56.

The selection result is stored in the register 63. The selection circuit 66 selects the address of the register 63 only during an interrupt transaction, and then selects the clear data of the interrupt from the interrupt clear control unit and stores it in the registers 71 and 72. The address of the register 63 is selected except for the interrupt transaction.

The register 71 stores the upper 4 bits of the address and outputs it to the NA bus. The register 72 stores the lower 32 bits and outputs it to the NA bus.

The operation of the memory dump transaction in the embodiment will be described. It shows which function of the embodiment each function of the memory dump control block diagram of FIG. 3 corresponds to.

Memory dump control function: SW visible register function group 20 Memory dump control register: SW visible register function group 20 Dump source start address register: SW visible register function group 20 Dump destination start address register: SW visible register function group 20 Counter Control: SW visible register function group 20 Dump source address register: SW visible register function group 20 Dump destination address register: SW visible register function group 20 End address register: SW visible register function group 20 End check circuit: Memory dump control unit 57

When the memory dump control section 57 issues a memory dump start instruction from the SW visible register group 20, the memory dump control section 57 causes the NA bus internal arbitration section 64.
Issue a request to acquire the NA bus. The NA bus internal arbitration unit 64 selects the request for the memory dump, and the memory dump does not operate other than its own IAC. Therefore, the NA bus arbitration unit 67 acquires the NA bus from the IAC. The dump source address in the SW visible register group 20 is selected by the selection circuit 50 and stored in the register 7, and the memory dump transaction is started.

As with the DMA read transaction, M
An instruction is issued to the P bus request factor control unit 12, and finally a coherent block read transaction is issued to the MP bus. At this time, the address of the register 7 is registered in the buffer 11 and waits for the reply of the data.

In the buffer 11, not only the dump source address but also the dump destination address corresponding to the tamper source address and the split ID of the coherent block read transaction issued to the MP bus are registered. As for the split ID, the issued coherent block read is registered in the buffer 19, generated by the registration ID generation circuit 29 according to the registered entry number, and registered in the buffer 11.

In the comparison circuit 41 of the split ID registered in the buffer 11 and the split ID of the data response transaction, if it is confirmed that the data response corresponds to the transaction registered in the buffer 11, The dump source address of is stored in the register 32. The selection circuit 75 selects the memory dump destination address registered in the buffer 11 to change the address from the memory dump source address to the memory dump destination address. The output of the selection circuit 75 is selected by the selection circuit 51, registered in the buffer 52, and waits for execution of the IO write with the data length of 64 bytes of the memory dump on the NA bus.

As described above, the memory dump transaction is always registered in the buffer 52 and waits for output to the NA bus.

The buffer 52 instructs the DMA read response control unit 53 that it is a memory dump transaction, and the DMA read response control unit 53 starts execution of IO write with a data length of 64 bytes to the NA bus. A request is sent to the NA bus internal arbitration unit 64, and N
Selected by the internal arbitration result of the A bus internal arbitration unit 64, the transaction type is stored in the register 62, and the address is stored in the register 63.

Since only the own IAC is operating in the memory dump, the IAC acquires the NA bus in the NA bus arbitration unit 67. The transaction type is stored in the register 70, the address is stored in the register 71 and the register 72, and an IO having a data length of 64 bytes for the NA bus is stored.
A write, that is, a memory dump is executed.

The operation of the BIA is as described above using the BIA block diagram of FIG. The operation during memory dump is described below. As an example, the operation of performing a memory dump from the CPU0 system to the normally operating CPU1 system and CPU2 system will be described.

A request comes from the CPU0 system, is stored in the request 0 register 145, and is arbitrated by the arbitration circuit 148. The CPU0 system is selected in the arbitration circuit 148, and the result is stored in the arbitration result register 149.

Data is stored only in the down data 0 register 150. The voting determination circuit 156 simply selects the output of the down data 0 register 150. The data selection circuit 157 is a down data 0 register 1
If 50 is selected, the down control unit 158 determines that the access code of the first phase is an IO write transaction having a data length of 64 bytes, it is determined as a memory dump, and instructs the data buffer 161 to store the data of the next phase and thereafter. put out. The data buffer 161 is the down controller 1
The data is stored according to the instruction of 58.

The memory dump destination judging circuit 159 judges from the arbitration result register that the CPU system which has not made a request is the memory dump destination, and stores the result in the memory dump destination register 160.

The access code conversion circuit 162 converts the IO write access code having a data length of 64 bytes into a DMA write access code having a data length of 64 bytes. A DMA write with a data length of 64 bytes is a normal transaction, not a special transaction for memory dump.

The access code conversion circuit 162 is the CPU 1 system or CPU indicated by the memory dump destination register 160.
A DMA write with a converted data length of 64 bytes is executed for the second system. First, the updater 1 register 164
And the access code of the DMA write with a data length of 64 bytes is stored in the updater 2 register 165, and the CPU 1
System, CPU2 system. Next, the data buffer 161
Memory dump data from Updater 1 register 16
4 and updater 2 stored in register 165, CPU1
System, CPU2 system to send data. With the above, the memory dump operation is completed.

[0126]

As described above, according to the present invention, it becomes possible to read out the memory contents of the CPU system separated by a factor such as a failure, and as a means for reading out, a common global memory or the like is used. There is an effect that the contents of each memory of the CPU system can be directly transferred to another system and the memory dump processing can be executed without specially providing the above memory.

[Brief description of the drawings]

FIG. 1 is a system block diagram to which an embodiment of the present invention is applied.

FIG. 2 is a functional block diagram of the IAC of FIG.

FIG. 3 is a functional block diagram of a memory dump control unit 131 in FIG.

FIG. 4 is a functional block diagram of the BIA of FIG.

5 is a diagram showing a part of further detailed blocks of the IAC functional block of FIG. 2;

FIG. 6 is a diagram showing a part of further detailed blocks of the IAC functional block of FIG. 2;

FIG. 7 is a diagram illustrating a processing example of an MP bus transaction.

FIG. 8 is a system block diagram of a conventional information processing apparatus having a triple configuration.

[Explanation of symbols]

 100a to 100c EPC 101a to 101c Memory 102a to 102c MP bus 103a to 103c BIU 104 to 107 BIA 108 to 111 IO bus 120 NA bus slave control unit 121 NA bus 122 MP bus 123 internal request control unit 124 DMA control unit 125 IO cache Control unit 126 MP bus master control unit 127 MP bus slave control unit 128 DMA response control unit 129 NA bus master control unit 130 IO control unit 131 memory dump control unit 132 memory dump control register 133 dump source start address register 134 dump destination start address register 135 Dump end address register 136 Dump source address register 137,141 +1 counter 138,142 Selector 139,143 Printer control unit 140 dump destination address register 144 completion check circuit

Claims (3)

[Claims] 1. A redundant configuration of at least three systems of information processing subsystems, an input / output bus, a plurality of peripheral control devices connected to the input / output buses, and a common peripheral control device. A bus interface device which is provided between the information processing subsystem and the input / output bus and executes a majority logic of the output from each of the information processing subsystems to the peripheral control device; Each system of the device subsystem has an arithmetic processing unit for executing arithmetic processing, a memory for storing program data, a transaction for accessing the peripheral control device from the arithmetic processing unit, and an access for the memory from the peripheral control device. A memory dump system in an information processing apparatus having an input / output control unit for controlling a transaction, comprising: Each of the force control units includes an instruction unit for instructing the start and end of a memory dump for transferring the contents of the memory of the own system to the memory of another system, and a self-system between the start instruction and the end instruction of the memory dump. And a memory dump control unit that sequentially reads the contents of the memory and sends the contents to the bus interface device, wherein the bus interface device sequentially reads the contents of the memory sent from the input / output control unit to the memory of the other system. A memory dump system having a sending control means for controlling sending. 2. The instructing means has means for retaining a memory dump source start address, a memory dump destination start address, and a memory dump end address, which have been instructed in advance, respectively, and the memory dump control means has the Means for reading data from the self-system memory while sequentially updating the memory tamping source start address to the memory dump end address, means for sequentially updating the memory dump destination start address, and the updated memory dump destination address and read data 2. The memory dump system according to claim 1, further comprising means for sending the data to the bus interface device. 3. The request control arbitration unit for arbitrating the requests of each CPU system, and the CP that has not received the request based on the result of the request arbitration unit.
Memory dump destination determination means for determining the U system as a memory dump destination, and CP designated by the memory dump destination determination means
3. The memory dump system according to claim 1, further comprising dump data transmission control means for executing writing to the U-system memory.