JPH09172231A - Dividing method of ceramic substrate - Google Patents
Dividing method of ceramic substrateInfo
- Publication number
- JPH09172231A JPH09172231A JP33057295A JP33057295A JPH09172231A JP H09172231 A JPH09172231 A JP H09172231A JP 33057295 A JP33057295 A JP 33057295A JP 33057295 A JP33057295 A JP 33057295A JP H09172231 A JPH09172231 A JP H09172231A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- dividing
- dicing
- conductor
- ground conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 55
- 239000000919 ceramic Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 238000000926 separation method Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 229910010293 ceramic material Inorganic materials 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
Landscapes
- Devices For Post-Treatments, Processing, Supply, Discharge, And Other Processes (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、特に放熱板上にセ
ラミック基板を搭載する半導体装置用の、セラミック基
板の分割方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of dividing a ceramic substrate, particularly for a semiconductor device having a ceramic substrate mounted on a heat dissipation plate.
【０００２】[0002]
【従来の技術】ＴＶ、ＨＤＴＶ、ＣＲＴ等の偏向回路を
集積化したビデオパック（商品名）なる半導体装置が本
願出願人において商品化されている。半導体素子その他
を固着したセラミック基板を一つのパッケージに収納し
たものであるが、低コスト化の当然の指向として樹脂モ
ールドで製品を供給することがなされている。また、製
造ラインに投入しやすいように他の半導体装置と同様に
リードフレームを用いる手法を例えば特開平６ー２５８
４１１号に提案している。2. Description of the Related Art A semiconductor device called a video pack (trade name) in which deflection circuits such as a TV, HDTV, and CRT are integrated has been commercialized by the present applicant. Although a ceramic substrate to which a semiconductor element or the like is fixed is housed in one package, products are supplied by resin molding as a natural aim of reducing costs. Further, a method of using a lead frame like other semiconductor devices so that it can be easily put into a manufacturing line is disclosed in, for example, Japanese Patent Laid-Open No. 6-258.
No. 411.
【０００３】この様な半導体装置では、セラミック基板
を半田ペーストなどにより放熱板に固着するためおよび
セラミック基板の浮遊容量を減じるために、セラミック
基板の裏面側にも全面に金属導体を形成する必要が生じ
る。そして前記セラミック基板に形成したスルーホール
を通して前記金属導体を接地するものである。前記セラ
ミック基板は、一枚の大きなセラミック基板を複数に分
割することにより形成する。図３（Ａ）を参照して、先
ずセラミック基板１の表面側には回路網を構成するため
の配線パターン２を、金属導体の蒸着とホトマスクを用
いたパターニングで形成し、同じく裏面側には蒸着によ
り接地導体３を形成した一枚の大きな基板１を準備す
る。続いて図３（Ｂ）を参照して、セラミック基板１の
表面側からダイシングによりセラミック基板１を個々の
基板に分割するものである。In such a semiconductor device, it is necessary to form a metal conductor on the entire back surface of the ceramic substrate in order to fix the ceramic substrate to the heat sink with solder paste or the like and to reduce the stray capacitance of the ceramic substrate. Occurs. Then, the metal conductor is grounded through a through hole formed in the ceramic substrate. The ceramic substrate is formed by dividing one large ceramic substrate into a plurality of pieces. With reference to FIG. 3 (A), first, a wiring pattern 2 for forming a circuit network is formed on the front surface side of the ceramic substrate 1 by vapor deposition of a metal conductor and patterning using a photomask, and also on the back surface side. A large substrate 1 having a ground conductor 3 formed by vapor deposition is prepared. Subsequently, referring to FIG. 3B, the ceramic substrate 1 is divided into individual substrates by dicing from the front surface side of the ceramic substrate 1.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、ダイシ
ングブレードによりフルカットするとは言え、裏面に形
成した接地導体がブレードに引きずられて、図３（Ｂ）
のバリ４が生じやすく、これが製造工程（セラミック基
板上に能動素子、受動素子を搭載する工程）において平
坦面を滑らせる搬送時のトラブルを発生させるという欠
点があった。However, even though full cutting is performed by the dicing blade, the grounding conductor formed on the back surface is dragged by the blade, and as shown in FIG.
However, there is a drawback in that the burr 4 is likely to occur, and this causes a trouble during transportation of sliding on a flat surface in a manufacturing process (a process of mounting an active element and a passive element on a ceramic substrate).
【０００５】セラミック基板上の配線導体を蒸着に依ら
ず印刷パターンで形成する場合には、セラミック基板に
Ｖ溝を形成してブレイキングに依り分割することも可能
ではあるが、高周波用の微細化パターンを形成するには
印刷パターンは不向きである。またＶ溝上に金属導体を
蒸着、パターニングするには、ホトレジスト形成時にホ
トレジストがＶ溝上に盛り上がるような形になり、これ
がホトマスクと接触してしまうために実施が困難であ
る。故にホトマスクを用いたパターニングを用いるため
には、セラミック基板上からのダイシングがセラミック
基板分割の唯一の手法である。When the wiring conductor on the ceramic substrate is formed by a printed pattern without vapor deposition, it is possible to form a V groove in the ceramic substrate and divide it by breaking, but a fine pattern for high frequency. The printing pattern is not suitable for forming the. In addition, the vapor deposition and patterning of the metal conductor on the V-groove is difficult to perform because the photoresist rises up on the V-groove when the photoresist is formed, and this is in contact with the photomask. Therefore, in order to use patterning using a photomask, dicing from the ceramic substrate is the only method for dividing the ceramic substrate.
【０００６】[0006]
【課題を解決するための手段】本発明は上記従来の課題
に鑑みなされたもので、セラミック基板のダイシングラ
イン予定部分に分割溝を形成し、その上に接地導体を形
成すると共に、セラミック基板の表面側からダイシング
によってセラミック基板を個々に分割することにより、
前記接地導体のバリが前記分割溝内に収まるようにする
ものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art. A dividing groove is formed in a portion of a ceramic substrate where a dicing line is to be formed, and a ground conductor is formed on the dividing groove. By dividing the ceramic substrate individually by dicing from the surface side,
The burr of the ground conductor is set within the dividing groove.
【０００７】[0007]
【発明の実施の形態】以下に本発明の具体的な実施の形
態を図面を参照しながら詳細に説明する。図１は本発明
の製造方法を示す断面図である。先ず図１（Ａ）に示す
ように、裏面側のダイシングラインに相当する部分に深
さ５００μ、幅５００μ程度のＶ字型の分離溝１１を形
成した、板厚０．５〜０．８ｍｍのセラミック基板１２
を準備する。分離溝１１の形状はＵ字型等でもよい。形
成は、焼成前のセラミック素材に鋳型を押しつけて分離
溝１１を形成した後に、前記セラミック素材を焼成する
ことで形成することができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a manufacturing method of the present invention. First, as shown in FIG. 1 (A), a V-shaped separation groove 11 having a depth of 500 μm and a width of 500 μm is formed in a portion corresponding to a dicing line on the back surface side. Ceramic substrate 12
Prepare The shape of the separation groove 11 may be U-shaped or the like. It can be formed by pressing a mold against the ceramic material before firing to form the separation groove 11, and then firing the ceramic material.
【０００８】次いで図１（Ｂ）に示すように、セラミッ
ク基板１２の表面に金等の導電材料を全面に蒸着した
後、その上にホトレジスト膜を形成し、ホトマスクを用
いて露光、現像してレジスト膜を形成し、該レジスト膜
をマスクにして前記導電材料のエッチングを行うことに
より回路網構成に必要な導電パターンを１３を形成す
る。また、セラミック基板１２の裏面の全面には膜厚１
０００オングストローム程度の金を蒸着して接地導体１
４とする。この接地導体１４は分離溝１１内にも同様の
膜厚で被着される。表面側の導電パターンの内接地電位
（ＧＮＤ）を印加するパターンと接地導体とは基板１２
に形成したビアホールを介して電気的に接続される。セ
ラミック基板１２表面側のダイシングライン１５部分は
平坦なセラミック素材が露出しているものとする。Then, as shown in FIG. 1B, after a conductive material such as gold is vapor-deposited on the entire surface of the ceramic substrate 12, a photoresist film is formed on it and exposed and developed using a photomask. A resist film is formed, and the conductive material is etched using the resist film as a mask to form a conductive pattern 13 necessary for the circuit network configuration. In addition, a film thickness of 1 is formed on the entire back surface of the ceramic substrate 12.
Ground conductor 1 by depositing about 000 angstroms of gold
4 is assumed. The ground conductor 14 is also deposited in the separation groove 11 with the same film thickness. The pattern for applying the inner ground potential (GND) of the conductive pattern on the surface side and the ground conductor are the substrate 12
It is electrically connected through the via hole formed in. It is assumed that the flat ceramic material is exposed at the dicing line 15 portion on the front surface side of the ceramic substrate 12.
【０００９】次いで図１（Ｃ）に示すように、ダイシン
グライン１５上からダイシングブレードによりセラミッ
ク基板１２を完全に切断して、横１０ｍｍ縦８ｍｍの如
き複数の基板に分離する。ダイシングブレードがセラミ
ック基板１２を貫通するとき、ブレードが分離溝１１内
の接地導体１４を引きずり図面下方へ押し出してバリ１
６を発生させる。このバリ１６はダイシングブレードの
切断速度と接地導体１４の膜厚との関係に依るが、高さ
が概ね数十μの範囲内に収まることが確認されている。
従って、分離溝１１の深さを適当な値（バリ１６の突起
が分離溝１１の深さを超えない様な深さ）にしておくこ
とにより、バリ１６は接地導体１４の水平面から突出す
ることがない。Next, as shown in FIG. 1C, the ceramic substrate 12 is completely cut from above the dicing line 15 with a dicing blade to separate it into a plurality of substrates having a width of 10 mm and a length of 8 mm. When the dicing blade penetrates the ceramic substrate 12, the blade drags the ground conductor 14 in the separation groove 11 and pushes the ground conductor 14 downward in the drawing to form the burr 1.
Generate 6. It has been confirmed that the burr 16 has a height within a range of several tens of μ although it depends on the relationship between the cutting speed of the dicing blade and the film thickness of the ground conductor 14.
Therefore, by setting the depth of the separation groove 11 to an appropriate value (the depth of the protrusion of the burr 16 does not exceed the depth of the separation groove 11), the burr 16 is projected from the horizontal surface of the ground conductor 14. There is no.
【００１０】個々の基板に分離した後、セラミック基板
１２に能動素子、受動素子をダイボンド、ワイヤボンド
して前記導電パターン１３により回路網を構成し、次い
で基板１２を鉄系、銅系のリードフレームの放熱板上に
銀ペーストなどで固着し、リードと前記回路網とをワイ
ヤボンドした後全体を樹脂モールドして製品が完成す
る。前記放熱板は前記接地導体と銀ペーストを介して接
地電位が与えられる。After being separated into individual substrates, active elements and passive elements are die-bonded and wire-bonded to the ceramic substrate 12 to form a circuit network by the conductive patterns 13, and then the substrate 12 is made of an iron-based or copper-based lead frame. The product is completed by fixing it on the heat radiating plate with silver paste or the like, wire-bonding the leads and the circuit network, and then resin-molding the whole. A ground potential is applied to the heat sink through the ground conductor and silver paste.
【００１１】本発明に依れば、上記のダイボンド、ワイ
ヤボンド工程において、接地導体１４の裏面側と作業台
の平坦表面とを当接させながら基板１２を滑らせる搬送
時に、バリ１６が引っかかってトラブルを発生させると
いうような現象を防止できる。図２は第２の実施の形態
を示すものである。セラミック基板１２の分離を、図２
（Ａ）に示すように基板１２の途中までダイシングした
後、図２（Ｂ）で図示したＡの方向に力を加えることに
より、セラミック基板１２をブレイキングして分離す
る。ブレイキングでも同様にバリ１６が発生するが、先
の実施の形態と同様に分離溝１１の深さを適宜設定して
おくことで、接地導体１４表面より突出しないように製
造することができる。本実施例ではダイシングがセラミ
ック基板１２の途中までで済むので、フルカット工程よ
りは工程を簡素化できる。According to the present invention, in the die-bonding and wire-bonding steps described above, the burr 16 is caught when the substrate 12 is slid while being brought into contact with the back surface of the ground conductor 14 and the flat surface of the workbench. It is possible to prevent a phenomenon that causes a trouble. FIG. 2 shows a second embodiment. The separation of the ceramic substrate 12 is shown in FIG.
As shown in FIG. 2A, after dicing the substrate 12 halfway, a force is applied in the direction of A shown in FIG. 2B to break and separate the ceramic substrate 12. The burr 16 is also generated during the breaking, but by appropriately setting the depth of the separation groove 11 as in the previous embodiment, it is possible to manufacture so as not to project from the surface of the ground conductor 14. In this embodiment, the dicing is completed halfway on the ceramic substrate 12, so the process can be simplified as compared with the full-cut process.
【００１２】[0012]
【発明の効果】以上に説明した通り、本発明によれば、
セラミック基板１２裏面側に分離溝１１を形成すること
で、搬送時のトラブル要因となる接地導体１４のバリ１
６が接地導体１４より突出しないようにできる利点を有
する。また、第２の実施の形態に依ればダイシングのハ
ーフカットとブレイキングとの組み合わせであるので、
フルカットよりは工程を簡素にでき、コストを下げられ
る利点を有する。As described above, according to the present invention,
By forming the separation groove 11 on the back surface side of the ceramic substrate 12, the burr 1 of the ground conductor 14 which causes a trouble during transportation.
There is an advantage that 6 can be prevented from protruding from the ground conductor 14. Further, according to the second embodiment, since it is a combination of half cutting and breaking of dicing,
It has the advantages that the process can be simplified and the cost can be reduced compared to full cut.
【図１】本発明を説明するための平面図である。FIG. 1 is a plan view for explaining the present invention.
【図２】本発明を説明するための平面図である。FIG. 2 is a plan view for explaining the present invention.
【図３】従来例をを説明するための平面図である。FIG. 3 is a plan view for explaining a conventional example.
１１ 分離溝 １２ セラミック基板 １４ 接地導体 11 separation groove 12 ceramic substrate 14 grounding conductor
Claims (3)
形成する工程と、 前記セラミック基板の表面側にはダイシングライン部分
を除いて導電パターンを形成し、前記セラミック基板の
裏面全面には接地導体を形成する工程と、 前記セラミック基板の表面側からダイシングすることに
より前記セラミック基板を複数の基板に分割する工程
と、を具備することを特徴とするセラミック基板の分割
方法。1. A step of forming a dividing groove on the back surface of one ceramic substrate, a conductive pattern is formed on the front surface side of the ceramic substrate except a dicing line portion, and a ground surface is formed on the entire back surface of the ceramic substrate. A method of dividing a ceramic substrate, comprising: a step of forming a conductor; and a step of dividing the ceramic substrate into a plurality of substrates by dicing from a front surface side of the ceramic substrate.
の全部をダイシングすることによることを特徴とする請
求項１記載のセラミック基板の分割方法。2. The method for dividing a ceramic substrate according to claim 1, wherein the dividing is performed by dicing the entire thickness of the ceramic substrate.
の一部を残してダイシングした後にブレイキングにより
行うことを特徴とする請求項１記載のセラミック基板の
分割方法。3. The method for dividing a ceramic substrate according to claim 1, wherein the dividing is performed by breaking after dicing while leaving a part of the thickness of the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33057295A JPH09172231A (en) | 1995-12-19 | 1995-12-19 | Dividing method of ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33057295A JPH09172231A (en) | 1995-12-19 | 1995-12-19 | Dividing method of ceramic substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09172231A true JPH09172231A (en) | 1997-06-30 |
Family
ID=18234158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33057295A Pending JPH09172231A (en) | 1995-12-19 | 1995-12-19 | Dividing method of ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09172231A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020017254A (en) * | 2000-08-29 | 2002-03-07 | 이형도 | A method for formation holes in substrate |
| JP2011071181A (en) * | 2009-09-24 | 2011-04-07 | Hitachi Chem Co Ltd | Printed wiring board |
| KR101388741B1 (en) * | 2012-10-04 | 2014-04-25 | 삼성전기주식회사 | Substrate for power module and method of manufacturing the same |
| JP2019004132A (en) * | 2017-06-19 | 2019-01-10 | パナソニックＩｐマネジメント株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND AUTOMOBILE HEADLIGHT USING THE WIRING BOARD |
| WO2019146638A1 (en) * | 2018-01-24 | 2019-08-01 | 三菱マテリアル株式会社 | Method for manufacturing substrate for power module, and ceramic-copper joint body |
-
1995
- 1995-12-19 JP JP33057295A patent/JPH09172231A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020017254A (en) * | 2000-08-29 | 2002-03-07 | 이형도 | A method for formation holes in substrate |
| JP2011071181A (en) * | 2009-09-24 | 2011-04-07 | Hitachi Chem Co Ltd | Printed wiring board |
| KR101388741B1 (en) * | 2012-10-04 | 2014-04-25 | 삼성전기주식회사 | Substrate for power module and method of manufacturing the same |
| JP2019004132A (en) * | 2017-06-19 | 2019-01-10 | パナソニックＩｐマネジメント株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND AUTOMOBILE HEADLIGHT USING THE WIRING BOARD |
| WO2019146638A1 (en) * | 2018-01-24 | 2019-08-01 | 三菱マテリアル株式会社 | Method for manufacturing substrate for power module, and ceramic-copper joint body |
| JP2019129207A (en) * | 2018-01-24 | 2019-08-01 | 三菱マテリアル株式会社 | Method for manufacturing substrate for power module, and welded body of ceramics and copper |
| US11676882B2 (en) | 2018-01-24 | 2023-06-13 | Mitsubishi Materials Corporation | Method of manufacturing power module substrate board and ceramic-copper bonded body |
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