JPH0917634A - Multilayer type inductor - Google Patents

Multilayer type inductor

Info

Publication number
JPH0917634A
JPH0917634A JP7162369A JP16236995A JPH0917634A JP H0917634 A JPH0917634 A JP H0917634A JP 7162369 A JP7162369 A JP 7162369A JP 16236995 A JP16236995 A JP 16236995A JP H0917634 A JPH0917634 A JP H0917634A
Authority
JP
Japan
Prior art keywords
coil
coil conductor
dielectric constant
insulating film
low dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7162369A
Other languages
Japanese (ja)
Inventor
Shingo Okuyama
晋吾 奥山
Masatoshi Arishiro
政利 有城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP7162369A priority Critical patent/JPH0917634A/en
Publication of JPH0917634A publication Critical patent/JPH0917634A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain a small-sized multilayer inductor wherein inductance value is large and Q characteristics are excellent. CONSTITUTION: Coil conductors 2, 3 and an insulating film 8 of low dielectric constant are alternately formed on the upper surface of an insulating board 1 by using photolithography means. Polyimide resin or the like is used as material of the insulating film 8 of low dielectric constant. The coil conductors 2, 3 are electrically connected in series through a window 8a formed in the insulating film 8 of low dielectric constant and constitute a coil.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層型インダクタ、特
に、高周波空芯コイル等として使用される積層型インダ
クタに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated inductor, and more particularly to a laminated inductor used as a high frequency air core coil or the like.

【0002】[0002]

【従来の技術】従来、この種のインダクタとしては、図
15に示すように、絶縁性基板70の上面に渦巻状コイ
ル導体71を設けたものが知られている。このコイル導
体71の一方の端部71aは絶縁性基板70の左端部に
設けた外部電極76に電気的に接続している。他方の端
部71bは、引出し電極73を介して、絶縁性基板70
の右端部に設けた外部電極77に電気的に接続してい
る。引出し電極73は絶縁被膜72を介してコイル導体
71と交差している。
2. Description of the Related Art Heretofore, as an inductor of this type, one having a spiral coil conductor 71 provided on an upper surface of an insulating substrate 70 is known as shown in FIG. One end 71a of the coil conductor 71 is electrically connected to the external electrode 76 provided on the left end of the insulating substrate 70. The other end portion 71b is connected to the insulating substrate 70 via the extraction electrode 73.
Is electrically connected to the external electrode 77 provided at the right end of the. The extraction electrode 73 intersects with the coil conductor 71 via the insulating coating 72.

【0003】[0003]

【発明が解決しようとする課題】従来のインダクタにあ
っては、絶縁性基板71のサイズを大きくすることな
く、インダクタンス値を大きくする場合、コイル導体7
1の線幅を細くして巻回数を多くする必要がある。とこ
ろが、線幅を細くすると、コイル導体の抵抗が大きくな
り、高周波域でのインダクタのQ特性が悪くなるという
問題点があった。
In the conventional inductor, when the inductance value is increased without increasing the size of the insulating substrate 71, the coil conductor 7 is used.
It is necessary to reduce the line width of 1 and increase the number of windings. However, when the line width is reduced, the resistance of the coil conductor increases, and the Q characteristic of the inductor in the high frequency range deteriorates.

【0004】そこで、本発明の目的は、インダクタンス
値が大きく、かつQ特性が優れた小型の積層型インダク
タを提供することにある。
Therefore, an object of the present invention is to provide a small-sized laminated inductor having a large inductance value and an excellent Q characteristic.

【0005】[0005]

【課題を解決するための手段】以上の目的を達成するた
め、絶縁性基板の表面に、フォトリソグラフィの手段に
てそれぞれ形成したコイル導体と低誘電率絶縁膜とを交
互に積層し、前記低誘電率絶縁膜に設けた窓部にて前記
コイル導体相互が層間接続していることを特徴とする。
In order to achieve the above object, coil conductors and low dielectric constant insulating films respectively formed by means of photolithography are alternately laminated on the surface of an insulating substrate, It is characterized in that the coil conductors are interlayer-connected to each other at a window provided in the dielectric constant insulating film.

【0006】[0006]

【作用】以上の構成により、コイル導体は絶縁性基板上
に積層され、各コイル導体は低誘電率絶縁膜に設けた窓
部にて電気的に直列に接続されコイルを構成する。構成
されたコイルは、インダクタンス値を大きくする場合、
コイル導体の積層数を多くしてコイルの線長を長くすれ
ばよく、線幅を細くしたり、絶縁性基板を大きくしたり
する必要がなくなる。
With the above construction, the coil conductors are laminated on the insulating substrate, and the coil conductors are electrically connected in series at the window provided in the low dielectric constant insulating film to form a coil. The configured coil, when increasing the inductance value,
It suffices to increase the number of laminated coil conductors to increase the coil wire length, and it is not necessary to reduce the wire width or increase the size of the insulating substrate.

【0007】[0007]

【実施例】以下、本発明に係る積層型インダクタの実施
例について、その製造方法と共に添付図面を参照して説
明する。 [第1実施例、図1〜図6]図1に示すように、絶縁性
基板1の上面にコイル導体2を形成する。コイル導体2
の一方の端部2aは絶縁性基板1の左辺に露出してい
る。コイル導体2はフォトリソグラフィの手段にて形成
されている。すなわち、スパッタリング、蒸着等のドラ
イメッキ方法等にてAg,Au,Cu等の金属膜を絶縁
性基板1の上面全面に形成する。次に、金属膜表面に感
光性レジスト膜を塗布、乾燥した後、この感光性レジス
ト膜にマスクフィルムを当てて所望の部分を露光する。
次に、感光性レジスト膜を現像し、金属膜の不要な部分
を感光性レジスト膜から露出させる。次に、この露出し
た部分の金属膜をエッチングにて除去した後、感光性レ
ジスト膜を剥離して所望のコイル導体2を形成する。
Embodiments of the laminated inductor according to the present invention will be described below with reference to the accompanying drawings together with the manufacturing method thereof. [First Embodiment, FIGS. 1 to 6] As shown in FIG. 1, a coil conductor 2 is formed on an upper surface of an insulating substrate 1. Coil conductor 2
One end 2a of the one is exposed on the left side of the insulating substrate 1. The coil conductor 2 is formed by means of photolithography. That is, a metal film of Ag, Au, Cu or the like is formed on the entire upper surface of the insulating substrate 1 by a dry plating method such as sputtering or vapor deposition. Next, after a photosensitive resist film is applied to the surface of the metal film and dried, a mask film is applied to the photosensitive resist film to expose a desired portion.
Next, the photosensitive resist film is developed to expose unnecessary portions of the metal film from the photosensitive resist film. Next, after removing the exposed metal film by etching, the photosensitive resist film is peeled off to form a desired coil conductor 2.

【0008】次に、図2に示すように、絶縁性基板1の
上面にフォトリソグラフィの手段にて低誘電率絶縁膜8
を形成する。この低誘電率絶縁膜8は、コイル導体2の
他方の端部2bを露出させるための窓部8aを有してい
る。低誘電率絶縁膜8の材料としては、ポリイミド樹脂
等が採用される。さらに、図3に示すように、低誘電率
絶縁膜8の上面にコイル導体3をフォトリソグラフィの
手段にて形成する。コイル導体3の一方の端部3aは、
窓部8aに露出しているコイル導体2の端部2bに電気
的に接続している。
Next, as shown in FIG. 2, a low dielectric constant insulating film 8 is formed on the upper surface of the insulating substrate 1 by means of photolithography.
To form The low dielectric constant insulating film 8 has a window 8a for exposing the other end 2b of the coil conductor 2. As a material of the low dielectric constant insulating film 8, a polyimide resin or the like is adopted. Further, as shown in FIG. 3, the coil conductor 3 is formed on the upper surface of the low dielectric constant insulating film 8 by photolithography. One end 3a of the coil conductor 3 is
It is electrically connected to the end 2b of the coil conductor 2 exposed in the window 8a.

【0009】次に、図4に示すように、絶縁性基板1の
上面にフォトリソグラフィの手段にて低誘電率絶縁膜9
を形成する。この低誘電率絶縁膜9は、コイル導体3の
他方の端部3bを露出させるための窓部9aを有してい
る。さらに、図5に示すように、低誘電率絶縁膜9の上
面にコイル導体4をフォトリソグラフィの手段にて形成
する。コイル導体4の一方の端部4aは、窓部9aに露
出しているコイル導体3の端部3bに電気的に接続して
いる。コイル導体4の他方の端部4bは絶縁性基板1の
右辺に露出している。
Next, as shown in FIG. 4, a low dielectric constant insulating film 9 is formed on the upper surface of the insulating substrate 1 by means of photolithography.
To form This low dielectric constant insulating film 9 has a window 9a for exposing the other end 3b of the coil conductor 3. Further, as shown in FIG. 5, the coil conductor 4 is formed on the upper surface of the low dielectric constant insulating film 9 by photolithography. One end 4a of the coil conductor 4 is electrically connected to the end 3b of the coil conductor 3 exposed in the window 9a. The other end 4b of the coil conductor 4 is exposed on the right side of the insulating substrate 1.

【0010】次に、図6に示すように、絶縁性基板1の
左右の両端部に外部電極15,16をスパッタリング、
蒸着あるいは印刷焼付等にて形成する。外部電極15は
コイル導体2の端部2aに電気的に接続し、外部電極1
6はコイル導体4の端部4bに電気的に接続している。
Next, as shown in FIG. 6, external electrodes 15 and 16 are sputtered on the left and right ends of the insulating substrate 1, respectively.
It is formed by vapor deposition or printing. The external electrode 15 is electrically connected to the end portion 2a of the coil conductor 2,
6 is electrically connected to the end 4b of the coil conductor 4.

【0011】こうして得られた積層型インダクタは、コ
イル導体2〜4相互が、低誘電率絶縁膜8,9にそれぞ
れ設けた窓部8a,9aにて電気的に直列に接続され、
コイルを構成する。このコイルは、そのインダクタンス
値を大きくするには、コイル導体の積層数を多くしてコ
イルの線長を長くすればよく、線幅を細くしたり、絶縁
性基板1を大きくしたりする必要はない。従って、Q特
性が良く、かつ小型の積層型インダクタンスが得られ
る。また、低誘電率絶縁膜8,9を使用しているので、
コイル導体2〜4が重なって形成されたとしても、その
間の浮遊容量を小さくすることができ、自己共振周波数
の向上を図ることができる。さらに、コイル導体2〜4
をフォトリソグラフィの手段にて形成しているので、線
幅の仕上がり精度が高く、コイルのインダクタンス値の
狭偏差化が可能となる。
In the multilayer inductor thus obtained, the coil conductors 2 to 4 are electrically connected in series by the windows 8a and 9a provided in the low dielectric constant insulating films 8 and 9, respectively.
Make up the coil. In order to increase the inductance value of this coil, it is sufficient to increase the number of laminated coil conductors to increase the wire length of the coil, and it is not necessary to reduce the wire width or increase the size of the insulating substrate 1. Absent. Therefore, it is possible to obtain a small laminated inductance having a good Q characteristic. Moreover, since the low dielectric constant insulating films 8 and 9 are used,
Even if the coil conductors 2 to 4 are formed to overlap each other, the stray capacitance between them can be reduced, and the self-resonant frequency can be improved. Furthermore, coil conductors 2 to 4
Is formed by means of photolithography, the finish accuracy of the line width is high, and it is possible to narrow the inductance value of the coil.

【0012】[第2実施例、図7〜図13]図7に示す
ように、絶縁性基板21の上面に渦巻状コイル導体22
をフォトリソグラフィの手段にて形成する。コイル導体
22の一方の端部22aは絶縁性基板21の左辺に露出
している。次に、図8に示すように、絶縁性基板21の
上面にフォトリソグラフィの手段にて低誘電率絶縁膜2
8を形成する。この低誘電率絶縁膜28は、コイル導体
22の他方の端部22bを露出させるための窓部28a
を有している。次に、低誘電率絶縁膜28の上面にコイ
ル導体23をフォトリソグラフィの手段にて形成する。
コイル導体23の一方の端部23aは、窓部28aに露
出しているコイル導体22の端部22bに電気的に接続
している。
[Second Embodiment, FIGS. 7 to 13] As shown in FIG. 7, a spiral coil conductor 22 is formed on the upper surface of an insulating substrate 21.
Are formed by means of photolithography. One end 22a of the coil conductor 22 is exposed on the left side of the insulating substrate 21. Next, as shown in FIG. 8, the low dielectric constant insulating film 2 is formed on the upper surface of the insulating substrate 21 by photolithography.
8 is formed. This low-dielectric-constant insulating film 28 has a window 28a for exposing the other end 22b of the coil conductor 22.
have. Next, the coil conductor 23 is formed on the upper surface of the low dielectric constant insulating film 28 by photolithography.
One end 23a of the coil conductor 23 is electrically connected to the end 22b of the coil conductor 22 exposed in the window 28a.

【0013】次に、図9に示すように、絶縁性基板21
の上面にフォトリソグラフィの手段にて低誘電率絶縁膜
29を形成する。この低誘電率絶縁膜29は、コイル導
体23の他方の端部23bを露出させるための窓部29
aを有している。次に、図10に示すように、低誘電率
絶縁膜29の上面に渦巻状コイル導体24をフォトリソ
グラフィの手段にて形成する。コイル導体24の一方の
端部24aは、窓部29aに露出しているコイル導体2
3の端部23bに電気的に接続している。
Next, as shown in FIG. 9, the insulating substrate 21
A low dielectric constant insulating film 29 is formed on the upper surface of the substrate by photolithography. The low-dielectric-constant insulating film 29 has a window 29 for exposing the other end 23b of the coil conductor 23.
a. Next, as shown in FIG. 10, the spiral coil conductor 24 is formed on the upper surface of the low dielectric constant insulating film 29 by photolithography. The one end 24a of the coil conductor 24 has the coil conductor 2 exposed at the window 29a.
3 is electrically connected to the end portion 23b.

【0014】次に、図11に示すように、絶縁性基板2
1の上面にフォトリソグラフィの手段にて低誘電率絶縁
膜30を形成する。この低誘電率絶縁膜30はコイル導
体24の他方の端部24bを露出させるための窓部30
aを有している。次に、図12に示すように、低誘電率
絶縁膜30の上面にコイル導体25をフォトリソグラフ
ィの手段にて形成する。コイル導体25の一方の端部2
5aは、窓部30aに露出しているコイル導体24の端
部24bに電気的に接続している。コイル導体25の他
方の端部25bは絶縁性基板21の右辺に露出してい
る。
Next, as shown in FIG. 11, the insulating substrate 2
A low-dielectric-constant insulating film 30 is formed on the upper surface of 1 by photolithography. The low-dielectric-constant insulating film 30 has a window portion 30 for exposing the other end portion 24b of the coil conductor 24.
a. Next, as shown in FIG. 12, the coil conductor 25 is formed on the upper surface of the low dielectric constant insulating film 30 by photolithography. One end 2 of the coil conductor 25
5a is electrically connected to the end 24b of the coil conductor 24 exposed in the window 30a. The other end 25b of the coil conductor 25 is exposed on the right side of the insulating substrate 21.

【0015】さらに、絶縁性基板21の左右の両端部に
外部電極35,36をスパッタリング、蒸着あるいは印
刷焼付等にて形成する。外部電極35はコイル導体22
の端部22aに電気的に接続し、外部電極36はコイル
導体25の端部25bに電気的に接続している。コイル
導体22〜25は、低誘電率絶縁膜28,29,30に
それぞれ設けた窓部28a,29a,30aにて電気的
に直列に接続され、コイルを構成する。
Further, external electrodes 35 and 36 are formed on the left and right ends of the insulating substrate 21 by sputtering, vapor deposition or printing. The external electrode 35 is the coil conductor 22.
Is electrically connected to the end 22a of the coil conductor 25, and the external electrode 36 is electrically connected to the end 25b of the coil conductor 25. The coil conductors 22 to 25 are electrically connected in series at window portions 28a, 29a, 30a provided in the low dielectric constant insulating films 28, 29, 30 to form a coil.

【0016】図13はこうして得られた積層型インダク
タの断面図であって、コイル導体22と24が厚み方向
に略対向して配設されている。この積層型インダクタは
前記第1実施例の積層型インダクタと同様の作用効果を
奏する。
FIG. 13 is a cross-sectional view of the laminated inductor thus obtained, in which coil conductors 22 and 24 are arranged so as to face each other in the thickness direction. This laminated inductor has the same effects as the laminated inductor of the first embodiment.

【0017】[第3実施例、図14]図14に示すよう
に、第3実施例の積層型インダクタは、コイル導体22
と24が厚み方向に対して垂直な方向にずれていること
以外は、前記第2実施例の積層型インダクタと略同様の
ものであり、同一部品及び同一部分には同じ符号を付し
ている。コイル導体22と24をずらせることによっ
て、コイル導体22と24の間に発生する浮遊容量を更
に抑えることができ、第2実施例の積層型インダクタの
作用効果に加えて、高周波特性をより向上させることが
できる。
[Third Embodiment, FIG. 14] As shown in FIG. 14, the laminated inductor of the third embodiment has a coil conductor 22.
And 24 are substantially the same as the laminated inductor of the second embodiment except that they are deviated in the direction perpendicular to the thickness direction, and the same parts and the same parts are designated by the same reference numerals. . By staggering the coil conductors 22 and 24, the stray capacitance generated between the coil conductors 22 and 24 can be further suppressed, and the high frequency characteristics can be further improved in addition to the function and effect of the laminated inductor of the second embodiment. Can be made.

【0018】[他の実施例]なお、本発明に係る積層型
インダクタは前記実施例に限定するものではなく、その
要旨の範囲内で種々に変更することができる。特に、コ
イル導体の形状、層数等は任意であって、仕様に合わせ
て種々に変更される。また、各実施例の積層型インダク
タにおいて、最外層のコイル導体の表面を絶縁層で覆う
ようなことも任意に行ない得る。
[Other Embodiments] The laminated inductor according to the present invention is not limited to the above-mentioned embodiments, but may be variously modified within the scope of the invention. In particular, the shape of the coil conductor, the number of layers, and the like are arbitrary and can be variously changed according to the specifications. Further, in the multilayer inductor of each example, it is possible to arbitrarily cover the surface of the outermost coil conductor with an insulating layer.

【0019】[0019]

【発明の効果】以上の説明で明らかなように、本発明に
よれば、絶縁性基板上にフォトリソグラフィの手段にて
コイル導体と低誘電率絶縁膜を交互に積層し、各コイル
導体が低誘電率絶縁膜に設けた窓部にて電気的に直列に
接続してコイルを構成するので、インダクタンス値を大
きくする場合、コイル導体の積層数を多くしてコイルの
線長を長くすればよく、従来のように線幅を細くする必
要がない。この結果、インダクタンス値が大きく、かつ
Q特性が優れた小型の積層型インダクタが得られる。
As is apparent from the above description, according to the present invention, the coil conductors and the low dielectric constant insulating film are alternately laminated on the insulating substrate by means of photolithography, and each coil conductor is Since the coil is constructed by electrically connecting in series at the window provided in the dielectric constant insulating film, when increasing the inductance value, the number of laminated coil conductors may be increased to increase the coil wire length. There is no need to reduce the line width as in the past. As a result, a small laminated inductor having a large inductance value and excellent Q characteristics can be obtained.

【0020】また、低誘電率絶縁膜を使用することによ
り、コイル導体間の浮遊容量を小さくすることができ、
自己共振周波数の向上を図ることができる。さらに、隣
接するコイル導体を厚み方向に対して垂直な方向にずら
せて配置することにより、コイル導体間に発生する浮遊
容量を更に抑えることができ、高周波特性をより向上さ
せることができる。
Further, by using the low dielectric constant insulating film, the stray capacitance between the coil conductors can be reduced,
The self-resonant frequency can be improved. Further, by arranging the adjacent coil conductors so as to be displaced in the direction perpendicular to the thickness direction, the stray capacitance generated between the coil conductors can be further suppressed, and the high frequency characteristics can be further improved.

【0021】また、コイル導体をフォトリソグラフィの
手段にて形成しているので、線幅の仕上がり精度が高
く、コイルのインダクタンス値の狭偏差化が可能とな
る。
Further, since the coil conductor is formed by means of photolithography, the finish accuracy of the line width is high, and the inductance value of the coil can be narrowed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る積層型インダクタの第1実施例の
製造手順を示す斜視図。
FIG. 1 is a perspective view showing a manufacturing procedure of a first embodiment of a laminated inductor according to the present invention.

【図2】図1に続く製造手順を示す斜視図。FIG. 2 is a perspective view showing a manufacturing procedure following FIG. 1;

【図3】図2に続く製造手順を示す斜視図。FIG. 3 is a perspective view showing a manufacturing procedure following FIG. 2;

【図4】図3に続く製造手順を示す斜視図。FIG. 4 is a perspective view showing a manufacturing procedure following that of FIG. 3;

【図5】図4に続く製造手順を示す斜視図。FIG. 5 is a perspective view showing a manufacturing procedure following that of FIG. 4;

【図6】第1実施例の積層型インダクタの外観を示す斜
視図。
FIG. 6 is a perspective view showing the outer appearance of the multilayer inductor of the first embodiment.

【図7】本発明に係る積層型インダクタの第2実施例の
製造手順を示す斜視図。
FIG. 7 is a perspective view showing a manufacturing procedure of a second embodiment of the laminated inductor according to the present invention.

【図8】図7に続く製造手順を示す斜視図。FIG. 8 is a perspective view showing a manufacturing procedure following that of FIG. 7;

【図9】図8に続く製造手順を示す斜視図。FIG. 9 is a perspective view showing a manufacturing procedure following that of FIG. 8;

【図10】図9に続く製造手順を示す斜視図。FIG. 10 is a perspective view showing a manufacturing procedure following that of FIG. 9;

【図11】図10に続く製造手順を示す斜視図。FIG. 11 is a perspective view showing a manufacturing procedure following that of FIG. 10;

【図12】第2実施例の積層型インダクタの外観を示す
斜視図。
FIG. 12 is a perspective view showing the outer appearance of a laminated inductor according to a second embodiment.

【図13】図12のXIII−XIII断面図。FIG. 13 is a sectional view taken along the line XIII-XIII of FIG. 12;

【図14】本発明に係る積層型インダクタの第3実施例
を示す断面図。
FIG. 14 is a sectional view showing a third embodiment of the laminated inductor according to the present invention.

【図15】従来の積層型インダクタの外観を示す斜視
図。
FIG. 15 is a perspective view showing the appearance of a conventional laminated inductor.

【符号の説明】[Explanation of symbols]

1…絶縁性基板 2,3,4…コイル導体 8,9…低誘電率絶縁膜 8a,9a…窓部 21…絶縁性基板 22,23,24,25…コイル導体 28,29,30…低誘電率絶縁膜 28a,29a,30a…窓部 1 ... Insulating substrate 2, 3, 4 ... Coil conductor 8, 9 ... Low dielectric constant insulating film 8a, 9a ... Window part 21 ... Insulating substrate 22, 23, 24, 25 ... Coil conductor 28, 29, 30 ... Low Dielectric insulating film 28a, 29a, 30a ... Window portion

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板の表面に、フォトリソグラフ
ィの手段にてそれぞれ形成したコイル導体と低誘電率絶
縁膜とを交互に積層し、前記低誘電率絶縁膜に設けた窓
部にて前記コイル導体相互が層間接続していることを特
徴とする積層型インダクタ。
1. A coil conductor and a low dielectric constant insulating film respectively formed by photolithography means are alternately laminated on a surface of an insulating substrate, and a window portion provided in the low dielectric constant insulating film is used for the above. A laminated inductor characterized in that coil conductors are interconnected between layers.
JP7162369A 1995-06-28 1995-06-28 Multilayer type inductor Pending JPH0917634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7162369A JPH0917634A (en) 1995-06-28 1995-06-28 Multilayer type inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7162369A JPH0917634A (en) 1995-06-28 1995-06-28 Multilayer type inductor

Publications (1)

Publication Number Publication Date
JPH0917634A true JPH0917634A (en) 1997-01-17

Family

ID=15753268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7162369A Pending JPH0917634A (en) 1995-06-28 1995-06-28 Multilayer type inductor

Country Status (1)

Country Link
JP (1) JPH0917634A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001155938A (en) * 1999-09-17 2001-06-08 Fdk Corp Multilayer inductor and manufacturing method thereof
JP2004119948A (en) * 2002-09-30 2004-04-15 Toppan Printing Co Ltd Electromagnetic induction spiral inductor
WO2005071699A1 (en) * 2004-01-23 2005-08-04 Murata Manufacturing Co., Ltd. Chip inductor and process for producing the same
JP2015201606A (en) * 2014-04-10 2015-11-12 株式会社村田製作所 Multilayer substrate manufacturing method and multilayer substrate
JP2018133443A (en) * 2017-02-15 2018-08-23 Tdk株式会社 Manufacturing method for laminated coil component
JP2020136503A (en) * 2019-02-20 2020-08-31 株式会社村田製作所 Coil component
US20200362113A1 (en) * 2017-03-22 2020-11-19 Toray Industries, Inc. Resin composition

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001155938A (en) * 1999-09-17 2001-06-08 Fdk Corp Multilayer inductor and manufacturing method thereof
JP2004119948A (en) * 2002-09-30 2004-04-15 Toppan Printing Co Ltd Electromagnetic induction spiral inductor
WO2005071699A1 (en) * 2004-01-23 2005-08-04 Murata Manufacturing Co., Ltd. Chip inductor and process for producing the same
US7460000B2 (en) 2004-01-23 2008-12-02 Murata Manufacturing Co. Ltd. Chip inductor and method for manufacturing the same
JP2015201606A (en) * 2014-04-10 2015-11-12 株式会社村田製作所 Multilayer substrate manufacturing method and multilayer substrate
JP2018133443A (en) * 2017-02-15 2018-08-23 Tdk株式会社 Manufacturing method for laminated coil component
US20200362113A1 (en) * 2017-03-22 2020-11-19 Toray Industries, Inc. Resin composition
JP2020136503A (en) * 2019-02-20 2020-08-31 株式会社村田製作所 Coil component
US11495397B2 (en) 2019-02-20 2022-11-08 Murata Manufacturing Co., Ltd. Coil component

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