JPH09181085A - Heterojunction bipolar transistor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a hetero-junction bipolar transistor(HBT) excellent in manufacturability without sacrificing performance as element by forming at least on a base layer a base electrode that is formed by self-alignment with an emitter layer, and that is positioned away from the normal mesa-side surface of the emitter layer. SOLUTION: A base electrode 20 is formed in proximity to the reverse mesa- side surface of an emitter layer 8 by the lift-off method using a mask the opening shape of which corresponds to that of a planar projection region that contains an emitter electrode 11 and a base layer 4 but does not contain the normal mesa-side surface 8a of the emitter layer 8. The base electrode 20 is formed on the base layer 4 by self-alignment with the emitter layer 8. At this time the base electrode 20 is not formed on the normal mesa-side surface 8a of the emitter layer 8. This prevents the base electrode 20 from being electrically short-circuited with the bottom 15 of the normal mesa-side 8a of the emitter layer 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor (HBT) and its manufacturing method.

[0002]

18 to 26 show a conventional HBT. FIG. 18 is a top view of a conventional HBT, and FIG. 19 is AA ′ of FIG. 18 (direction perpendicular to the orientation flat).
It is sectional drawing. Hereinafter, a conventional method for manufacturing an HBT will be described. As shown in FIG. 20, in this example, (0,-
On a GaAs substrate 1 having a (1,0,0) plane orientation having an orientation flat of a (-1, -1) plane orientation, an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ to form a lower collector layer 2 and a thickness of 50 are obtained.
00 Å n ⁺ -type GaAs (hereinafter referred to as n ⁺ -GaAs) layer and the impurity concentration of the upper collector layer 3 3 × 10 ¹⁶ cm
^-3 and a thickness of 7000 Å n ^-- GaAs layer and base layer 4
And an impurity concentration of 4 × 10 ¹⁹ cm ⁻³ and a p ⁺ -GaAs layer having a thickness of 1000 Å are epitaxially grown, and a semiconductor material layer 5 to be a lower emitter layer 5 is further formed on the base layer 4.
The impurity concentration is 5 × 10 ¹⁷ cm ^-3 and the thickness is 1000Å
_{N-Al x Ga 1-x} As layer (x = 0.26) or n
-In _x Ga _1-x P layer (x = 0.48) and an impurity concentration of 5 × 10 ¹⁸ cm ^-3 to form the upper emitter layer 6 and a thickness of 500Å
N ⁺ -GaAs layer 6c, and an n-thickness of 1000Å with an impurity concentration of 4 × 10 ¹⁹ cm ⁻³ forming the emitter contact layer 7.
A three-layer structure 8c including a ⁺ -In _0.5 Ga _0.5 As layer 7c is sequentially epitaxially grown.

Next, as shown in FIG. 21, a lower emitter electrode 9 made of a WSi layer and an upper emitter electrode 10 made of a W layer as shown in FIG. 19 are formed on the emitter contact layer 7.
In order to form the emitter electrode 11 having a two-layer structure of the
A W layer 10c of Å is sequentially deposited, and a resist 12 is formed by a photolithography method on a portion which will be required as an emitter electrode 11 later.

Next, a reactive ion etching method (RIE method: Reactive Ion E) is performed using the resist 12.
22, the WSi layer 9c and the W layer 10a are formed of the lower emitter electrode 9 and the upper emitter electrode 10 by etching an unnecessary portion so that the size of the WSi layer 9c and the W layer 10a becomes the emitter width 2 μm × the emitter length 10 μm. The emitter electrode 11 is formed. Further, in order to use the lower emitter electrode 9 as a mask when the emitter layer 8 having the mesa structure is formed by etching the three-layer structure 8c later, the side surface of the lower emitter electrode 9 is etched as shown in FIG. . In this etching, the side surface of the lower emitter electrode 9 is selectively removed by about 0.2 μm by the RIE method using the upper emitter electrode 10 as a mask. After this, the resist 12 is removed.

Next, using the lower emitter electrode 9 as a mask, as shown in FIGS. 24 and 25, the emitter layer 8 is formed.
Etching is performed to form a mesa structure and expose the base layer 4. This etching is performed using a solution obtained by mixing tartaric acid and hydrogen peroxide solution at a ratio of 10: 1 as an etching solution. When the In _x Ga _1-x P layer is used as the semiconductor material layer 5c to be the lower emitter layer 5, the In _x Ga _1-x P layer is not removed by this etching solution, and therefore an aqueous hydrochloric acid solution (for example, hydrochloric acid:
The In _x Ga _1-x P layer is to be etched using water (mixing ratio of 1:30). At this time, the cross-sectional shape of the emitter layer 8 in the direction perpendicular to the orientation flat of the substrate 1 is a trapezoidal type (forward mesa type) in which the lower bottom is longer than the upper bottom as shown in FIG. 24, but is parallel to the orientation flat. It is generally known that the cross-sectional shape of the emitter layer 8 in a different direction shows a trapezoidal type (inverse mesa type) in which the lower bottom is shorter than the upper bottom as shown in FIG. For explanation below,
24 and 25, the surface of the emitter layer 8 on the forward mesa type side is the normal mesa side surface 8a, and the surface on the reverse mesa type side is the reverse mesa side surface 8b.
Shows the forward mesa side surface 8a and the reverse mesa side surface 8b, respectively.

Subsequently, the base electrode 14 as shown in FIG. 19 is formed on the base layer 4 in the vicinity of the emitter electrode 11 by the lift-off method in a self-aligned manner with respect to the emitter layer 8. The base electrode 14 includes a Pt layer (100 Å), a Ti layer (500 Å), a Pt layer (500 Å) and an Au layer (3
000Å), and is formed on the base layer 4 so as to surround the periphery of the vicinity of the emitter layer 8 and so that the width of the emitter electrode in FIG. 18 is 1 μm. At the same time, Pt is also formed on the upper emitter electrode 10.
A four-layer structure 14a of Ti, Pt, and Au is formed, but this does not function as a base electrode.
In order to reduce the base resistance and the base-collector capacitance of the HBT, the base electrode 14 should be as close as possible to the emitter layer 8 (the distance between the emitter layer 8 and the base electrode 14 is 0.3 μm or less). Is required to be formed.

[0007]

However, such an HBT is used in the etching process for forming the mesa structure of the emitter layer 8 as shown in FIG. It often happens that the portion 15 of the sigma protrudes beyond the end 16 of the upper emitter electrode 10. Further, InGa is formed in the lower emitter layer 5.
When the P layer is used, the lower emitter layer 5 can be selectively etched with an aqueous hydrochloric acid solution, but the hem portion 15 of the forward mesa side surface 8a is more than the end portion 16 of the upper emitter electrode 10. If further etching is performed so as to be on the inside, the forward mesa side surface 8a and the reverse mesa side surface 8
Since b is also etched, there is a problem that the distance between the emitter layer 8 and the base electrode 14 becomes long on the reverse mesa type side. If the base electrode 14 is formed in the vicinity of the emitter layer 8 in order to reduce the distance between the emitter layer 8 and the base electrode 14 to 0.3 μm or less in such a state, as shown in FIG. There is a problem in that the emitter layer 8 and the base electrode 14 are electrically short-circuited because 14 is formed on the hem portion 15 of the forward mesa side surface 8a.

Therefore, an object of the present invention is to obtain a heterojunction bipolar transistor and a method for manufacturing the same which solve the above-mentioned problems, and a heterojunction having good manufacturability without sacrificing performance as an element. It is to provide a junction bipolar transistor.

[0009]

In the heterojunction bipolar transistor according to claim 1, a semiconductor substrate,
A collector layer provided on a semiconductor substrate, a base layer provided on the collector layer, a mesa-type emitter layer provided on the base layer and having a regular mesa side surface, and an emitter provided on the emitter layer. The electrode and the emitter electrode and the base layer, but does not include the forward mesa side surface, is provided in a plane projection region and is formed on at least the base layer in a self-aligned manner with respect to the emitter layer. And a base electrode spaced apart from.

In a heterojunction bipolar transistor according to a second aspect, a semiconductor substrate, a collector layer provided on the semiconductor substrate, a base layer provided on the collector layer, and a base layer provided on the base layer, A mesa-type emitter layer having a lower emitter layer and a regular mesa side surface, an emitter electrode provided on the emitter layer, and a plane projection region including the emitter electrode and the base layer, and at least on the base layer. A base electrode formed in a self-aligned manner with respect to the emitter layer, and the forward mesa side surface of the emitter layer is recessed by etching only the lower emitter layer, and is located inside the emitter electrode. Away from.

In the heterojunction bipolar transistor according to claim 3, a semiconductor substrate, a collector layer provided on the semiconductor substrate, a base layer provided on the collector layer, and a base layer provided on the collector layer, The emitter layer has a mesa structure having a regular mesa side surface, an emitter electrode provided on the emitter layer, and a plane projection region including the emitter electrode and the base layer. A base electrode formed in alignment, the forward mesa side surface of the emitter layer is recessed by etching with respect to the entire emitter layer, is located inside the emitter electrode, and is separated from the base electrode.

According to another aspect of the heterojunction bipolar transistor of the present invention, the thin film depletion layer is provided on the base layer, and the base electrode is electrically connected to the base layer through the thin film depletion layer.

In the heterojunction bipolar transistor according to the fifth aspect, the semiconductor substrate is the first conductivity type GaA.
s, the collector layer includes a lower collector layer that is a first-conductivity-type GaAs layer, and an upper collector layer that is a first-conductivity-type GaAs layer having a lower impurity concentration than the GaAs layer. A two-conductivity-type GaAs layer, a first-conductivity-type semiconductor material layer whose mesa-type emitter layer serves as a lower emitter layer, a first-conductivity-type GaAs layer serving as an upper emitter layer, and an emitter contact layer. A first conductivity type In _x Ga _1-x As layer, the emitter electrode serves as a lower emitter electrode, and a WSi layer serves as an upper emitter electrode, and the base electrode includes a Pt layer and a Ti layer. It has a four-layer structure in which a Pt layer and an Au layer are sequentially stacked.

In the heterojunction bipolar transistor of the sixth aspect, the thin film depletion layer is a thinned semiconductor material layer.

In the heterojunction bipolar transistor according to claim 7, the semiconductor material layer is Al _x Ga _{1 -x} As.
It is a layer.

In the heterojunction bipolar transistor according to claim 8, the semiconductor material layer is an In _x Ga _1-x P layer.

In the method of manufacturing a heterojunction bipolar transistor according to claim 9, a step of preparing a semiconductor substrate, a step of forming a collector layer on the semiconductor substrate,
A step of forming a base layer on the collector layer, a step of forming an emitter layer of a mesa structure having a regular mesa side surface on the base layer, a step of forming an emitter electrode on the emitter layer, an emitter electrode and a base A step of selecting a plane projection area including a layer but not including a normal mesa side surface, and a base electrode formed on the base layer in a self-aligned manner with respect to the emitter layer by forming a conductor layer in the plane projection area. And a step of forming.

In the method for manufacturing a heterojunction bipolar transistor according to claim 10, a step of preparing a semiconductor substrate, a step of forming a collector layer on the semiconductor substrate, and a step of forming a base layer on the collector layer. A step of forming a mesa-type emitter layer having a lower emitter layer on the base layer and having a regular mesa side surface, a step of forming an emitter electrode on the emitter layer, and the step of forming the emitter electrode and the base layer A step of selecting a plane projection region that does not include the forward mesa side surface, a step of forming a resist in the plane projection area, and a step of selectively etching the forward mesa side surface of the lower emitter layer of the emitter layer using the resist. Forming a conductor layer on the emitter electrode and the base layer, and thus forming a base electrode formed on the base layer in a self-aligned manner with respect to the emitter layer And a degree.

In the method of manufacturing a heterojunction bipolar transistor according to claim 11, a step of preparing a semiconductor substrate, a step of forming a collector layer on the semiconductor substrate, and a step of forming a base layer on the collector layer. A step of forming a thin film depletion layer on the base layer, a step of forming an emitter layer having a mesa structure having a regular mesa side surface on the thin film depletion layer, and a step of forming an emitter electrode on the emitter layer,
The steps of selecting a plane projection region including the emitter electrode and the thin film depletion layer but not including the normal mesa side face, forming a resist in the plane projection region, and selectively using the resist to form the forward mesa side face of the emitter layer A step of etching, a step of removing the resist, a step of forming a conductor layer on the emitter electrode and the thin film depletion layer, a heat treatment of the conductor layer,
And electrically connecting the conductor layer to the base layer through the thin film depletion layer, and forming a base electrode formed on the base layer in a self-aligned manner with respect to the emitter layer.

In the method of manufacturing a heterojunction bipolar transistor according to claim 12, the semiconductor substrate is GaAs of the first conductivity type, and the collector layer is the G of the first conductivity type.
an aAs layer, a lower collector layer, and an upper collector layer, which is a first conductivity type GaAs layer having a lower impurity concentration than the GaAs layer, and a base layer is a second conductivity type GaAs layer, and has a mesa structure. An emitter layer is a lower emitter layer, a first conductive type semiconductor material layer, an upper emitter layer is a first conductive type GaAs layer, and an emitter contact layer is a first conductive type InGaAs layer. The electrode has a WSi layer serving as a lower emitter electrode and a W layer serving as an upper emitter electrode, and the base electrode has a four-layer structure in which a Pt layer, a Ti layer, a Pt layer, and an Au layer are sequentially stacked.

In the method for manufacturing a heterojunction bipolar transistor according to claim 13, the thin film depletion layer is a thin semiconductor material layer.

In the method for manufacturing a heterojunction bipolar transistor according to claim 14, the semiconductor material layer is Al.
_x Ga _1-x As layer.

In the method of manufacturing a heterojunction bipolar transistor according to claim 15, the semiconductor material layer is In.
_x Ga _1-x P layer.

[0024]

1 to 17 show a heterojunction bipolar transistor (HB) according to an embodiment of the present invention.
A sectional view of (T) is shown. All cross-sectional views represent a cross-section that crosses the center of the emitter layer in a direction perpendicular to the orientation flat of the substrate. In addition, the orientation flat of the (0, -1, -1) plane orientation is (1, 0,
A lower collector layer 2 on a GaAs substrate 1 having a (0) plane orientation,
Up to the point where the upper collector layer 3 and the p ⁺ -GaAs base layer 4 are epitaxially grown, all the embodiments of the present invention are the same as the conventional example, and the description thereof will be omitted. The description will be given starting from forming each layer on the base layer 4. 2 and the subsequent figures, the illustration of the base layer 4 and the subsequent layers is also omitted.

Embodiment 1 As shown in FIG. 1, a semiconductor material layer 5c and an n ⁺ -GaAs layer 6c are formed on the base layer 4.
And a n ⁺ -In _0.5 Ga _0.5 As layer 7c having a three-layer structure 8c
To grow epitaxially. Then, as in the conventional method, a WSi having an emitter width of 2 μm and an emitter length of 10 μm is formed by using a resist (not shown) by the sputtering method and the RIE method.
A two-layer structure of a lower emitter electrode 9 made of a layer and an upper emitter electrode 10 made of a W layer is formed. Further, as shown in FIG. 2, in order to use the lower emitter electrode 9 as a mask when the mesa structure of the emitter layer 8 is formed later, the side surface of the lower emitter electrode 9 is etched by the RIE method to form the upper emitter electrode 10. As a mask, the side surface of the lower emitter electrode 9 is selectively removed by about 0.2 μm to form an emitter electrode 11 having a two-layer structure of the lower emitter electrode 9 and the upper emitter electrode 10.

Next, using the lower emitter electrode 9 as a mask, a mesa structure of the emitter layer 8 is formed as shown in FIG. 3, and at the same time, etching for exposing the base layer 4 is performed using tartaric acid and hydrogen peroxide solution. The etching is performed using a solution mixed at a ratio of 10: 1. Since the In _x Ga _1-x P is not removed by this etching solution if you are using In _x Ga _1-x P layer as the semiconductor material layer 5c of (x = 0.48), aqueous hydrochloric acid (e.g., hydrochloric acid: water = 1:
The In _x Ga _1-x P layer will be etched using a mixing ratio of 30). In the above HBT manufacturing process,
The film type, film thickness, production conditions, etc. of each layer are the same as those of the conventional example.

After the emitter layer 8 having the mesa structure is formed as described above, the emitter layer 11 and the base layer 4 are included in this embodiment, but the forward mesa side surface 8a of the emitter layer 8 is included.
By a lift-off method using a mask (not shown) having an opening having a shape corresponding to the plane projection area, the vicinity of the reverse mesa side surface 8b of the emitter layer 8 as shown in FIG. Base electrode 2 having a top surface shape
0 is formed on the base layer 4 in a self-aligned manner with respect to the emitter layer 8. At this time, the AA ′ cross section of FIG. 4 has a shape as shown in FIG. 5, and the base electrode 20 is not formed on the forward mesa side surface 8 a of the emitter layer 8. Incidentally, like the conventional example,
Pt, Ti and Pt formed on the upper emitter electrode 10
The four-layer structure 20a of Au and Au does not function as a base electrode.

In the HBT of this embodiment, the base resistance and the base-collector capacitance are increased by about 10% and about 5%, respectively, as compared with the conventional HBT, but the base electrode 20 is arranged in the order of the emitter layer 8. Since it is not formed on the mesa side surface 8a side but is formed only in the vicinity of the reverse mesa side surface 8b of the emitter layer 8,
Unlike the conventional case, the base electrode 20 and the hem portion 15 of the forward mesa side surface 8a of the emitter layer 8 are not electrically short-circuited, and the distance between the emitter layer 8 and the base electrode 20 is shortened (about 0. HBT can be manufactured with good productivity.

Embodiment 2 Also in this embodiment shown in FIGS. 6 to 10, as in the first embodiment shown in FIGS. 1 to 5, each layer is sequentially formed on the GaAs substrate 1, and the emitter electrode is formed on the emitter contact layer 7. from forming a 11 to the point where to form the emitter layer 8 of the mesa structure to produce a structure as shown in FIG. 6 is etched to expose the base layer 4, the semiconductor material layer 5c n-in _x
Except that it is formed as a Ga _1-x P layer (x = 0.48), it is exactly the same as the conventional and first embodiments.

Usually, of the forward mesa side surface 8a of the emitter layer 8, it is the forward mesa side portion 5a of the lower emitter layer 5 that is exposed to the outside of the end 16 of the upper emitter electrode 10. In this embodiment, The forward mesa side surface 5a of the emitter layer 5 is selectively etched so that the emitter layer 8 is located inside the end 16 of the upper emitter electrode 10.

In this embodiment, after the emitter layer 8 having a mesa structure is formed as shown in FIG. 3, the emitter electrode 11 and the base layer 4 are included, but the normal mesa side surface 8a of the emitter layer 8 is 4 μm wide, which is a plane projection area not included
A resist 2 as shown in FIG. 7 is formed on the base layer 4 and the upper emitter electrode 10 by a photolithography method using a mask (not shown) having holes each having a length of 9 μm.
1 and 21a are formed. At this time, as shown in FIG. 7, the resist 21 is formed on the base layer 4 so as to have a width of 1 μm along the reverse mesa side surface 8b of the emitter layer 8, and at the same time, the resist 21a is formed on the upper emitter electrode 10. It is formed with an offset of 0.5 μm from both ends in the emitter length direction.

Next, as shown in FIG. 8, the lower emitter layer 5 is formed of n-In _x so that the forward mesa side surface 5 a of the lower emitter layer 5 is located inside the end portion 16 of the upper emitter electrode 10.
The normal mesa side surface 5a of the Ga _{1 -x} P layer is selectively removed by using a hydrochloric acid aqueous solution (hydrochloric acid: water = 1: 30) as an etching solution. At this time, the lower emitter layer 5 is formed on the base layer 4.
Since the resist 21 is formed along the vicinity of the reverse mesa side surface 5b, the reverse mesa side surface 5b of the lower emitter layer 5 is hard to be etched.

After the emitter layer 8 is etched as described above, the base electrode 22 having the same shape as the conventional one is formed on the base layer 4 in a self-aligned manner with respect to the emitter layer 8 by the lift-off method as shown in FIG. 9 is formed along the forward mesa side surface 8a and the reverse mesa side surface 8b so as to surround the periphery of the emitter layer 8, the shape of the AA 'cross section of FIG. 9 is the same as that of the lower emitter layer 5 as shown in FIG. Since the mesa side surface 5a is located inside the end portion 16 of the upper emitter electrode 10, the emitter layer 8 and the base electrode 22 are not electrically short-circuited.

In this embodiment, unlike the prior art and the first embodiment, n-In _x Ga is used as the semiconductor material layer 5c.
_{Since the 1-x} P layer is used, the n-In _x Ga _1-x P layer is selectively removed after performing etching to form the mesa structure of the upper emitter layer 6 and the emitter contact layer 7. The mesa side surface 5a of the forward mesa is etched using a hydrochloric acid aqueous solution capable of At this time, the lower emitter layer 5
Since the resist 21 is formed on the base layer 4 along the vicinity of the reverse mesa side surface 5b to prevent the reverse mesa side surface 5b from being further etched, the forward mesa side surface 5a of the lower emitter layer 5 is selectively formed. When the base electrode 22 is formed later, the distance between the opposite mesa side surface 8b of the emitter layer 8 and the base electrode 22 is not increased and the base resistance and the base-collector capacitance are not increased. It is possible to form the base electrode 22 having the same shape as the above on the base layer 4 in the vicinity of the emitter layer 8 in a self-aligned manner with respect to the emitter layer 8, thereby improving the productivity.

Embodiment 3 FIG. In this embodiment shown in FIGS. 11 to 17, as shown in FIG.
An impurity concentration of 5 × 10 ¹⁷ cm ⁻³ and a thickness of 30 are formed so that carriers in the layer are completely depleted to form a depletion layer.
The lower emitter layer 23, which is a 0Å n-In _x Ga _1-x P layer (x = 0.48), and the n-GaAs layer 24c and n ⁺ -, which have an impurity concentration of 5 × 10 ¹⁷ cm ^-3 and a thickness of 700 Å. Three-layer structure 2 of GaAs layer 6c and n ⁺ -In _0.5 Ga _0.5 As layer 7c
5c and 5c are epitaxially grown, and then, as shown in FIG. 12, on the three-layer structure 25c, the emitter electrode 11 similar to the conventional first and second embodiments is formed by the sputtering method and the RIE method. .

Next, using the emitter electrode 11 as a mask, 3
The layer structure 25c is etched to form a mesa type emitter layer 25. As shown in FIG. 13, in this step, a solution obtained by mixing tartaric acid and hydrogen peroxide solution at a ratio of 10: 1 was used as an etching solution, and the n-GaAs layer 2 was formed.
4c is selectively removed to expose the lower emitter layer 23. Then, a resist 29 and a resist 29a as shown in FIG. 14 are formed as a plane projection region including the emitter electrode 11 and the base layer 4 but not including the normal mesa side surface 25a of the emitter layer 25, and having a width of 4 μm and a length of 9 μm. It is formed by a photolithography method using a mask (not shown) having a portion. At this time, the resist 29 is formed on the lower emitter layer 23 along the vicinity of the reverse mesa side surface 25b of the emitter layer 25 so as to have a width of 1 μm, and at the same time, the resist 29a is formed on the upper emitter electrode 10 as an emitter. It is formed so as to be offset by 0.5 μm from both ends in the longitudinal direction.

After that, the mixed mesa of tartaric acid and hydrogen peroxide is again used as an etching solution to selectively remove the forward mesa side surface 25a of the emitter layer 25.
As shown in FIG. 5, the entire forward mesa side surface 25a of the emitter layer 25 is selectively removed so that the skirt portion 26 of the forward mesa side surface 25a of the emitter layer 25 is located inside the end 16 of the upper emitter electrode 10. You can After this resist 29
And 29a are removed.

After the emitter layer 25 is etched as described above, the base electrode 27 having a four-layer structure of Pt, Ti, Pt, and Au is formed by the lift-off method as shown in FIGS. It is formed on the layer 23 in a self-aligned manner with respect to the emitter layer 25. At this time, the four-layer structure 27a is simultaneously formed on the upper emitter electrode 10, but the four-layer structure 27a does not function as a base electrode.

The base electrode 27 formed in this step is a base electrode having the same shape as the base electrodes 14 and 22 directly formed on the base layer 4 in the conventional example and the second embodiment. However, at this time, first, a four-layer structure serving as the base electrode 27 is formed on the lower emitter layer 23 with respect to the emitter layer 25 in the vicinity of the forward mesa side surface 25a and the reverse mesa side surface 25b so as to surround the periphery of the emitter layer 25. It is formed by the lift-off method in a self-aligned manner. Then, when the base electrode 27 is heat-treated, Pt of the Pt layer 28 of the lowermost layer thermally diffuses in the lower emitter layer 23, so that the base electrode 27 and the base layer 4 are electrically connected. Thus, the base electrode having a base width of 1 μm as shown in FIG. 17 is formed around the emitter layer 25.

As described above, the base electrode 27 having the same shape as the conventional one as shown in FIGS. 16 and 17 is conducted to the base layer 4 by the lift-off method using heat treatment so as to surround the periphery of the emitter layer 25. However, the emitter layer 25 and the base electrode 22 are not electrically short-circuited even if they are formed.

In this embodiment, the emitter layer 2
In performing the etching for forming the mesa type structure of 5, the resist 21 for preventing the etching of the reverse mesa side surface 25b of the emitter layer 25 is formed along the reverse mesa side surface 25b after performing the normal etching. Emitter layer 23
Since it is formed on the back surface and is etched again, the forward mesa side surface 25a of the emitter layer 25 can be selectively removed, and when the base electrode 27 is formed later, the reverse mesa side surface 25b of the emitter layer 25 is formed. The base electrode 27 having the same shape as that of the conventional one is formed on the emitter layer 2 without separating the base electrode 27 from the base electrode 27 and increasing the base resistance and the capacitance between the base and the collector.
5 can be formed on the base layer 4 in the vicinity of 5, and productivity can be improved. Furthermore, since the lower emitter layer 23 is thinned to the extent that carriers in the layer are depleted and left on the base layer 4, a recombination current between the pn junction between the base layer 4 and the emitter layer 25. It is possible to suppress the occurrence of the above and improve the performance of the device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a step of sequentially epitaxially growing an emitter contact layer on a substrate in a manufacturing process of an HBT.

FIG. 2 is a cross-sectional view showing a stage in which an emitter electrode is formed on an emitter contact layer in the HBT manufacturing process.

FIG. 3 is a cross-sectional view showing a step of forming a mesa structure of an emitter layer by etching in a manufacturing process of HBT.

FIG. 4 is a top view showing a step of forming a base electrode in the HBT manufacturing process.

FIG. 5 is a cross-sectional view showing a step of forming a base electrode in the HBT manufacturing process.

FIG. 6 is a cross-sectional view showing a step of manufacturing a mesa structure of the emitter layer by etching using the emitter electrode as a mask in the manufacturing process of the HBT.

FIG. 7 is a top view showing a step of forming a resist used for selectively removing the mesa-type side of the mesa structure of the emitter layer on the emitter electrode and the base layer in the manufacturing process of the HBT. is there.

FIG. 8 is a view showing a step of selectively manufacturing the mesa structure side of the emitter layer by using a resist for preventing the etching of the reverse mesa structure side of the emitter layer in the manufacturing process of the HBT. It is sectional drawing which shows the step removed.

FIG. 9 is a top view showing a step of forming a base electrode on the base layer around the emitter layer in which the forward mesa type side of the emitter layer is selectively removed in the manufacturing process of the HBT.

FIG. 10 is a cross-sectional view showing a step of forming a base electrode on the base layer around the emitter layer in which the forward mesa type side of the emitter layer is selectively removed in the manufacturing process of the HBT.

FIG. 11 is a cross-sectional view showing a step of forming a thinned lower emitter layer, an intermediate emitter layer, an upper emitter layer, and an emitter contact layer on a base layer in a manufacturing process of an HBT.

FIG. 12 is a cross-sectional view showing a step of forming an emitter electrode on the emitter contact layer in the HBT manufacturing process.

FIG. 13 is a cross-sectional view showing a step in the HBT manufacturing process in which a mesa structure is manufactured by etching up to the intermediate emitter layer using the emitter electrode as a mask.

FIG. 14 is a top view showing a step of forming a resist used for selectively removing the normal mesa side of the mesa structure of the emitter layer on the emitter electrode and the lower emitter layer in the manufacturing process of the HBT. Is.

FIG. 15 shows a step in the HBT manufacturing process in which the forward mesa side of the mesa structure of the emitter layer is selectively removed using a resist for preventing etching of the reverse mesa side of the emitter layer. FIG.

FIG. 16 is a cross-sectional view showing a step of forming a base electrode by heat treatment and a lift-off method around the emitter layer in which the forward mesa type side of the emitter layer is selectively removed in the manufacturing process of the HBT.

FIG. 17 is a top view showing a step of forming a base electrode by heat treatment and a lift-off method around the emitter layer in which the forward mesa type side of the emitter layer is selectively removed in the HBT manufacturing process.

FIG. 18 is a top view of a conventional HBT.

FIG. 19 is a sectional view of a conventional HBT.

FIG. 20 is a cross-sectional view showing a step of sequentially epitaxially growing up to an emitter contact layer on a substrate in a conventional HBT manufacturing process.

FIG. 21 is a cross-sectional view showing a step of forming a WSi layer, a W layer, and a resist used in an etching step for forming an emitter electrode on an emitter contact layer in a conventional HBT manufacturing process.

FIG. 22 is a cross-sectional view showing a step of performing etching for forming an emitter electrode using a resist in a conventional HBT manufacturing process.

FIG. 23 is a cross-sectional view showing a step of selectively removing a side surface of a lower emitter electrode by using the upper emitter electrode as a mask in a conventional HBT manufacturing process.

FIG. 24 is a front sectional view showing a step of performing etching for producing a mesa structure of the emitter layer in the conventional HBT manufacturing process.

FIG. 25 is a side sectional view showing a step of performing etching for producing a mesa structure of an emitter layer in a conventional HBT manufacturing process.

FIG. 26 is a cross-sectional view showing a state in which a base electrode and an emitter layer are in contact with each other and electrically short-circuited in a conventional HBT manufacturing process.

[Explanation of symbols]

1 GaAs substrate, 2 a lower collector layer, 3 an upper collector layer, 4 the base layer, 5c semiconductor material layer, 5 a lower emitter layer, 6c n ⁺ -GaAs layer, 6 an upper emitter _{^{layer, 7c n + -In 0.5 Ga 0.5}} As layer , 7 emitter contact layer, 8 emitter layer, 8a forward mesa side surface,
8b reverse mesa side surface, 8c three-layer structure, 9a WSi layer,
9 lower emitter electrode, 10a W layer, 10 upper emitter electrode, 11 emitter electrode, 14 base electrode, 2
0 base electrode, 22 base electrode, 23 lower emitter electrode, 24 intermediate emitter layer, 27 base electrode.

Claims (15)

[Claims] 1. A semiconductor substrate, a collector layer provided on the semiconductor substrate, a base layer provided on the collector layer, and a mesa structure having a regular mesa side surface provided on the base layer. An emitter layer, an emitter electrode provided on the emitter layer, and provided in a plane projection region including the emitter electrode and the base layer but not including the forward mesa side surface, and at least on the base layer. A heterojunction bipolar transistor having a base electrode formed in a self-aligned manner with respect to the emitter layer and spaced from the forward mesa side surface of the emitter layer. 2. A semiconductor substrate, a collector layer provided on the semiconductor substrate, a base layer provided on the collector layer, a lower emitter layer provided on the base layer, and a forward mesa side surface. An emitter layer having a mesa structure having, an emitter electrode provided on the emitter layer, and provided in a plane projection region including the emitter electrode and the base layer, and at least on the base layer with respect to the emitter layer. And a base electrode formed in a self-aligned manner, the side surface of the forward mesa of the emitter layer is set back by etching only for the lower emitter layer,
A heterojunction bipolar transistor located inside the emitter electrode and separated from the base electrode. 3. A semiconductor substrate, a collector layer provided on the semiconductor substrate, a base layer provided on the collector layer, and a mesa structure having a regular mesa side surface provided on the base layer. An emitter layer, an emitter electrode provided on the emitter layer, and provided in a plane projection region including the emitter electrode and the base layer, and formed on at least the base layer in a self-aligned manner with respect to the emitter layer. A side surface of the emitter layer, the side surface of the forward mesa of the emitter layer is set back by etching with respect to the entire emitter layer, is located inside the emitter electrode, and is separated from the base electrode. Heterojunction bipolar transistor. 4. The heterojunction bipolar transistor according to claim 3, further comprising a thin film depletion layer provided on the base layer, wherein the base electrode is electrically connected to the base layer through the thin film depletion layer. 5. The first conductive type GaAs is used as the semiconductor substrate.
Wherein the collector layer includes a lower collector layer which is a first-conductivity-type GaAs layer and an upper collector layer which is a first-conductivity-type GaAs layer having an impurity concentration lower than that of the GaAs layer. Is a second conductive type GaAs layer, and the first conductive type semiconductor material layer in which the emitter layer of the mesa type structure is a lower emitter layer and the first emitter type semiconductor material layer is an upper emitter layer.
A conductive type GaAs layer and a first conductive type In _x Ga _{1 -x} As layer serving as an emitter contact layer are provided, and the emitter electrode is a WSi layer serving as a lower emitter electrode, and a W layer serving as an upper emitter electrode. 5. The heterojunction bipolar transistor according to claim 1, wherein the base electrode has a four-layer structure in which a Pt layer, a Ti layer, a Pt layer, and an Au layer are sequentially stacked. 6. The heterojunction bipolar transistor according to claim 4, wherein the thin film depletion layer is a thinned semiconductor material layer. 7. The heterojunction bipolar transistor according to claim 5, wherein the semiconductor material layer is an Al _x Ga _1-x As layer. 8. The heterojunction bipolar transistor according to claim 5, wherein the semiconductor material layer is an In _x Ga _{1 -x} P layer. 9. A step of preparing a semiconductor substrate, a step of forming a collector layer on the semiconductor substrate, a step of forming a base layer on the collector layer, and a step of forming a mesa side surface on the base layer. Forming an emitter layer having a mesa structure; forming an emitter electrode on the emitter layer; selecting a plane projection region including the emitter electrode and the base layer but not including the normal mesa side surface; Forming a conductor layer in the plane projection region and thereby forming a base electrode formed on the base layer in a self-aligned manner with respect to the emitter layer. . 10. A step of preparing a semiconductor substrate, a step of forming a collector layer on the semiconductor substrate, a step of forming a base layer on the collector layer, and a step of forming a lower emitter layer on the base layer. Then, a step of forming an emitter layer having a mesa structure having a forward mesa side surface, a step of forming an emitter electrode on the emitter layer, and a plane including the emitter electrode and the base layer but not including the forward mesa side surface. Selecting a projection region, forming a resist in the plane projection region, selectively etching the forward mesa side surface of the lower emitter layer of the emitter layer using the resist, and the emitter A conductor layer is formed on the electrode and the base layer, and thus a base electrode is formed on the base layer in a self-aligned manner with respect to the emitter layer. Method of manufacturing a heterojunction bipolar transistor having a step. 11. A step of preparing a semiconductor substrate, a step of forming a collector layer on the semiconductor substrate, a step of forming a base layer on the collector layer, and a thin film depletion layer on the base layer. The step of forming an emitter layer having a mesa structure having a regular mesa side surface on the thin film depletion layer, forming an emitter electrode on the emitter layer, and including the emitter electrode and the thin film depletion layer. , Selecting a plane projection region that does not include the normal mesa side surface, forming a resist in the plane projection region, and selectively etching the normal mesa side surface of the emitter layer using the resist A step of removing the resist, a step of forming a conductor layer on the emitter electrode and the thin film depletion layer, a heat treatment of the conductor layer, and thus the conductivity. Conducting a layer through the thin film depletion layer to the base layer, and forming a base electrode formed on the upper base layer in a self-aligned manner with respect to the emitter layer. . 12. The semiconductor substrate is a first conductivity type GaA.
s, the collector layer includes a lower collector layer that is a first-conductivity-type GaAs layer, and an upper collector layer that is a first-conductivity-type GaAs layer having an impurity concentration lower than that of the GaAs layer. The base layer is a second conductive type GaAs layer, the emitter layer having the mesa structure is a first conductive type semiconductor material layer serving as a lower emitter layer, and the first emitter type semiconductor material layer serving as an upper emitter layer.
A conductive type GaAs layer and a first conductive type In _x Ga _{1 -x} As layer serving as an emitter contact layer are provided, and the emitter electrode is a WSi layer serving as a lower emitter electrode, and a W layer serving as an upper emitter electrode. 12. The method for manufacturing a heterojunction bipolar transistor according to claim 9, wherein the base electrode has a four-layer structure in which a Pt layer, a Ti layer, a Pt layer, and an Au layer are sequentially stacked. 13. The method of manufacturing a heterojunction bipolar transistor according to claim 11, wherein the thin film depletion layer is a thin semiconductor material layer. 14. The semiconductor material layer is Al _x Ga _{1 -x} As.
The method for manufacturing a heterojunction bipolar transistor according to claim 12, wherein the heterojunction bipolar transistor is a layer. 15. The method of manufacturing a heterojunction bipolar transistor according to claim 12, wherein the semiconductor material layer is an In _x Ga _1-x P layer.