JPH09181284A - Semiconductor integrated circuit device and multistage connecting structure of its circuit cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the wiring efficiency of the wiring connecting the input- output terminals of adjacent circuit cells of a gate array to each other and to shorten the propagation delay time caused by the wiring. SOLUTION: Circuit cells 1a and 1b are adjacently arranged in the X-axis direction. The output terminal 3a of the cell 1a and the input terminal 3b of the cell 1b are respectively provided at the central parts of the adjacent sides of the cells 1a and 1b so that the terminals 3a and 3b can constitute one input- output terminal and a contact hole 4 which connects the terminals 3a and 3b to each other is formed between the adjacent sides. Therefore, no wiring space is required for connecting circuits cells adjacently arranged in the X-axis direction and the propagation delay time is shortened. The circuit cells 1a and 1b can be connected to other circuit cells through wiring formed of the same layer as that of the terminal 3a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a multi-stage connection structure of its circuit cells, and more particularly, in standard cell and gate array type semiconductor integrated circuit devices, circuit cells are arranged and circuit cells are connected to each other. In this case, the input terminal and the output terminal in the circuit cell are formed in different layers on the boundary area between adjacent circuit cells, and are arranged at the target positions with respect to the center line of the circuit cell. In this state, the present invention relates to a semiconductor integrated circuit device in which wiring efficiency is improved and delay time is reduced by connecting respective terminals with through holes, and a multi-stage connection structure of circuit cells thereof.

[0002]

2. Description of the Related Art With the progress of miniaturization technology of semiconductor elements, the scale of circuits to be integrated in standard cell and gate array type semiconductor integrated circuit devices is increasing and the operating frequency thereof is also increasing.

Generally, the gate array method is also called a master slice method, in which circuit elements such as transistors for forming a logic gate are regularly arranged, and a semiconductor wafer which has been subjected to official diffusion is prepared in advance and requested by a user. Thus, a custom semiconductor integrated circuit device is completed through a metal wiring process for forming the desired circuit function.

Referring to FIGS. 5A and 5B showing an example of the layout outline of the gate array system, the input / output buffers 51 are arranged on the semiconductor chip 50 in rows along the periphery thereof. A peripheral region 52 to be arranged, a spread type having an internal region 54 in which the circuit cells 53 are spread over the entire surface, and a peripheral region 57 in which input / output buffers 56 are arranged in a line along the periphery of the semiconductor chip 55. When,
There is a continuous column array type in which a plurality of circuit cells 58 are arranged in columns and an internal region 60 used as a wiring region 59 exists between the columns.

To improve the efficiency of wiring for connecting circuit cells arranged inside these semiconductor device,
Various methods have been proposed for reducing the signal propagation delay between circuit cells. As an example, FIG. 6A showing a plan view of the input / output terminal arrangement of the circuit cells and FIG. 6A showing a plan view showing a state in which the input / output terminals are connected when the circuit cells are arranged adjacent to each other. Referring to b), the circuit cell 61 has an input terminal 62 and an output terminal 63 arranged side by side in the horizontal direction near the center of the cell.

On the other hand, there are a plurality of circuit blocks 61a in which the input terminals 62a and the output terminals 63a are arranged and a plurality of circuit blocks 61b in which the input terminals 62b and the output terminals 63b are arranged, two in FIG. 6B. Are arranged side by side in the direction of the output terminal 63b and the input terminal 62b.
The spaces are connected by wiring 64.

[0007]

In the conventional semiconductor device described above, as shown in FIGS. 7 and 8, the input terminal 7 is used.
2, 72a, 72b and output terminals 73, 73a, 73b
Is arranged inside the circuit cell 71, and when connecting the adjacent circuit cells 71a and 71b, it is necessary to connect by using wiring, so that the delay time increases due to the increase of the wiring load, and There is a drawback that the wiring efficiency between the circuit cells is lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having improved wiring efficiency and reduced delay time and a multi-stage connection structure of the circuit cells thereof, in view of the above-mentioned drawbacks. is there.

[0009]

The semiconductor integrated circuit device of the present invention is characterized in that it has a plurality of rectangular circuit cells each having a length equal to each other in the Y-axis direction on a plane. In a semiconductor integrated circuit device composed of cell rows arranged in an array, the input terminal and the output terminal in the circuit cell are arranged on a boundary region with another circuit cell adjacently arranged, The input terminal and the output terminal are arranged at the edge portions of the circuit cell at the target position with the center line of the circuit cell interposed therebetween, and the input terminal and the output terminal are provided with a polycrystalline silicon layer, a first metal layer and a second metal layer. And at least two of the layers.

A plurality of circuit cells are arranged in the X-axis direction and Y
By arranging the terminals adjacent to each other in the axial direction or both directions, the respective terminals are connected to the first and second terminals only when the respective input terminals and the output terminals are connected.
If the metal layer is a through-hole connection, the polycrystalline silicon layer and the first or second metal layer are contact-connected.

A feature of the multi-stage connection structure of circuit cells of the present invention is that the circuit cells have a plurality of rectangular circuit cells each having the same length in the Y-axis direction on a plane, and the circuit cells are arranged in an array. In a multi-stage connection structure of circuit cells that is configured by a cell row and that connects the input terminal and the output terminal between these circuit cells, another input terminal and the output terminal in the circuit cell are arranged adjacent to each other. On the boundary area with the circuit cell in the X-axis direction of the circuit cell or Y
The input terminal and the output terminal are arranged at the edge portions of the circuit cell at the target position with the center line in the axial direction interposed therebetween, and each of the input terminal and the output terminal includes a polycrystalline silicon film and a first or second metal film. By using a circuit cell formed by using any one of the above, and arranging a plurality of the circuit cells adjacent to each other in the X-axis direction, the Y-axis direction, or both of these directions,
The through hole connection is made only when the one input terminal and the other output terminal which are adjacent to each other are connected.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 (a) is a plan view of the arrangement of input / output terminals of a circuit cell showing a first embodiment of a semiconductor integrated circuit device of the present invention, and FIG. 1 (b) is a plan view of this circuit cell in the X-axis direction. FIG. 4 is a plan view showing a state in which circuit cells are adjacent to each other and the input / output terminals are connected to each other.

Referring to FIG. 1A, the input terminals 2 and 2 are respectively provided at substantially central portions of the two opposite sides of the circuit cell 1 on the left and right sides.
The output terminal 3 is arranged. The circuit cells 1 are arranged so that the edges of the circuit cells 1 coincide with the central portions of these terminals.

As the circuit cell 1, for example, an inverter 10
Referring to FIG. 2 showing a layout of 0, this layout is an example in which the positions of the input terminals and the output terminals for applying the present invention to the layout example of the known art are changed. In the example of the n-type substrate, a power supply potential line made of the first metal layer 11a, a ground potential line made of the second metal layer 11b,
P ⁺ forming the source electrode of a P-channel transistor
Contact 17 for connecting the diffusion layer to the first metal layer 11b
And a contact 16 for connecting the first metal layer 11b to the substrate via the n ⁺ diffusion layer, a P-channel type and a P-w type.
a contact connecting the polycrystalline silicon layer 13 forming the gate electrode of each n-channel transistor formed in the well region 14 to the input terminal 2, ap ⁺ diffusion layer forming the drain electrode of the p-channel transistor, and n. The contacts 18 and 20 respectively connecting the n ⁺ diffusion layers forming the drain electrode of the channel type transistor to the first metal layer 11c, and the first metal layer 11c connected to the second metal layer 12 and led to the contact of the output terminal 3. The through hole 19 for connecting the contact, the contact 21 for connecting the n ⁺ diffusion layer forming the source electrode of the n-channel transistor to the first metal layer 11a, and the first metal layer 11a are p
⁺ Contact 2 connecting to P-well via diffusion layer
2 and.

On the other hand, referring to FIG. 1B, for example, the circuit cells 1a and 1b as shown in FIG. 1A are arranged adjacent to each other in the X-axis direction. The output terminal 3 of the circuit cell 1a is provided at the center of the side of the circuit cells arranged adjacent to each other.
a and the input terminal 3b of the circuit cell 1b are arranged so as to form one input / output terminal, and a contact hole 4 for connecting the output terminal 3a and the input terminal 2b is formed in the center thereof.

The feature of the present invention resides in that in FIG. 2, the input terminals 2a and 2b in the circuit cells 1a and 1b are included.
And the output terminals 3a and 3b are formed in different layers on the boundary area between the circuit cells 1a and 1b adjacent to each other in the X-axis direction, with respect to the center line of the circuit cell. It is located at the target position.

Circuit cells 1a and 1 arranged adjacent to each other in the X-axis direction
Since the output terminal 3a of the circuit cell 1a and the input terminal 2b of the circuit cell 1b are arranged at the same position in different layers when connecting with b, the circuit cells adjacent to each other in the X direction only through holes 4 are provided. It becomes possible to connect 1a and 1b.

For example, the inverter 100 shown in FIG.
Referring to FIG. 3, which shows a cross-sectional view taken along the section line AA in the case where they are arranged adjacent to each other in the axial direction, referring to FIG.
And 100b, the polycrystalline silicon layer 13 is formed on the substrate via the oxide film SiO ₂ , and the gate electrodes are led to the input terminals 2a and 2b.

A first metal layer 11 is formed on the polycrystalline silicon layer 13 via an oxide film SiO ₂ , and a drain electrode is connected to a second metal layer 18 formed on the drain electrode via a through hole 19. To do.

An oxide film Si is formed on the first metal layer 11.
The second metal layer 18 formed through O ₂ has the output terminal 3a.
And 3b respectively.

These inverters 100a and 100
b adjacently arranged, and the output terminal 3 of the inverter 100a
When a is connected to the input terminal 2b of the inverter 100b, the contact hole 4 is formed to connect the polycrystalline silicon layer 13 derived from the gate electrode of the inverter 100b and the second metal layer 18.

On the other hand, the inverter 100c arranged adjacent to the inverter 100b is an example in which the input terminal 2c is not connected to the output terminal 3b of the inverter 100b. That is, although they are arranged adjacent to each other, the contact hole 4 described above is not formed, so that the polycrystalline silicon layer 13 and the second metal layer 18 are not connected.

In the above-mentioned example, the input terminal is formed of polycrystalline silicon and the output terminal is formed of the second metal layer. However, by partially changing the layout of the circuit cell, polycrystalline silicon and It is obvious that it can be realized by one metal layer or a combination of each of the first metal layer and the second metal layer.

In the conventional circuit cell, if the input terminal and the output terminal in the circuit cell are located near the center of the circuit cell, the wiring required for connecting adjacent circuit cells is at least The wiring that is (1/2) × 2 times the size of the circuit cell in the X-axis direction is required, but it is completely unnecessary in the present invention.

Therefore, the wiring area required for connecting the circuit cells adjacent to each other in the X-axis direction, which is conventionally required, becomes unnecessary, and the circuit area can be used for connection between other circuit cells.

At the same time, since a wiring for connecting the adjacent cells is not required, the delay time due to this wiring can be reduced.

On the other hand, regarding the connection with other circuit cells,
Connection is possible by drawing out the wiring formed in the same layer as the output terminal 3a of the circuit cell 1a. Further, when adjacent cells are not connected to each other, the layers forming the input terminal and the output terminal are different from each other, and therefore the cells are not connected only by being arranged adjacent to the end.

FIG. 3 shows the structure of a circuit cell according to the second embodiment of the present invention, and FIG. 4 is a semiconductor in which circuit cells adjacent to each other in the Y-axis direction are connected using the circuit cell according to the second embodiment. It is a device.

Referring to FIG. 3, the circuit cell 5 is an input terminal 6 at the edge of the left side and an input terminal at the edge of the right side at the center of the two sides facing in the X-axis direction. 7 is arranged and is an input terminal 8 at the edge of the upper side and an output terminal 9 at the edge of the right side at the center of the two sides facing in the Y-axis direction.
Is arranged.

On the other hand, referring to FIG. 4, for example, the circuit cells 5b and 8b as shown in FIG. 3 are arranged adjacent to each other in the Y-axis direction. This adjacent circuit cell a
And 5b are arranged at the center of the cell sides so that the output terminal 9a of the circuit cell 5a and the input terminal 7b of the circuit cell 1b form one input / output terminal, and the output terminal 9a and the input terminal are formed at the center thereof. Contact hole 10 for connecting to 7b
Are formed.

A feature of the present invention is that the input terminal 7 and the output terminal 9 are provided in FIG. 3 and the input terminals 7a and 7b and the output terminals 9a and 9b are provided in FIG.

In FIG. 4, by providing the input terminals 7a and 7b and the output terminals 9a and 9b, not only the connection of the circuit cells arranged adjacent to each other in the X-axis direction but also the circuit arranged adjacent to each other in the Y-axis direction. The cells 5a and 5b can be connected only by the through hole 10.

In the conventional circuit cell, if the input terminal and the output terminal in the circuit cell are located near the center of the circuit cell, the wiring required to connect the circuit cells arranged adjacent to each other is: The wiring length of (1/2) × 2 times the size of the circuit cell in the Y-axis direction was required at least, but in the present invention, it is completely unnecessary.

Therefore, as in the first embodiment, the wiring area required for connecting the circuit cells adjacent to each other in the Y-axis direction, which has been conventionally required, becomes unnecessary, and the connection between other circuit cells is eliminated. Can be used for At the same time, it is possible to reduce the signal propagation delay time caused by the wiring for connecting the cells arranged adjacent to each other.

Regarding the connection with other circuit cells, the connection can be made by drawing out the wiring in the same layer as the output terminal 9a of the circuit cell 5a. Further, when adjacent cells are not connected to each other, the layers forming the input terminal and the output terminal are different from each other, and therefore the cells are not simply connected to each other to be connected.

[0036]

As described above, according to the semiconductor device of the present invention, the input terminal and the output terminal in the circuit cell are formed in different layers on the boundary region between adjacent circuit cells, and the circuit cell is formed. On the center line in the X-axis direction and facing two edges, and on the center line in the Y-axis direction, facing two edges, and connecting the terminals with through holes. By doing so, the connection wiring, which has been conventionally required, is not required, so that it is possible to achieve higher integration by improving the wiring efficiency and reduce the signal propagation delay time by the wiring for connecting circuit cells to achieve higher speed. .

[Brief description of the drawings]

FIG. 1A is a plan view showing an input / output terminal arrangement of a circuit cell according to a first embodiment of the present invention. FIG. 2B is a plan view of a main portion of the circuit cell shown in FIG. 1A, in which the input and output terminals of the circuit cells adjacent in the X-axis direction are connected to each other.

FIG. 2 is a plan view showing an example of a layout of circuit cells.

FIG. 3 is a cross-sectional view schematically showing a connection state and a non-connection state of input terminals and output terminals when circuit cells are arranged adjacent to each other.

FIG. 4A is a plan view showing a circuit cell according to a second embodiment of the present invention. FIG. 4B is a plan view of a main portion of a semiconductor integrated circuit device in which circuit cells adjacent to each other in the X-axis direction are connected by using the circuit cell shown in FIG.

FIG. 5A is a plan view of a continuous column array type gate array. (B) It is a top view of the spread type gate array.

FIG. 6A is a plan view showing an example of a conventional circuit cell. (B) It is a top view which shows an example of the principal part of the circuit cell of the semiconductor integrated circuit device which connected the circuit cell adjacent to the X-axis direction using the conventional circuit cell.

[Explanation of symbols]

1, 1a, 1b, 5, 5a, 5b, 61, 61b Circuit cells 2, 2a, 2b, 6, 6a, 6b, 7, 7a, 7b, 6
2, 62a, 62b input terminals 3, 3a, 3b, 8, 8a, 8b, 9, 9a, 9b, 6
3, 63a, 63b Output terminal 4 Contact for connecting metal layer and polycrystalline silicon layer 19 Through hole for interconnecting metal layer 14 Wiring for connecting circuit cell 50 Continuous column array type gate array 51, 56 Input / output buffer 52 , 57 Peripheral region 53, 58 Circuit cell 54, 60 Internal region 100 Inverter 100a, 100b, 100c Inverter shown in a schematic sectional view

Claims (3)

[Claims] 1. A semiconductor integrated device having a plurality of rectangular circuit cells each having a length equal to each other in the Y-axis direction on a plane and having a plurality of circuit cells arranged in an array. In the circuit device, the circuit located at a target position on a boundary region with another circuit cell in which the input terminal and the output terminal in the circuit cell are adjacently arranged and a center line of each of the circuit cells is sandwiched therebetween. The input terminal and the output terminal are arranged at the cell edge portion and are formed by using at least two layers of a polycrystalline silicon layer, a first metal layer and a second metal layer. A characteristic semiconductor integrated circuit device. 2. A plurality of the circuit cells are arranged adjacent to each other in the X-axis direction, the Y-axis direction, or both directions,
Only when the respective input terminals and the output terminals are connected, if the respective terminals are the first and second metal layers, the through-hole connection is performed, and the polycrystalline silicon layer and the first or second metal layer are connected. The semiconductor integrated circuit device according to claim 1, wherein contact connection is made with a metal layer. 3. A plurality of circuit cells each having a rectangular shape whose lengths in the Y-axis direction on the plane are equal to each other, and the circuit cells are arranged in an array and are formed. In a multi-stage connection structure of circuit cells connecting an input terminal and an output terminal between circuit cells, the input terminal and the output terminal in the circuit cell are on a boundary region with another circuit cell adjacently arranged, The input terminal and the output terminal are arranged at the edge portion of the circuit cell at a target position across the center line of the circuit cell in the X-axis direction or the Y-axis direction, and each of the input terminal and the output terminal has a polycrystalline silicon film and A circuit cell formed using either the first or second metal film is used, and a plurality of the circuit cells are arranged in the X-axis direction and Y-axis direction.
A multi-stage connection structure of circuit cells, wherein by arranging them adjacent to each other in the axial direction or both of these directions, a through hole or a contact connection is made only when the adjacent one input terminal and the other output terminal are connected.