JPH09181299A - Charge-voltage conversion circuit and solid-state imaging device - Google Patents

Abstract

The present invention relates to a charge-voltage conversion circuit, which widens an output dynamic range by increasing a gate voltage of an output transistor immediately after a reset operation is completed. A capacitor C having one end connected to a ground line GND,
A reset transistor T11 having a source connected to the other end of the capacitor C, a drain connected to a reset power supply, and a gate connected to a reset signal source, and a gate connected to the other end of the capacitor C to output the source Of the output transistor T21 whose drain is connected to the power supply line VDD and one end of which is connected to the source of the transistor T21 and whose other end is connected to the ground line G.
A load resistor RL1 connected to ND and a reset auxiliary transistor T31 having a drain connected to the source of the transistor T21 and a source connected to the ground line GND are provided, and the transistor T31 has a capacitance C when resetting the circuit. The ground line GND connected to one end of the transistor is connected to the source of the transistor T21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-voltage conversion circuit and a solid-state image pickup device, for example, a circuit for converting charges generated by a photodiode into a voltage and an application device thereof.

[0002]

2. Description of the Related Art In recent years, solid-state image pickup devices have been widely used in line sensors and image sensors. The line sensor converts the signal charge generated by the one-dimensionally arranged photodiodes into a voltage. The image sensor converts the signal charge generated by the two-dimensionally arranged photodiodes into a voltage. These sensors can not only record images but also perform various image analyzes and observations at remote locations. A charge-voltage conversion circuit that converts signal charges into a voltage is incorporated in such a solid-state imaging device. The charge-voltage conversion circuit is desired to have a wide output signal dynamic range in order to drive the solid-state imaging device at a low voltage. The output signal dynamic range is the width from the level (black level) when there is no signal charge to the level (white level) when there is the most signal charge.

Next, a solid-state image pickup device to which a charge-voltage conversion circuit is applied will be described. FIG. 6 shows a configuration diagram and an operation waveform diagram of a solid-state imaging device according to a conventional example. FIG.
In (A), 1 is a photodiode that receives light to generate signal charges, 2 is a transfer circuit that transfers signal charges, 3
Is a signal charge-voltage conversion circuit for converting the signal charge into a voltage,
T3 is a selection transistor for enabling the output of the signal charge-voltage conversion circuit 3.

The signal charge-voltage conversion circuit 3 comprises a resetting transistor T1, an output transistor T2, a load resistor RL and a capacitance C. Note that the reset of the signal charge-voltage conversion circuit means an operation of sweeping out the signal charges accumulated in the electrostatic capacitance to the outside. The capacitance C includes a gate capacitance generated between the gate of the transistor T1 and the substrate, a diffusion layer capacitance between the source and the substrate, and the transistor T.
The gate capacitance generated between the second gate and the substrate and the floating capacitance generated between the wiring and the substrate are used.

Next, the operation of the solid-state image pickup device will be described with reference to FIG. First, the signal charge-voltage conversion circuit 3 is reset. The reset operation is performed by the transistor T1.
This is performed by inputting an "H" level reset signal (φR) to the gate and inputting a reset voltage (VDR) to the drain. By this reset operation, the signal charge accumulated in the capacitor C is swept out. Then, the gate of the output transistor T2 after the completion of the reset operation is kept substantially at the reset voltage. At this time as well, the photodiode 1 receiving the light is generating signal charges.

When the reset operation is completed, the signal charge generated in the photodiode 1 is accumulated in the electrostatic capacitance C of the signal charge-voltage conversion circuit 3. At this time, the transfer circuit 2 transfers the signal charge based on the transfer clock signal (φT). The signal charge becomes the gate voltage of the transistor T2. Since the signal charge is usually an electron (negative charge),
The more electrons are stored in the capacitor, the lower the gate voltage of the transistor T2 is. As the gate voltage of the transistor T2 decreases, the on resistance of T2 increases.

Next, "H" is applied to the selection transistor T3.
When the level output enable signal (φC) is input,
The load resistance RL is connected to the source of the transistor T2. As a result, the output voltage (VOUT) which is almost resistance-divided by the ON resistance of the transistor T2 and the load resistance RL.
) Is output from the source of the transistor T3. When the output voltage is output, the reset operation of the signal charge-voltage conversion circuit 3 starts. It is possible to convert the signal charge into a voltage by repeating the accumulation of the signal charge and the sweeping out thereof.

[0008]

However, in the solid-state image pickup device to which the signal charge-voltage conversion circuit according to the conventional example is applied, the present inventor has confirmed that the output signal dynamic range is narrowed. The dynamic range is
The source voltage of the output transistor T2 immediately after the reset operation of the signal charge-voltage conversion circuit 3 is the power supply voltage (VD
It became clear that it becomes narrower because it is lower than in D).

That is, since the transistor T1 is turned on and a sufficiently high reset voltage is applied to the gate of the transistor T2 during the reset operation period of the signal charge-voltage conversion circuit 3, the on resistance of the transistor T2 is extremely small. The source potential of T2 is almost the power supply voltage VDD.
However, at the end of the reset operation, the transistor T1 is turned off to cut off the reset voltage, so that the charge remaining in the signal charge-voltage conversion circuit 3 is redistributed to the gate capacitance of the transistor T2. As a result, the gate voltage of the output transistor T2 immediately after the end of the reset operation is lowered, and T2
The source potential of the source voltage of the power source drops from the power supply voltage VDD.

Therefore, the source potential of T2 drops from the power supply voltage VDD due to the drop of the gate voltage of the transistor T2, and the offset level intervenes in the optimum black level in the state where there is no signal charge immediately after the end of the reset operation. Like The offset level is shown in the dashed circled diagram in FIG. The dashed circled diagram is the output dynamic range of the circuit. This offset level narrows the output signal dynamic range. The narrowed dynamic range causes problems that it is difficult to drive the solid-state imaging device at a low voltage, and the S / N ratio (signal-to-noise ratio) of the output voltage (imaging signal) is reduced.

The present invention has been devised in view of the problems of the conventional example, and by increasing the gate voltage of the output transistor immediately after the end of the reset operation, the output dynamic range can be widened. An object is to provide a voltage conversion circuit and a solid-state imaging device.

[0012]

A first charge-voltage conversion circuit according to the present invention, as shown in the embodiment thereof in FIG. 1, has a capacitance whose one end is connected to a first power supply line, A first field effect transistor having a source connected to the other end of the capacitance, a drain connected to a reset power supply, and a gate connected to a reset signal source; and a gate connected to the other end of the capacitance. A second field effect transistor having a source connected to the output section and a drain connected to the second power supply line, one end connected to the source of the second field effect transistor, and the other end connected to the first field effect transistor. A load resistance connected to the power supply line, and a switch element that connects the first power supply line connected to one end of the capacitance and the source of the second field effect transistor when the circuit is reset. It is characterized by being

In the first conversion circuit of the present invention, the switch element is configured to generate a second reset signal based on a second reset signal whose timing is shifted from that of the first reset signal input to the gate of the first field effect transistor. The source of the field-effect transistor is connected to the first power supply line. In a second charge-voltage conversion circuit of the present invention, in the first conversion circuit, the switch element serves as a source of the second field effect transistor based on a reset signal input to a gate of the first field effect transistor. It is characterized in that it is connected to the first power supply line.

In the first and second conversion circuits of the present invention, the capacitance is the capacitance generated between the impurity diffusion layer of the first field effect transistor and the substrate, and the gate of the first field effect transistor. The capacitance generated between the sources and the capacitance generated between the gate and the source of the second field effect transistor are used. In the first and second conversion circuits of the present invention, the drain is the second
And a third field effect transistor having a source connected to one end of the load resistor and the output section and a gate connected to an input signal source. To do.

In the solid-state image pickup device of the present invention, a light receiving element that receives light to generate a signal charge, a transfer circuit that sequentially transfers the signal charge generated in the light receiving element, and a signal charge transferred by the transfer circuit. And a signal charge-voltage conversion circuit for outputting a voltage by repeating sweeping out of the signal charge and sweeping out the signal charge, wherein the signal charge-voltage conversion circuit is one of the first and second charge-voltage conversion circuits of the present invention. The above-mentioned object is achieved.

The operation of the first charge-voltage conversion circuit of the present invention at the time of reset will be described. This operation is started when the reset signal source of "H" level is input from the reset signal source to the first field effect transistor and the switch element is turned on. When the reset signal is input to the gate of the first field effect transistor, the first field effect transistor is turned on, so that the reset voltage is applied to the gate of the second field effect transistor and the switch element is turned on. During the reset period, the potential of the first power supply line connected to one end of the capacitance is applied to the source of the second field effect transistor.

Therefore, the gate-source capacitance of the second field effect transistor is charged with a reset voltage close to that charged in the electrostatic capacitance. As a result, even if the first field effect transistor and the switch element are turned off immediately after the end of the reset operation, the gate of the second field effect transistor maintains the same potential as the reset voltage charged in the capacitance. By keeping the gate at the reset potential, the reset operation ends with the source of the transistor kept at the potential of the second power supply line.

As described above, in the first conversion circuit of the present invention,
By connecting the source of the second field effect transistor to the first power supply line during the reset period, the source of the second field effect transistor is connected to the potential close to the potential of the other end of the capacitance, that is, Since it can be forcibly aligned near the potential of the first power supply line, at the end of the reset operation, the charging state of the electrostatic capacitance and the charging state of the gate-source capacitance of the second field effect transistor should be made substantially equal. You can

Therefore, the reset potential charged in the gate-source capacitance of the second field effect transistor is
Immediately after the switch element is turned off, that is, immediately after the reset operation is completed, the source of the second field effect transistor can be held at substantially the potential of the second power supply line. In addition, in the first conversion circuit of the present invention, the second reset signal whose timing is delayed from the first reset signal input to the gate of the first field effect transistor is input to the switch element, thereby performing the reset operation. It is possible to shift the ON periods of the first switch element and the switch element.

Therefore, even after the first field effect transistor is turned off, the source of the second field effect transistor can be held at the potential of the first power supply line, so that the gate / source of the second field effect transistor can be maintained. The reset potential charged in the inter-capacitance can hold the source of the second field effect transistor immediately after the end of the reset operation at substantially the potential of the second power supply line.

In the second conversion circuit of the present invention, the first conversion circuit
Since the switching element connects the source of the second field effect transistor and the first power supply line based on the reset signal input to the gate of the field effect transistor of FIG. You can Since the reset signal source is shared, the circuit scale can be reduced as compared with the first conversion circuit.

Next, the operation of the solid-state image pickup device of the present invention will be described. First, the light receiving element generates a signal charge when receiving light. The signal charge generated in the light receiving element is sequentially transferred to the signal charge-voltage conversion circuit by the transfer circuit. The signal charge-voltage conversion circuit has one of the first and second charge-voltage conversion circuits of the present invention. Then, the signal charge-voltage conversion circuit repeats accumulation of signal charges transferred by the transfer circuit and sweeping of the signal charges. As a result, the signal charge-voltage conversion circuit outputs a voltage (imaging signal) according to the amount of signal charges accumulated.

As described above, in the signal charge-voltage conversion circuit of the solid-state image pickup device of the present invention, the first and second charge-voltage conversion circuits of the present invention are used.
Since any one of the voltage conversion circuits is included, the source potential of the second field effect transistor of the signal charge-voltage conversion circuit immediately after the end of the reset operation is kept at the potential VDD of the power supply line, so that there is no signal charge. It is possible to reduce the offset level generated in the optimum black level of the state.

Therefore, the dynamic range of the output signal can be expanded by the amount of the reduced offset level. By widening the dynamic range, the solid-state imaging device can be driven at a low voltage and the S / N ratio of the imaging signal can be improved.

[0025]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 5 are explanatory views of a solid-state imaging device to which the charge-voltage conversion circuit according to the embodiment of the present invention is applied. (1) First Embodiment FIG. 1 shows a configuration diagram of a solid-state imaging device to which a charge-voltage conversion circuit according to a first embodiment of the present invention is applied.
The solid-state image pickup device is provided with a charge-voltage conversion circuit for each of a plurality of lines, and constitutes an image sensor. In the present embodiment, a case of one line will be described in order to simplify the description.

In FIG. 1, reference numeral 11 denotes a photodiode which receives light and generates signal charges. The photodiode 11 is an example of a light receiving element. Photodiode 11
A reverse bias is applied to. A transfer circuit 12 sequentially transfers the signal charges (normal electrons e) generated in the photodiode 11. Reference numeral 13 denotes a signal charge-voltage conversion circuit that outputs an output voltage (VOUT: imaging signal) by repeating accumulation of signal charges transferred by the transfer circuit 12 and sweeping out of the signal charges. This conversion circuit 13 comprises the first charge-voltage conversion circuit of the present invention.

The signal charge-voltage conversion circuit 13 includes a capacitance C and four n-channel field effect transistors (hereinafter simply referred to as transistors) T11, T21, T31, T41.
And one load resistor RL1. RL1 is commonly provided for each line. The capacitance C has one end connected to the ground line (first power supply line) GND and the other end connected to the source of the reset transistor T11 and the gate of the output transistor T21. The electrostatic capacitance C is the floating diffusion capacitance CFD generated between the n-type impurity diffusion layer (source) of the transistor T11 and the substrate as shown in FIG.
The capacitance CR generated between the gate and source of 11 and the capacitance CD generated between the gate and source of the transistor T21 are used.

The transistor T11 is an example of a first field effect transistor, and has a function of resetting the signal charge-voltage conversion circuit 13 based on the first reset signal (φR). The source of the transistor T11 is connected to the other end of the capacitance C, the drain of T11 is connected to the reset power supply, and the gate of T11 is connected to the first reset signal source. In this embodiment, a reset power supply (not shown) supplies the reset voltage (VDR) to the gate of the transistor T11. The reset power supply charges the electrostatic capacitance C with positive charges. Further, the first reset signal source has a function of generating a signal having a predetermined pulse width,
When the voltage conversion circuit 13 is reset, an “H” (high) level signal is supplied to the gate of T11, and “L” is stored during charge accumulation.
A (low) level signal is supplied to the gate of T11.

The output transistor T21 is an example of the second field effect transistor and constitutes a source follower circuit. The gate of the transistor T21 is connected to the other end of the electrostatic capacitance C, the source of T21 is connected to the output section, and the drain of T21 is connected to the power supply line VDD. The reset assisting transistor T31 is an example of a switch element, and the signal charge-voltage conversion circuit 1 is based on the second reset signal (φA).
3 has a function of connecting the source of the transistor T21 to the ground line GND at the time of resetting. The drain of the transistor T31 is connected to the source of the transistor T21,
Is connected to the ground line GND. Transistor T
The gate of 31 is connected to the second reset signal source. The second reset signal source has a function of generating a signal having a predetermined pulse width, and outputs the second reset signal at a timing delayed by the time Δt from the first reset signal to the gate of the transistor T31. The second reset signal source supplies an “H” (high) level signal to the gate of T31 when the signal charge-voltage conversion circuit 13 is reset, and an “L” (low) level signal of T31 during charge accumulation. Supply to the gate.

The transistor T41 is an example of a third field effect transistor and has a function of enabling (selecting) the output of the circuit 13. The drain of the transistor T41 is connected to the source of the transistor T21.
Is connected to one end of the load resistor RL1 and the output (OUT), and the gate of T21 is connected to an input signal source (not shown). The transistor T41 is provided to connect the source follower circuit of each column to the output line when forming the image sensor. This is because without T41, the source follower circuits connected to the same output line simultaneously function and signal crosstalk occurs. Replace the transistor T41 with the transistor T of the source follower circuit in each column.
Column selection is possible by providing between 21 and the output line.

The load resistor RL1 is provided to take out the output voltage VOUT. One end of the load resistor RL1 is connected to the source of the transistor T21, and the other end of RL1 is connected to the ground line GND. In the image sensor, since the charges are read out line by line, the load resistor RL1 is commonly used for each signal charge-voltage conversion circuit. Next, the reason why the source of the transistor T21 is connected to the ground line GND at the time of resetting the signal charge-voltage conversion circuit 13 will be described with reference to FIGS. 2A and 2B. FIG. 2A shows a cross-sectional view when the transistors T11 and T21 of the signal charge-voltage conversion circuit 13 are formed by a semiconductor device.
In FIG. 2A, CFD is n ⁺ of the transistor T11.
It is a capacitance generated between the impurity diffusion layer and the p-type silicon substrate. CR is a capacitance generated between the gate of the transistor T11 and the p-type silicon substrate. CD is a transistor T
This is the capacitance generated between the gate and source of 21. CR is a capacitance generated between the gate and the source of the transistor T11. VFDx indicates the potential between the ground line GND and the gate of the transistor T21. VFDx becomes the gate potential of the transistor T21. VOUTx represents the output voltage of the source follower circuit. φR indicates a reset signal.

FIG. 2B shows the capacitors CFD, CR, CD, the gate potential VFDx, and the output voltage VOU of the source follower circuit of the signal charge-voltage conversion circuit 13 shown in FIG.
An equivalent circuit diagram including Tx and a reset signal φR is shown. In FIG. 2B, VFDx indicates a gate potential when x is 1 and when x is 2. VFD1
Is the gate potential of T21 when the transistor T11 is on, and VFD2 is the gate potential of T21 when the transistor T11 is off.

Next, assuming that there is no inflow of signal charges from the outside, the charge amounts Q1 and Q2 stored in the total capacitance C of the signal charge-voltage conversion circuit 13 before and after reset will be calculated. First, when the signal charge-voltage conversion circuit 13 is reset, that is, when the amount of charge Q1 stored in the total capacitance C = CFD + CR + CD when the transistor T11 is on is obtained, Q1 is expressed by the equation (1). Be done.

[0034]

[Equation 1]

Next, immediately after the resetting of the signal charge-voltage conversion circuit 13, that is, when the transistor T11 is turned off, the charge amount Q2 stored in the total capacitance C = CFD + CR + CD is calculated, and Q2 is (2). Indicated by the formula.

[0036]

[Equation 2]

However, VRH and VRL are transistor T
These are the "H" level voltage and the "L" level voltage of the reset signal φR applied to the gate of 11. Since there is no inflow of signal charges from the outside, Q1 = Q2 according to the law of conservation of charge. Therefore, the gate potential VDF2 immediately after the reset of the signal charge-voltage conversion circuit 13 is given by the equation (3).

[0038]

(Equation 3)

Next, in the equation (3), the condition for maximizing the VDF2 is obtained. In a miniaturized semiconductor device, the capacitance C that usually becomes dominant is the gate-source capacitance CD of the transistor T21. In the equation (3), VDF2 can be effectively increased by increasing VOUT2-VOUT1 in terms of the capacitance CD, that is, by decreasing VOUT1. If the gate potential VDF2 immediately after the reset of the signal charge-voltage conversion circuit 13 is increased, the output voltage (source potential) VOUT2 of the source follower circuit can be increased and the output dynamic range is expanded.

Next, the operation of the solid-state image pickup device according to the first embodiment of the present invention will be described with reference to FIGS. First, the first reset signal (φR) and the second reset signal (φA) as shown in FIG.
It is input to the voltage conversion circuit 13 and reset. Here, the first reset signal source (not shown) outputs the first reset signal of “H” level to the gate of the transistor T11,
The second reset signal source (not shown) outputs the second reset signal of "H" level delayed by .DELTA.t to the gate of the transistor T31. Then, as shown in FIG. 3B, the transistor T11 is turned on first, and the transistor T31 is turned on after this, so that the reset voltage is applied to the gate of the transistor T21, and after that, the transistor T21 is turned on.
At the time of the reset operation, the potential of the ground line GND, which is lower than the potential of the power supply line VDD (the same potential as the potential at one end of the capacitance C), is applied to the source of the. At this point, the transfer circuit 12 has not transferred the signal charge, and the transistor T
The on resistance RD of 21 is small.

At this time, if the output voltage VOUT is obtained by turning on the transistor T41, VOUT is given by the equation (4).

[0042]

(Equation 4)

Here, RA is the ON resistance value of the transistor T31, RD is the ON resistance value of the transistor T21, RL is the value of the load resistance RL1, and VD is the voltage of the power supply line VDD. Neglecting the on resistance of the transistor T41, RA <RA +
Since it is RL, the output voltage VOUT becomes approximately 0 during the reset period if RA is sufficiently low. Next, when “L” level reset signals φR and φA are output from the first and second reset signal sources (not shown) to the gate of the transistor T11 and the gate of the transistor T31, respectively, in FIG. The transistor T11 turns off, and T31 turns off after this, but the gate-source capacitance CD of the transistor T21 remains charged with the reset voltage (positive charge). As a result, even if the transistors T11 and T31 are turned off, the reset potential is maintained at the gate of the transistor T21 immediately after the completion of the reset operation. Since the reset potential is maintained, the source potential of this transistor can be maintained substantially at the potential VDD of the power supply line.

At this time, the photodiode 11 receives the light and generates a signal charge (negative charge). The signal charges generated in the photodiode 11 are transferred to the transfer circuit 12 to which the transfer clock signal φT as shown in FIG.
Are sequentially transferred to the signal charge-voltage conversion circuit 13. As the signal charge is accumulated in the electrostatic capacitance C, the gate potential becomes lower, so that the on-resistance of the transistor T21 increases. This is because the positive charge due to the reset voltage is neutralized by the negative charge due to the signal charge.

When the output enable signal φC as shown in FIG. 3A is input to the gate of the transistor T41 of the signal charge-voltage conversion circuit 13, the transistor T41 is turned on as shown in FIG. 4B. Turn on. When T41 is turned on, the signal charge-voltage conversion circuit 13 outputs the output voltage (imaging signal) VOUT. VOUT is given by equation (5).

[0046]

(Equation 5)

By repeating the accumulation of the signal charges transferred by the transfer circuit 12 and the sweeping out of the signal charges in this way, the signal charge-voltage conversion circuit 13 causes the image pickup signal of the level corresponding to the accumulated amount of the signal charges. Is output. As described above, in the solid-state image pickup device to which the charge-voltage conversion circuit according to the first embodiment of the present invention is applied, the source of the transistor T21 is connected to the ground line GND by connecting the source of the transistor T21 to the ground line GND during the reset operation. Can be forcibly aligned with the same potential as the other end of the capacitance C, that is, the potential of the ground line GND.
Even if 31 is turned off, the reset voltage of the same potential charged in the electrostatic capacitance C is applied to the gate-source capacitance C of the transistor T21.
Can be charged to D.

Therefore, even if the transistor T31 is turned off immediately after the end of the reset operation, the reset potential charged in the gate-source capacitance CD of the transistor T21 becomes the gate voltage of the transistor T21 immediately after the end of the reset operation. As a result, the source potential of the transistor T21 of the signal charge-voltage conversion circuit 13 immediately after the end of the reset operation is maintained at the potential VDD of the power supply line, so that the optimum black level in the state in which there is no signal charge is set as in the conventional example. Such an offset level is not present. As a result, the black level voltage at the time of signal reading becomes high, and the output signal dynamic range can be widened due to the absence of the offset level. By widening the dynamic range, the solid-state imaging device can be driven at a low voltage and the S / N ratio of the imaging signal can be improved.

When the transistor T11 is on, the transistor T41 is off and the signal is not read out. Therefore, the output of the source follower circuit is connected to the ground line G.
Connecting to ND does not affect the output line. Further, when the transistor T31 is turned on at the time of reset, a through current momentarily flows through the power supply line VDD → T21 → T31 → ground line GND. As a countermeasure against this, current consumption can be suppressed by adjusting the on-resistance of the transistor T21.

(2) Description of Second Embodiment FIG. 5 is a block diagram of a solid-state image pickup device to which a charge-voltage conversion circuit according to a second embodiment of the present invention is applied.
In the second embodiment, unlike the first embodiment, a reset signal φR having the same timing as the reset signal φA input to the gate of the transistor T12 is input to the gate of the transistor T32.

In FIG. 5A, the second solid-state image pickup device includes a photodiode 21, a transfer circuit 22, and a signal charge-voltage conversion circuit 23. The signal charge-voltage conversion circuit 23 includes an electrostatic capacitance C, a reset transistor T12, and a transistor T2 forming a source follower circuit.
2. A transistor T32 for assisting the reset operation, a transistor T42 for controlling the output of the circuit, and a load resistor RL2. The transistor T32 is an example of a switch element. Unlike the first embodiment, in the second embodiment, the gate of the transistor T12 and the gate of the transistor T32 are connected. The gates of T12 and T32 are connected to a reset signal source (not shown). Other connection methods of the transistors T12, T22, T32 and T42,
Since the capacitance C is the same as that in the first embodiment, its description is omitted.

Next, the operation of the second solid-state image pickup device will be described with reference to FIG. First, a reset signal (φR = φA) as shown in FIG. 5B is input to reset the signal charge-voltage conversion circuit 23. Here, an "H" level reset signal is input to the gates of the transistors T12 and T32 from a reset signal source (not shown). Then, since the transistors T12 and T32 are turned on at the same time, the reset voltage (VDR) is applied to the gate of the transistor T22, and at the same time, the source of the transistor T22 is connected to the power line V.
A potential of the ground line GND (same potential as one end of the electrostatic capacitance C) lower than the potential of DD is applied.

Next, an "L" level reset signal is input to the gates of the transistors T12 and T32 from a reset signal source (not shown). Then, the transistors T12 and T32 are turned off at the same time, but the gate-source capacitance CD of the transistor T22 remains charged with the reset voltage (positive charge). As a result, even if the transistors T12 and T32 are turned off at the same time, the transistor T immediately after the reset operation is finished.
The reset potential is maintained at the gate of 22. Since the reset potential is maintained, the source potential of this transistor is almost equal to the potential VD of the power supply line as in the first embodiment.
Can be kept at D.

The signal charge generated in the photodiode 21 is transferred to the transfer circuit 2 based on the transfer clock signal φT.
2, the signals are sequentially transferred to the signal charge-voltage conversion circuit 23. As the signal charge is stored in the electrostatic capacitance C, the on resistance of the transistor T22 increases. Then, when the output enable signal φC as shown in FIG. 5B is input to the gate of the transistor T42 of the signal charge-voltage conversion circuit 23, T42 is turned on. When T42 is turned on, the signal charge-voltage conversion circuit 23 outputs the output voltage (imaging signal) VOUT.
Is output. VOUT is as shown in the equation (5). By repeating the accumulation of the signal charges and the sweeping out of the signal charges in this manner, the signal charge-voltage conversion circuit 23 outputs an image pickup signal according to the accumulated amount of the signal charges.

As described above, in the solid-state image pickup device to which the charge-voltage conversion circuit according to the second embodiment of the present invention is applied, the reset signal φR = φA input to the gate of the transistor T12 is input to the gate of the transistor T32. Therefore, the number of reset signal sources can be one. Since the transistors T12 and T32 can share the reset signal source, the circuit scale can be reduced as compared with the first embodiment.

In addition, as in the first embodiment, the transistor T32 changes to T12 based on the reset signal φR = φA.
Since the potential of the ground line GND is supplied to the source of the transistor T22 at the same time as the reset voltage is supplied, the gate of T22 immediately after the completion of the reset operation can be maintained at the potential of the power supply line VDD. In each of the embodiments of the present invention, the method of forming the circuit by the n-channel field effect transistor has been described, but the same effect can be obtained when the circuit is formed by the p-channel field effect transistor. Further, the charge-voltage conversion circuit can be applied not only to the solid-state image pickup device but also to an integration circuit.

[0057]

As described above, in the charge-voltage conversion circuit of the present invention, the source of the second field effect transistor is connected to the first power supply line by the switch element during the resetting operation. Since the source of the transistor is forcibly aligned with the same potential as the other end of the capacitance, the reset voltage of the same potential charged in the capacitance is used as the gate-source capacitance of the second field effect transistor. Can be charged. As a result, the reset potential charged in the gate-source capacitance holds the source of the second field effect transistor immediately after the end of the reset operation at the potential of the second power supply line.

Further, the signal charge of the solid-state image pickup device of the present invention-
Since the voltage conversion circuit has the charge-voltage conversion circuit of the present invention, the source potential of the second field-effect transistor of the signal charge-voltage conversion circuit immediately after the end of the reset operation becomes the potential of the second power supply line. Will be kept. Therefore,
Since the offset level does not intervene in the optimum black level when there is no signal charge, the output signal dynamic range can be expanded.

This greatly contributes to lowering the voltage of the solid-state image pickup device and improving the S / N ratio of the image pickup signal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a solid-state imaging device to which a charge-voltage conversion circuit according to a first embodiment of the present invention is applied.

FIG. 2 is a capacitance according to each embodiment of the present invention and an equivalent circuit diagram related thereto.

FIG. 3 is an operation explanatory diagram (1) of the solid-state imaging device according to each embodiment of the present invention.

FIG. 4 is an operation explanatory view (No. 2) of the solid-state imaging device according to each embodiment of the present invention.

FIG. 5 is a configuration diagram of a solid-state imaging device according to a second embodiment of the present invention and an operation waveform diagram thereof.

FIG. 6 is a configuration diagram of a solid-state imaging device according to a conventional example and an operation waveform diagram thereof.

[Explanation of symbols]

1, 11, 21 ... Photodiode, 2, 12, 22 ...
Transfer circuit, 3, 13, 23 ... Charge-voltage conversion circuit, T
1, T2, T3, T11, T21, T31, T41, T12, T2
2, T32, T42 ... N-channel field effect transistor, RL, RL1, RL2 ... Load resistance, C ... Capacitance.

Claims (6)

[Claims] 1. A capacitance having one end connected to a first power supply line, a source connected to the other end of the capacitance, a drain connected to a reset power supply, and a gate connected to a reset signal source. And a second field effect transistor having a gate connected to the other end of the capacitance, a source connected to an output section, and a drain connected to a second power supply line, A load resistance having one end connected to the source of the second field effect transistor and the other end connected to the first power supply line, and a first power supply line connected to one end of the capacitance when the circuit is reset. And a switch element that connects the source of the second field effect transistor to the source of the second field effect transistor. 2. The switching element, based on a second reset signal whose timing is shifted from that of the first reset signal input to the gate of the first field effect transistor, is connected to the source and the second field effect transistor of the second field effect transistor. The charge-voltage conversion circuit according to claim 1, wherein the charge-voltage conversion circuit is connected to one power supply line. 3. The switch element connects the source of the second field effect transistor and the first power supply line based on a reset signal input to the gate of the first field effect transistor. Item 2. The charge-voltage conversion circuit according to item 1. 4. The capacitance is a capacitance generated between an impurity diffusion layer of the first field effect transistor and a substrate, a capacitance generated between a gate and a source of the first field effect transistor, and the second capacitance. 2. The charge-voltage conversion circuit according to claim 1, wherein the capacitance generated between the gate and the source of the field effect transistor is used. 5. A third electric field having a drain connected to a source of the second field effect transistor, a source connected to one end of the load resistor and the output section, and a gate connected to an input signal source. The charge-voltage conversion circuit according to claim 1, further comprising an effect transistor. 6. A light-receiving element that receives light to generate a signal charge, a transfer circuit that sequentially transfers the signal charge generated by the light-receiving element, accumulation of the signal charge transferred by the transfer circuit, and the signal charge And a signal charge-voltage conversion circuit that outputs a voltage by repeating extraction of the voltage, the signal charge-voltage conversion circuit according to any one of claims 1, 2, 3, and 4. A solid-state imaging device having a voltage conversion circuit.