JPH09181593A - Digital output stage circuit - Google Patents

Abstract

(57) [PROBLEMS] To provide a digital output stage circuit capable of reducing the number of pins of an LSI and significantly reducing the cost for preventing spurious of the LSI. A first synchronizing circuit 101 provided corresponding to each of a plurality of bit data and synchronizing these bit data with a system clock CP, and a system clock C.
A PLL circuit 51 which receives P and is composed of a plurality of voltage control delay stages, and a second output which synchronizes each output of the first synchronizing circuit 101 with each output of each delay stage of the PLL circuit 51 as a predetermined clock. The present invention is characterized by including a synchronizing circuit 102 and a drive circuit 61 for driving the output signals of the synchronizing circuit 102 which are out of phase with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is particularly applicable to digital L
The present invention relates to a digital output stage circuit that prevents simultaneous switching of SI output stages.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a configuration of a digital output stage circuit which has been conventionally applied. D1, D2 in the figure ...
D8 indicates an 8-bit data signal to be output,
For example, an 8-bit color signal output signal in the video signal processing LSI is shown. The data signal D1 is input to a D-type flip-flop (abbreviated as D-FF) 111. CP indicates a system clock, which is, for example, a clock of 14.3 MHz. The signal obtained at the output Q in synchronization with the rise of the system clock CP is the output buffer (OB).
Guided by 121. The output buffer 121 is connected to the output pad 131 of the LSI and drives the capacitive load C1. Similarly, the data signals D2 to D8 are also synchronized by the D-FFs 112 to 118, guided to the respective output buffers 122 to 128, and configured to drive the loads C2 to C8 via the pads 132 to 138, respectively. ing.

As is well known, in the conventional circuit shown in FIG. 4, the loads C1 to C8 are driven in synchronization with the system clock CP, so that sudden inflow and outflow of charges are caused in the buffers 21 to 28 at the same time. Happens through. The inflow and outflow currents at the time of simultaneous switching in this output stage circuit cause various problems as described below.

First, there is a problem of malfunction due to switching noise inside the LSI. Regarding this internal malfunction, the malfunction is improved by, for example, providing one ground terminal and one power supply terminal for each of the eight output lines of the output circuit. As a result, LSI with many output circuits
In contrast, many ground terminals and power terminals are required.
Considering a low-cost LSI, the increase in the number of pins (the number of terminals) is an improvement item.

Further, the simultaneous switching current causes spurious interference, which is a main cause of electromagnetic interference. As a result, when these LSIs are used in equipment, a large number of external parts such as inductances and capacitors are required as a countermeasure against spurious. As you can see again,
It is necessary to take measures such as shielding a substrate using these LSIs with a shield material. As a result, the cost is considerably increased, which is an obstacle to the demand for cost reduction of consumer appliances.

[0006]

As described above, conventionally,
Simultaneous switching currents are generated in the output stage of the digital LSI, and the current situation is that this problem leads to an increase in cost, such as measures against malfunctions and spurious interference.

The present invention has been made in view of the above circumstances. An object of the present invention is to provide a digital output stage circuit that greatly improves the conventional problems caused by simultaneous switching by a simple and inexpensive means. To provide.

[0008]

A digital output stage circuit of the present invention is provided for each of a plurality of bit data, and a first synchronizing circuit for synchronizing these bit data with a system clock signal; A PLL circuit which receives a system clock signal and is composed of at least a plurality of voltage control delay stages, and outputs of each of the plurality of voltage control delay stages of the PLL circuit are each used as a predetermined clock to output each output of the first synchronization circuit. A second synchronizing circuit for synchronizing;
A drive circuit for driving each output signal of the second synchronizing circuit.

In the present invention, the data to be output is
After synchronizing with the system clock, a plurality of predetermined clocks having different timings, which are created by a PLL (phase-locked loop) circuit to which the system clock is input, synchronize with each other to prevent simultaneous switching of the drive circuits.

[0010]

1 is a circuit diagram showing a configuration of a digital output stage circuit according to an embodiment of the present invention. To simplify the explanation, the data signals to be output are D1 and D2.
, ... The output stage circuit will be described assuming that D4 is 4 bits. Date
D-type flip-flop (D-
11 to 14 are provided. The D-FFs 11 to 14 respectively input the data signals D1 to D4 (D input) and the system clock CP, and synchronize each Q output with the system clock CP. These D-FF 11
˜14 form a first synchronizing circuit 101. The system clock CP is also input to the PLL circuit 51 that controls the timing of data output in the next stage of the D-FFs 11-14.

The Q outputs of the D-FFs 11 to 14 are respectively D
-It is led to the D input of FF 21-24. D-FF 21 ~ 24
Is a clock pulse P5 commonly generated by the PLL circuit 51.
Is supplied. For example, the Q output corresponding to the data is obtained from each of the D-FFs 21 to 24 in synchronization with the rising of the clock pulse P5.

D-FF 2 synchronized with clock pulse P5
The Q outputs of 1 to 24 are introduced to the D inputs of D-FFs 31 to 34, respectively. A clock pulse P1 having the same phase as the system clock CP is supplied to the D-FF 31. D-FF
A clock pulse P2 delayed in phase from the clock pulse P1 is supplied as the 32 clock. As a clock of the D-FF 33, a clock pulse P3 whose phase is delayed from the clock pulse P2 is supplied. As a clock of the D-FF 34, a clock pulse P4 whose phase is delayed from the clock pulse P3 is supplied. The clock pulse P5 has a phase delayed from that of the clock pulse P4 and is set to have a phase opposite to that of the clock pulse P1. PLL
These D-FFs 21 to 24 and D- whose output is controlled by the circuit 51
The FFs 31 to 34 form the second synchronization circuit 102.

The Q outputs of the D-FFs 31-34 synchronized with the clock pulses having different phases are guided to the output buffers (OB) 61-64, respectively, and the output pads 65-
Drive capacitive loads C1 through C4 via 68.

According to the above configuration, the data signal is once synchronized with the clock pulse P5 generated by the PLL circuit 51, and then P1 and P1 having a phase difference according to each data in the rising phase cycle of the clock pulse P5, P2, P3,
Since it is synchronized with the clock pulse of P4, it is possible to generate output data with a time difference without being affected by the duty of the system clock CP.

FIG. 2 is a circuit diagram showing the configuration of the PLL circuit 51 shown in FIG. 1, and FIG. 3 is a timing chart showing the operation of the circuit of FIG. In FIG. 3, eight delay circuits DLY capable of controlling the delay amount Δτ by the control signal CNT are connected in series to form a delay stage. Each delay circuit DL
In Y, the input I is connected to the inverter 81 whose delay amount is variable by the control signal CNT, and the output of the inverter 81 whose delay amount is controlled according to CNT is the waveform shaping inverter.
The waveform is shaped by the switch 82 and connected to the output O.

The PLL circuit 51 starts with the clock pulse P1 having the same phase as the system clock CP and the delay circuit DL.
Each time Y passes, clock pulses P2, P3, P4, ... Are taken out, and the output of the last eighth delay circuit DLY is the output node of the clock pulse P9 (in phase with CP). P
The total delay value of the delay stages of the LL circuit 51 is configured to have at least ½ or more of the cycle of the system clock CP.

The logic circuit 70 inputs the clock pulse P1 and the inverted signal of the clock pulse P3 via the inverter 701, the AND gate 702, the clock pulse P3 and the inverted signal of the clock pulse P5 via the inverter 703. AND gate 704, AND gates 702, 704
It is composed of an OR gate 705 which inputs both outputs.

This logic circuit 70 has (P1). (/ P3) +
The logical configuration is (P3) / (/ P5) (/ P3
And / at the head of P5 represents the inversion of the signal). Logic circuit 70
Output S is connected to the buffer circuit 71. The output of the buffer circuit 71 is integrated by a low-pass filter (abbreviated as LPF) including a resistor 72 and a capacitor 73, and the DC component becomes a control signal CNT that controls the delay amount. With this PLL configuration, the control system operates so that the duty ratio of the output S of the logic circuit becomes 1: 1.

As shown in FIG. 3, the clock pulse P1 shows the same signal as the system clock CP, and the clock pulses P2, P3, P4 ... P9 are waveforms each having a delay amount of Δτ as shown in the figure. The rising phase of each of the clock pulses P2, P3 and P4 exists between the rising phase of the system clock CP and the rising phase of the clock pulse P5. Such a PLL configuration can be applied to a clock system having any duty ratio, and its application range is extremely wide.

According to the present invention, with the output stage circuit configuration of the digital circuit of the present invention, the ground (or power supply) by the simultaneous switching of the output circuits, which has been a problem in the past, has been proposed.
The problem that the number of pins of the LSI increases due to the addition of terminals is solved. When four sets of 8-bit data outputs exist in the related art by adopting a configuration in which at least simultaneous switching does not occur in each set of data, four ground terminals and power supply terminals are required respectively. By applying the above, only one or two ground terminals and power terminals are required.
Therefore, the number of pins of the LSI can be saved from 4 to 6.

Further, it is apparent that the conventional problem of spurious due to simultaneous switching can be greatly improved by giving a logical time difference to the switching time. Further, the scale of the logic circuit added by the present invention is not large and does not become an obstacle in practical use.

As a result, a large number of external parts required for spurious countermeasures in the device using these LSIs are reduced, and the cost of the device can be sufficiently reduced. Considering recent LSIs that tend to be low in voltage, it is very advantageous in terms of design to eliminate external parts for spurious countermeasures, although it depends on conditions such as the LSI layout on the board of the system.

[0023]

As described above, by arranging the digital output stage by using the PLL circuit so that simultaneous switching does not occur, external components for spurious countermeasures, an increase in the number of pins are eliminated, and integration and cost reduction are achieved. Done LS
A digital output stage circuit capable of realizing I can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a digital output stage circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a PLL circuit 51 shown in FIG.

FIG. 3 is a timing chart showing the operation of the circuit of FIG.

FIG. 4 is a diagram showing a configuration of an output stage circuit of a conventional digital circuit.

[Explanation of symbols]

11-14, 21-24, 31-34 ... D-type flip-flop (D
-FF), 51 ... PLL circuit, 61-64 ... Output buffer, 65
~ 68 ... Output pad, C1 ~ C4 ... Capacitive load.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03K 19/00 101N 101R

Claims (3)

[Claims] 1. A first synchronizing circuit which is provided for each of a plurality of bit data and synchronizes the bit data with a system clock signal, and at least a plurality of voltage control delay stages receiving the system clock signal. And a second synchronization circuit that synchronizes the outputs of the first synchronization circuit with the outputs of the plurality of voltage control delay stages of the PLL circuit as predetermined clocks, respectively. 2. A digital output stage circuit comprising: a drive circuit for driving each output signal of the synchronization circuit of 2. 2. A third synchronizing circuit, wherein the second synchronizing circuit synchronizes an output signal of the first synchronizing circuit with one of predetermined clocks of the PLL circuit, and a third synchronizing circuit. 3. The digital output stage circuit according to claim 1, further comprising a fourth synchronizing circuit for synchronizing each output signal of the synchronizing circuit of No. 3 with a predetermined clock of the corresponding PLL circuit. 3. The digital output stage circuit according to claim 1, wherein the total delay value of the voltage controlled delay stage of the PLL circuit is at least ½ or more of the cycle of the system clock.