JPH09181982A - Solid-state imaging device - Google Patents

Abstract

(57) Abstract: Threshold voltage Vth of horizontal switch transistor
The vertical streak-shaped fixed pattern noise was generated due to the variation of the. SOLUTION: Each of vertical signal lines 13 from which a signal is read out from a pixel transistor 11 is connected to each of load capacitors 16 (..., 16n, 16n + 1, ...) via operation switch transistors 15 (..., 15n, 15n + 1, ...). One end is connected and the load capacitor 16 (..., 16
n, 16n + 1, ...) Between the other end and the output end of the output circuit 21, horizontal scanning pulses (..., φHn, φHn + 1,
, And horizontal switch transistors 17 (..., 17n, 17n + 1, ...) Which are turned on in sequence are connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device having a structure in which signals generated in a plurality of pixel portions are temporarily held in a capacitor and then output to the outside through an output circuit.

[0002]

2. Description of the Related Art FIG. 5 shows the configuration of a conventional amplification type solid-state image pickup device. In FIG. 5, a plurality of pixel transistors 11 having a MOS structure are arranged two-dimensionally.
In the drawing, pixel transistors of m rows and n columns (P
m, n). In these pixel transistors 11, each gate electrode is connected to the vertical selection line 12 in row units, and each source electrode is connected to the vertical signal line 13 in column units. A power supply voltage VD is supplied to each drain electrode. A vertical scanning pulse φV (..., φVm, φVm) from the vertical scanner 14 for sequentially reading pixel information for each line while performing vertical scanning is applied to the vertical selection line 11.
+1, ...) is applied.

On the other hand, one end of the vertical signal line 13 is an NchMOS transistor (hereinafter referred to as an operation switch transistor) which is an operation switch arranged in each vertical column.
15 (..., 15n, 15n + 1, ...) Drain electrodes are connected. The source electrode of the operation switch transistor 15 has a load capacitor 16 (..., 16n, 16n).
are grounded via n + 1, ..., And an operation pulse φOP is applied to the gate electrode thereof. Further, the source electrode of the operation switch transistor 15 is an NchMOS transistor (hereinafter, referred to as a horizontal switch transistor) 17 (..., 17n, 17n + 1, which is a horizontal switch).
…) Is connected. Each source electrode of these horizontal switch transistors 17 is connected to a horizontal signal line 18, and its gate electrode is connected to a horizontal selection line 19.

The horizontal selection line 19 is connected to the horizontal scanner 20. An output circuit 21 is provided at one end of the horizontal signal line 18.
Are connected. The output circuit 21 includes a differential amplifier 22 having an inverting (-) input terminal connected to one end of the horizontal signal line 18 and a predetermined reference voltage VB applied to a non-inverting (+) input terminal, and the differential amplifier 22. Of the NchMOS transistor (hereinafter, referred to as reset switch transistor) 23, which is a reset switch connected between the inverting input terminal and the output terminal of the reset pulse φR and applied to the gate electrode in parallel with the reset switch transistor 23. The integrating circuit is composed of the connected capacitor 24, and the output terminal of the differential amplifier 22 is connected to the circuit output terminal 25.

In the amplification type solid-state image pickup device having the above structure, the signal of the pixel transistor 11 for one line is supplied to the load capacitors 16 (..., 16n, ...) During the horizontal blanking period.
16n + 1, ...) is sampled and held, and the signal is read during the horizontal effective period. That is, in the horizontal blanking period, the signal of the pixel transistor 11 for one line is changed to the operation switch transistor 15
It is temporarily stored in the load capacitors 16 (..., 16n, 16n + 1, ...) For each column via (..., 15n, 15n + 1, ...).

In the subsequent horizontal effective period, the electric charge accumulated in each load capacitor 16 (..., 16n, 16n + 1, ...) Is output from the horizontal scanner 20 as a horizontal scanning pulse (..., φHn, φHn + 1, ...). Each horizontal switch transistor 17 (..., 17n, 17n +
1, ...) are sequentially turned on to flow into the output circuit 21 through the horizontal signal line 18, are converted into a voltage, and are output from the circuit output terminal 25. Then, in order to read the signal for the next one line, in the output circuit 21, the reset switch transistor 23 responds to the reset pulse φR.
Is turned on to reset the horizontal signal line 18. And
Each horizontal switch transistor 17 (..., 17n, 17n
Each time (+1, ...) Is sequentially turned on, the above-described operation is repeated to read the signals of all pixels.

[0007]

However, in the above-described conventional amplification type solid-state image pickup device, the horizontal switching element is an MO that has little interference between the control system of the switch and the channel.
Although the S transistor is used, when the MOS transistor is used, the following problems occur. That is, since there is always a variation in the threshold voltage Vth in the MOS transistor, when the signal is read, for example, n
Since the threshold voltages Vth of the nth horizontal switch transistor 17n and the n + 1th horizontal switch transistor 17n + 1 are different from each other, even if the nth load capacitor 16n and the n + 1th load capacitor 16n +
Even if the signals stored in 1 and 1 are the same, the amount of inversion charges formed under the channel varies.

As a result, the electric charge flowing into the capacitor 24 of the output circuit 21 via the horizontal signal line 18 varies.
In this way, the horizontal switch transistors 17 (..., 17)
(n, 17n + 1, ...) Is turned on, the electric charge flowing into the capacitor 24 of the output circuit 21 fluctuates due to the variation in the threshold voltage Vth of each transistor, and therefore is output via the horizontal signal line 18. The signal voltage output to the circuit 21 is slightly different for each vertical column. Therefore, the output voltage Vout of the output circuit 21 is
The potential changes in each vertical column, and the level varies.

As a result, in the external signal processing circuit (not shown), the sampling timings (t1, t2, t3, t4) of the cycle of the sampling pulse are obtained.
...) is used to sample the output voltage Vout at that time,
And the output voltage Vo at the timing t1 and the timing t2
ut, the difference between the output voltage Vout at the timing t3 and the timing t4, ... Are sequentially output as a video signal, the horizontal switch transistors 17 (..., 17n, 17n + 1, ...) On the monitor screen. There is a problem that vertical stripe-shaped fixed pattern noise is generated due to the variation in each threshold voltage Vth.

The present invention has been made in view of the above problems, and an object of the present invention is to eliminate vertical stripe-shaped fixed pattern noise due to the threshold voltage Vth of a horizontal switch transistor being different for each transistor. It is to provide a solid-state imaging device capable of suppressing the occurrence.

[0011]

A solid-state image pickup device according to the present invention comprises a plurality of pixel portions, and a plurality of capacitors each having one end connected to each signal line from which a signal is read out from the plurality of pixel portions. An output circuit that receives a signal supplied from each of the plurality of capacitors via the signal line and outputs the received signal to the outside, and is connected between each of the other ends of the plurality of capacitors and an output end of the output circuit. It is configured to include a plurality of switch elements that are sequentially turned on in response to a scan pulse.

In the solid-state image pickup device having the above configuration, when a plurality of switch elements are in the off state during the horizontal blanking period, signals of the pixel portion for one line are read out, and a plurality of signals are read out via the respective signal lines. The capacitor is sampled and held. In the subsequent horizontal effective period, the plurality of switch elements are sequentially turned on in response to the scan pulse, so that the charges stored in the plurality of capacitors are read out.
At this time, the plurality of capacitors are connected in parallel to the output circuit via the plurality of switch elements that are sequentially turned on. As a result, the sample-hold capacitor acts as a detection capacitor for the output circuit when reading out the charges.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of the present invention applied to, for example, an amplification type solid-state imaging device, and in the figure, the same parts as those in FIG. 5 are designated by the same reference numerals. In FIG. 1, a plurality of pixel transistors 11 having a MOS structure are two-dimensionally arranged, each gate electrode of these pixel transistors 11 is connected to a vertical selection line 12 in a row unit, and each source electrode is in a vertical signal in a column unit. The power supply voltage VD is supplied to each drain electrode, which is connected to the line 13.

A vertical scanning pulse φV (..., φVm, φVm +) is supplied to the vertical selection line 11 from a vertical scanner 14 for sequentially reading pixel information for each line while performing vertical scanning.
1, ...) are sequentially applied. On the other hand, one end of the vertical signal line 13 is connected to the drain electrodes of the operation switch transistors 15 (..., 15n, 15n + 1, ...) Arranged in each vertical column. The configuration so far is the same as the configuration of the conventional amplification type solid-state imaging device shown in FIG.

Operation switch transistor 15 (..., 15)
Each source electrode of n, 15n + 1, ... Is connected to one end of each of the load capacitors 16 (..., 16n, 16n + 1, ...), and the operation pulse φOP is applied to its gate electrode. Load capacitor 16 (..., 16n, 16n +
The other ends of (1, ...) Are connected to the horizontal signal line 18. In addition, the load capacitors 16 (..., 16n, 16n +
1, ...) Between one end and the output end of the output circuit 21,
Horizontal switch transistor 17 (..., 17n, 17n +
1, ...) are respectively connected. Then, the horizontal switch transistors 17 (..., 17n, 17n + 1, ...)
Each gate electrode of is connected to the horizontal selection line 19.

The horizontal selection line 19 is connected to the horizontal scanner 20. An output circuit 21 is provided at one end of the horizontal signal line 18.
Are connected. The output circuit 21 includes a differential amplifier 22 having an inverting (-) input terminal connected to one end of the horizontal signal line 18 and a predetermined reference voltage VB applied to a non-inverting (+) input terminal, and the differential amplifier 22. Has a circuit configuration including a reset switch transistor 23 connected between an inverting input terminal and an output terminal of the differential switch 22 and having a gate electrode to which a reset pulse φR is applied. The output terminal of the differential amplifier 22 is a circuit output terminal. 25 is connected.

Next, the circuit operation of the above configuration will be described with reference to the equivalent circuits of FIGS. 2 and 3 corresponding to each operation.

First, in the horizontal blanking period, as shown in FIG. 2A, the reset switch transistor 23 of the output circuit 21 is turned on (closed), and the horizontal switch transistors 17 (..., 17n, 17n + 1, ...) Are turned off. Operation switch transistor 15 (..., 1 in the open state)
5n, 15n + 1, ...) is turned on, the signal of the pixel transistor 11 for one line is passed through the operation switch transistors 15 (..., 15n, 15n + 1, ...) And the load capacitors 16 (..., 16n, ...) For each column. 16n + 1,
...) is sample-held.

Then, as shown in FIG. 2B, the reset switch transistor 23 and the operation switch transistor 15 (..., 15n, 15n + 1,
...) is turned off, the sample hold ends.
At this time, considering the noise generated by switching,
It is better to turn off the operation switch transistor 15 first, and then turn off the reset switch transistor 23. Otherwise, the potential of the input side wiring of the output circuit 21, that is, the horizontal signal line 18 is not stable, so that the reset operation in the output circuit 21 described later cannot be performed.

During the subsequent horizontal effective period, FIG.
As shown in (A), the horizontal scanning pulses (..., .phi.Hn, .phi.Hn + 1, ...) That are sequentially output from the horizontal scanner 20 cause the respective horizontal switch transistors 17 (..., 17n ,.
By sequentially turning on 17n + 1, ..., The charge accumulated in each load capacitor 16 (..., 16n, 16n + 1, ...) Is read. At this time, the load capacitors 16 (..., 16n, 16n + 1, ...) In turn, the horizontal switch transistors 17 (..., 17n, ...) Between the inverting input terminal and the output terminal of the differential amplifier 22 in the output circuit 21.
17n + 1, ...), and thus constitutes an integrating circuit together with the differential amplifier 22.

All load capacitors 16 (..., 16n,
16n + 1, ...
As shown in (B), the reset switch transistor 23 in the output circuit 21 is turned on to reset the wiring on the input side of the output circuit 21, that is, the horizontal signal line 18. When the reset is completed, the reset switch transistor 23
Turn off. This read operation and reset operation
Each horizontal switch transistor 17 (..., 17n, 17n
The information of all pixels is read out by repeating the above for +1, ...

As described above, for example, in the amplification type solid-state image pickup device, the load capacitor is connected to each of the vertical signal lines 13 from which the signal is read out from the pixel transistor 11 via the operation switch transistors 15 (..., 15n, 15n + 1, ...). 16 (..., 16n, 16n + 1, ...) Are connected to one end of each of the load capacitors 16 (..., 16).
The horizontal switch transistors 17 (..., 17n, ...) Between the other ends of the n, 16n + 1, ...
17n + 1, ...) are connected, so that V
Horizontal switch transistor 17 with th variation
Since (..., 17n, 17n + 1, ...) Is not directly connected to the input side of the output circuit 21, that is, the horizontal signal line 18,
It is possible to obtain the output voltage Vout that is not affected by the potential fluctuation due to the Vth variation.

The load capacitors 16 (..., 16n,
When the charge is read from 16n + 1, ..., The load switch capacitors 16 (..., 16n, 16n + 1 ,.
17n + 1, ...) Via the differential amplifier 2 of the output circuit 21
2 is connected in parallel with the differential amplifier 22 and constitutes an integrating circuit together with the differential amplifier 22, and thus acts as a detection capacitor of the output circuit 21. As a result, the original detection capacitor (capacitor 24 in FIG. 5) of the output circuit 21 is not needed, so that the circuit configuration of the output circuit 21 can be simplified.

In the read operation of FIG. 3B, the horizontal switch transistor 17n is turned off after the charge held in the nth load capacitor 16n has been read, for example. It may be performed before 17n + 1 is turned on.
However, considering that the horizontal switch transistor 17 has switching noise, it is preferable to turn off the horizontal switch transistor 17n before turning off the reset switch transistor 23 during the reset operation.

Now, as shown in FIG. 4, the read operation of the charges held in the load capacitor 16 will be described.
Analysis will be performed by taking the case where the number of load capacitors 16 for sample and hold is two as an example. This is considered to be a result of replacing the unread capacitor with a single equivalent circuit in a circuit having a plurality of capacitors. Hereinafter, the circuit will be analyzed in consideration of the parasitic capacitance.

In FIG. 4, Csh1, Csh2
Is the capacitor capacity for sample and hold, CP1, CP
2 is the parasitic capacitance of each sample and hold capacitor, CB is the parasitic capacitance of the wiring of the horizontal signal line 18, Vs
Is the initial potential of the horizontal signal line 18, ΔVs is the potential change of the horizontal signal line 18 after reading, and Vout is the differential amplifier 2
2 is the initial output voltage, ΔVout is the potential change of the output of the differential amplifier 22 after reading, V1 and V2 are the potentials held in the capacitors for sample and hold, and G
Is the gain of the differential amplifier 22, Qsh1, Qsh2, QP
1, QP2, QB are capacitor capacitances Csh1, Csh
2. Charges accumulated in the parasitic capacitances CP1, CP2, CB.

First, the relationship between the potential change ΔVout of the output of the differential amplifier 22 after reading and the voltage applied to the sample-hold capacitor Csh1 is shown.
In the circuit of FIG. 4, the following equation is established.

[Equation 1]

[Equation 2]

(Equation 3)

Calculating using these equations, the potential change ΔVout of the output of the differential amplifier 22 after reading is
It becomes like the following formula.

(Equation 4)

Next, the necessity of the reset operation in the output circuit 21 will be described. After the read operation, the voltage applied to the sample-hold capacitor Csh1 is

(Equation 5) It is.

Since the gain G of the differential amplifier 22 is finite, the voltage applied to the sample-hold capacitor capacitance Csh1 after the horizontal switch transistor 17 is turned off changes as compared with the initial state. That is,
When the read operation is performed, the potential of the wiring of the input to the differential amplifier 22, that is, the potential of the horizontal signal line 18 is changed.
ut will be different from the original value. Therefore, in order to read the signal of the next vertical column, the differential amplifier 2
It is necessary to reset the input potential of 2 and return to the initial state.

In the above embodiment, in the output circuit 21, the reset switch transistor 23 is connected between the inverting input terminal and the output terminal of the differential amplifier 22, but the connecting position is limited to this. However, the inverting input terminal of the differential amplifier 22 and another power source, for example, V
The configuration may be such that it is connected to the B power supply, and the point is that it is possible to stabilize the potential on the input side wiring of the differential amplifier 22, that is, the horizontal signal line 18 by the reset operation.

Further, in the above-described embodiment, the case where the present invention is applied to the amplification type solid-state image pickup device has been described. However, the present invention is not limited to this, and after the signals generated in a plurality of pixel portions are temporarily held in the capacitors. The present invention can be applied to all solid-state imaging devices configured to output to the outside via an output circuit.

[0033]

As described above, according to the present invention,
One end of each of the plurality of capacitors is connected to each signal line from which the signals are read out from the plurality of pixel portions, and the other end of each of the plurality of capacitors is connected to the output end of the output circuit in response to the scanning pulse. By connecting a plurality of switching elements that are in the ON state one after another, and not including a switching element with a variation in threshold voltage on the input side of the output circuit, an output that is not affected by potential variation due to the variation is output. Since the voltage can be obtained, it is possible to suppress the generation of vertical streak-shaped fixed pattern noise due to the threshold voltage of the switch element being different for each switch element.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram (1) for explaining each operation.

FIG. 3 is an equivalent circuit diagram (No. 2) for explaining each operation.

FIG. 4 is an equivalent circuit diagram for analyzing a circuit.

FIG. 5 is a configuration diagram showing a conventional example.

[Explanation of symbols]

11 Pixel transistor 12 Vertical selection line 13 Vertical signal line 14 Vertical scanner 15 (..., 15n, 15n + 1, ...) Operation switch transistor 16 (..., 16n, 16n + 1, ...) Load capacitor 17 (..., 17n, 17n + 1, ...) Horizontal Switch transistor 18 Horizontal signal line 20 Horizontal scanner 21 Output circuit 22 Differential amplifier 23 Reset switch transistor

Claims (2)

[Claims] 1. A plurality of pixel units, a plurality of capacitors each having one end connected to each signal line from which a signal is read from the plurality of pixel units, and a signal line from each of the plurality of capacitors. An output circuit that receives a signal supplied via the output circuit and outputs the signal to the outside, and is connected between each of the other ends of the plurality of capacitors and the output end of the output circuit and sequentially turned on in response to a scan pulse. A solid-state imaging device comprising a plurality of switch elements. 2. The output circuit includes a differential amplifier having an inverting input terminal connected to one end of the signal line and a predetermined reference voltage applied to a non-inverting input terminal, and the signal line in response to a reset pulse. 2. The solid-state imaging device according to claim 1, further comprising a reset switch that resets the potential of the.