JPH09186558A - Oscillator - Google Patents

Abstract

(57) Abstract: In an oscillator that oscillates / stops a clock signal by pressing a switch, noise and malfunction caused by chattering when the switch is operated are prevented. SOLUTION: When a switch 1 is pressed once, a CR oscillation circuit starts oscillation of a clock signal 22. This clock signal 22 is divided by a frequency dividing circuit, but the half cycle of the clock signal 24 is made longer than the time during which chattering occurs and the noise time. Then, the level of the signal line 21 is detected every half cycle of the clock signal 24, and it is controlled whether the oscillation of the CR oscillation circuit is continued or stopped depending on the detection signal and the state before the switch 1 is pressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillating device for starting and stopping oscillation of a pulse in response to a switch pulse from a switch means.

[0002]

2. Description of the Related Art An oscillating device that starts and stops oscillation of a pulse in response to a switch pulse from a push switch has conventionally been used as a supply source of an operation clock of an electronic device such as an electronic thermometer. Although used, the conventional oscillator of this type sometimes malfunctions due to external noise.

The present invention has been made to solve the above-mentioned problems, and prevents a malfunction caused by chattering when a push switch is pressed and released, and also prevents a malfunction caused by extraneous noise. An object of the present invention is to provide an oscillation device capable of repeating start and stop of oscillation without malfunction by repeating a switch pressing operation.

[0004]

In order to achieve the above object, an oscillating device of the present invention includes a switch means for generating a switch pulse, and an oscillation start and an oscillation stop of the pulse based on the switch pulse of the switch means. And a detection pulse output means for counting the pulses oscillated by the oscillation means and outputting a detection pulse having a predetermined cycle, and a detection pulse from the detection pulse output means. Determination means for determining whether or not the switch pulse has continued for the detection pulse time, and a state in which the oscillation means oscillates a pulse as a first state, and the oscillation means stops oscillation of the pulse. When the first switch determines that the next switch pulse has been maintained for a predetermined period of time when the first switch is in the first state, Second stop oscillation of the oscillation means
State is maintained, and when the determination means determines that the next switch pulse has been maintained for a predetermined time in the second state, the oscillation means is caused to start oscillation to maintain the first state. And a state maintaining means for performing the operation.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. In the following, of the two outputs of the D-type flip-flop (hereinafter, simply referred to as FF), the output with a bar above Q in the figure will be referred to as Q bar output for convenience.

FIG. 1 is a diagram showing one embodiment of an oscillation device according to the present invention. In this oscillation device, a connection point between a resistor 2 connected to the power supply voltage V _ss and a push switch 1 (hereinafter simply referred to as switch 1) connected to the power supply voltage V _dd is represented by F
This is applied to the D input terminals of F3 and FF4 and the R (reset) input terminal of FF10. The Q output 24 of the FF 20 is provided to the CL (clock) input terminal of the FF 3, and a signal obtained by inverting the Q output 24 of the FF 20 by the inverter 5 is provided to the CL input terminal of the FF 4.

The Q bar output 25 of the FF3 and the Q bar output 26 of the FF4 are supplied to the NOR circuit 6, and this output 27
It is provided to the R input terminal of F7. The power supply voltage _Vdd is introduced into the D input terminal of the FF7, and the FF is supplied to the CL input terminal.
Nineteen Q outputs 23 are provided. The Q bar output 28 of the FF 7 is supplied to the CL input terminal of the FF 8 and the NOR circuit 9. The Q bar output of FF8 is fed back to the D input terminal of FF8. That is, the FF 8 constitutes a 1/2 frequency dividing circuit. The Q output 29 of the FF 8 is supplied to the NOR circuit 9, and the output 30 of the NOR circuit 9 is supplied to the D input terminal of the FF 10.

A clock signal 22 is supplied to a CL input terminal of the FF 10, and a Q output 31 of the FF 10 is supplied to each R input of each of the FFs 17 to 20 constituting a frequency dividing circuit. On the other hand, the Q bar output 32 of the FF 10 is connected to the NAND circuit 11.
Given to.

The NAND circuit 11, the inverter 12,
13, 14, the resistor 15 and the capacitor 16 constitute a CR oscillation circuit, and the clock signal 22 output from the inverter 14 of the CR oscillation circuit is supplied to the FFs 17 to 20.
, And is divided. That is,
The clock signal 22 is input to the CL input terminal of the FF 17, the Q bar output of the FF 17 is fed back to the D input terminal of the FF 17, and the Q output is provided to the CL input terminal of the FF 18. Similarly, the Q-bar output of the FF 18 is fed back to the D input terminal of the FF 18, and its Q output is given to the CL input terminal of the FF in the next stage.

The same connection is repeated, and the FF 19 CL
The Q output of the previous stage FF is input to the input terminal, the Q bar output is fed back to the D input terminal of the FF19, and the Q output 23 is connected to the CL input terminal of the next stage FF20 and the CL output terminal of the FF7.
It is given to the input terminal. Q bar output of FF20 is FF2
0 is fed back to the D input terminal and its Q output 24 is
Of the FF4 via the CL input terminal of the FF4 and the inverter 5
It is provided to the L input terminal.

In FIG. 1, the CR oscillation circuit includes an FF 10
Clock signal 2 when the Q bar output 32 of
2 oscillate. Although not shown in FIG. 1, the clock signal 22 output from the CR oscillation circuit is:
Naturally, it is supplied as an operation clock of an electronic device such as an electronic thermometer on which the oscillation device is mounted.

In the above structure, the switch 1 forms the switching means of the present invention, and the CR oscillation circuit composed of the NAND circuit 11, the inverters 12, 13, 14, the resistor 15 and the capacitor 16 is the oscillation means of the present invention. To form FF17 to FF20
The frequency dividing circuit is composed of the detection pulse output means in the present invention, and the FF3, FF4, the inverter 5 and the NOR circuit 6 form the judgment means in the present invention, and the FF7, FF8 and the NOR circuit 9 are provided. , FF10 form the state holding means in the present invention. These meanings will become more apparent from the following description of the operation.

The operation of the oscillator shown in FIG. 1 will be described with reference to a timing chart shown in FIG.

If it is assumed that the CR oscillation circuit is not oscillating the clock signal 22 and the switch 1 is pressed in this state, the level of the signal line 21 becomes high by the switch pulse. Is reset, the Q bar output 32 of the FF 10 becomes high level, and the CR oscillation circuit starts oscillating the clock signal 22. That is, the NAND circuit 11 is activated by this switch operation, and the CR oscillation circuit composed of the NAND circuit 11, the inverters 12, 13, 14, the resistor 15, and the capacitor 16 is oscillated.

At this time, the Q output 31 of the FF 10 goes low at the same time, and the FF 17
Since the reset of 〜20 is released, the frequency dividing circuit including the FFs 17 to 20 starts frequency division of the clock signal 22.

The FF 3 receives the clock signal 24, which is the Q output of the FF 20, as a clock input, and reads the level of the D input terminal at the falling edge of the clock signal 24. Therefore, when the switch 1 is pressed, the signal line 21 is at the high level, and accordingly, the D of the FF3 is high.
Since the input terminal is at the high level, the high level is read at the falling edge of the clock signal 24, and the Q bar output 25 of the FF3 is at the low level. That is, this FF
3 indicates that the level of the signal line 21 is detected at the falling edge of the clock signal 24.

The FF 4 has a clock input obtained by inverting the clock signal 24, which is the Q output of the FF 20, by the inverter 5, and reads the level of the D input terminal at the falling edge of the clock input. Therefore, when the switch 1 is pressed, the D input terminal of the FF4 is at the high level, so that the high level is read at the falling edge of the clock input, and the Q bar output 26 of the FF4 becomes the low level. That is, it can be said that this FF 4 detects the level of the signal line 21 at the falling edge of the clock input.

Since the clock input of the FF 4 is obtained by inverting the clock signal 24, it can be said that the FF 4 detects the level of the signal line 21 at the rising edge of the clock signal 24. On the other hand, FF
3 detects the level of the signal line 21 at the falling edge of the clock signal 24, so that the FF3 and FF4 detect the level of the signal line 21 every half cycle of the clock signal 24. it can.

The NOR circuit 6 takes the NOR of the Q-bar output 25 of FF3 and the Q-bar output 26 of FF4. Therefore, the level of the signal line 21 is the clock signal 2
If the signal is held at the high level or the low level for a period longer than one cycle of No. 4, the output 27 of the NOR circuit 6 is held at the same level.

From this, by appropriately selecting one cycle of the clock signal 24, when the switch 1 is pressed,
It can also be seen that chattering when separated can be prevented. In other words, if the half cycle of the clock signal 24 is longer than the time during which the switch 1 is chattering, even if the switch 1 is pressed or released, even if chattering occurs, the output of the NOR circuit 6 is generated by the chattering. 27 can be prevented from changing many times, and malfunction due to chattering can be prevented.

This is clear from a detailed study of the operation of the circuit configuration shown in FIG. For example, clock signal 2
4 is longer than the time during which the chattering of the switch 1 occurs, the chattering has already stopped at the first rising edge of the clock signal 24 shown in FIG. In FF4, the high level of the D input terminal can be read without being affected by chattering.

When the switch 1 is pressed, the output 27 of the NOR circuit 6 is at a high level.
Is reset, and its Q output 28 goes from low to high. The Q bar output 28 of this FF7 is FF
8 is supplied to the CL input terminal, but the state of the FF 8 does not change at this time since the state of the FF 8 is inverted at the falling edge of the clock input. Hold. In this case, the low level is maintained.

As described above, the Q output 28 of the FF 7 is at the high level and the Q output 29 of the FF 8 is at the low level. At this time, the output 30 of the NOR circuit 9 is at the low level.

Since the FF 10 reads the level of the D input terminal at the falling edge of the clock signal 22, the FF 10 reads the low level of the D input terminal at the falling edge of the clock signal 22. Since the Q bar output 32 becomes high level,
The oscillation circuit continues to oscillate the clock signal 22.

As described above, the CR oscillation circuit continues to oscillate the clock signal 22 while the switch 1 is pressed.

Next, the operation when the switch 1 is pressed when the CR oscillation circuit stops oscillating, and when the switch 1 is released after the switch 1 is kept pressed for a certain period of time will be described.

When the switch 1 is released, the level of the signal line 21 becomes V _SS , that is, a low level. However, the first rising edge or the falling edge of the clock signal 24 immediately after the switch 1 is released causes the Q bar output of the FF 3 to change. 25,
One of the Q bar outputs 26 of the FF 4 is always at a high level, and the output 27 of the NOR circuit 6 is at a low level. Then, while the switch 1 is kept released thereafter, FF3
Since both the Q bar output 25 and the Q bar output 26 of the FF 4 are at the high level, the output 27 of the NOR circuit 6 holds the low level.

The same applies when chattering occurs when the switch 1 is released. An example is shown in FIG. Here, FF3 will be described as an example.

Now, it is assumed that the clock signal 24 is as shown in FIG. It is also assumed that the half cycle of the clock signal 24 is set to be longer than the time during which the chattering of the switch 1 occurs. Then, the releases the switch 1 continues to push at t ₁ as shown in FIG. 3 (b), and chattering subsides when the time period chattering indicated by a broken line have occurred in t _3.

[0030] In this case, FF3 the signal line at the time of t _{2 2}
At this time, the level of the signal line 21 recognized by the FF 3 is either a high level or a low level. Whether it becomes high level or low level depends on the mode of occurrence of chattering, but in any case, it becomes high level or low level.

At time t ₂ , the FF 3 is connected to the signal line 21.
Is recognized as a low level, the Q bar output 25 of the FF 3 becomes a high level as shown in FIG.
If recognized as a high level at time t _2, Q-bar output 25 of FF3 becomes a high level at the next falling edge of the clock signal 24 as shown in FIG. _{3 (d) (t 5)} . Thus F
The timing at which the Q bar output 25 of F3 changes from low level to high level changes depending on how chattering occurs, but in any case, it goes high without malfunction. This switches the half cycle of the clock signal 24 to the switch 1
This is an effect of making the time longer than the time during which chattering occurs, and this is apparent from a detailed study of the operation of the circuit configuration shown in FIG.

As described above, when the half cycle of the clock signal 24 is set longer than the time during which the chattering of the switch 1 occurs, the FF 3 operates even if the chattering occurs when the switch 1 is operated. It does not malfunction. This is the same for FF4.

When the output 27 of the NOR circuit 6 goes low, the reset of the FF 7 is released. The FF 7 reads the level V _DD of the D input terminal, that is, the high level at the falling edge of the clock signal 23 which is the clock input.
The Q bar output 28 of F7 becomes low level. That is, when the switch 1 is released, the Q bar output 28 of the FF 7 changes from the high level to the low level.

As a result, the state of the FF 8 is inverted, the Q output 29 of the FF 8 goes high, and the output 30 of the NOR circuit 9 holds the low level. Therefore, FF1
Since 0 reads this low level at the falling edge of the clock signal 22, the Q bar output 32 goes high, and the CR oscillation circuit continues to oscillate the clock signal 22. Further, at this time, the Q output 31 of the FF 10 becomes low level, so that the frequency dividing circuit continues the frequency division of the clock signal 22.

As described above, the oscillation of the clock signal 22 is continued when the switch 1 is pushed while the CR oscillation circuit stops oscillating and is released for a certain period of time and then released. .

Next, an operation when the switch 1 is pressed while the CR oscillation circuit continues to oscillate the clock signal 22 will be described.

At this time, since the signal line 21 goes high, the FF 10 is reset and its Q output 32
Holds high level. Therefore, when the switch 1 is pressed, the CR oscillation circuit continues to oscillate the clock signal 22.

On the other hand, the D input terminals of FF3 and FF4 are at high level, and their Q bar outputs 25 and 26 are both at low level, so that the output 27 of the NOR circuit 6 is at high level and the FF 7 is reset. Its Q bar output 28
Becomes high level. Therefore, the output 30 of the NOR circuit 9 becomes low level. The FF 10 receives the clock signal 2
Since the low level of the output 30 of the NOR circuit 9 is read at the falling edge of 2, the Q output 32 becomes high level and the Q output becomes low level. By the above operation,
When the switch 1 is pressed, the CR oscillation circuit continues to oscillate the clock signal 22, and the frequency dividing circuit continues the frequency dividing operation of the clock signal 22.

Next, the operation when the switch 1 is released from the above state will be described.

At this time, since the signal line 21 is at the low level, the reset of the FF 10 is released, and the FF 3 and the FF 10 are reset.
4 are both at low level. Therefore, FF
3, since the Q bar outputs 25 and 26 of the FF 4 are both at a high level, the output 27 of the NOR circuit 6 is at a low level,
The reset of the FF 7 is released.

Therefore, the Q-bar output 28 of the FF 7 goes low since the high level of the D input terminal is read at the first falling edge of the clock signal 23 after the reset is released. That is, Q bar output 2 of FF7
8 changes from a high level to a low level.

As a result, the state of the FF 8 changes, so that the Q output 29 changes from high level to low level, and the output 30 of the NOR circuit 9 changes to high level.

When the output 30 of the NOR circuit 9 goes high, the FF 10 reads this high level at the falling edge of the clock signal 22, so that the Q output 31 goes high and the Q bar output 32 goes low. As a result, the CR oscillation circuit stops oscillating the clock signal 22,
The frequency dividing circuit is reset to stop the frequency dividing operation of the clock signal 22.

Next, a description will be given of the operation when the level of the signal line 21 becomes high due to noise mixing when the switch 1 is released but the CR oscillation circuit continues to oscillate the clock signal 22. I do.

If this extraneous noise is mixed during the period in which the level of the clock signal 24 is maintained at the high level or the low level, the extraneous noise is supplied to the FF3, F
Since no detection is made by F4, no malfunction occurs.

When the clock signal 24 falls while the signal line 21 is at a high level due to external noise, the Q bar output 25 of the FF3 at this time goes to a low level, but at this time, the Q bar output 26 of the FF4 goes to a low level. Is the high level as described above, so that the output 27 of the NOR circuit 6
Will still hold the low level. Therefore, the Q bar output 28 of the FF 7 keeps the low level,
Since the Q output 29 of F8 holds a high level, the output 30 of the NOR circuit 9 holds a low level, and the FF 10 reads the low level at the falling edge of the clock signal 22, so that the Q bar output 32 of the FF 10 is at a high level. , And the CR oscillation circuit continues to oscillate the clock signal 22. This is due to external noise caused by the signal line 21.
The same applies to the case where the clock signal 24 rises while is at the high level.

That is, even if external noise is mixed, if the external noise is shorter than a half cycle of the clock signal 24,
No malfunction is caused by the external noise.

As described above, in this oscillation device, by setting the half cycle of the clock signal 24 to be longer than the time during which external noise and chattering occur, chattering occurs when the switch 1 is pressed and released. Malfunction, malfunction due to external noise can be prevented,
The start and stop of the oscillation of the clock signal 22 can be cyclically repeated according to the repetition of the pressing operation of the switch 1.

[0049]

As described above, the oscillating device of the present invention comprises the switch means for generating the switch pulse and the oscillating means for starting and stopping the oscillation of the pulse based on the switch pulse of the switch means. An oscillating device, which detects a pulse oscillated by the oscillating means and outputs a detection pulse having a predetermined cycle, and a switch pulse which is a detection pulse based on the detection pulse from the detection pulse output means. The determination means for determining whether or not the time has continued, the state in which the oscillating means is oscillating a pulse is a first state, and the state in which the oscillating means stops oscillating a pulse is a second state. When the determination means determines that the next switch pulse has been maintained for a predetermined time in the state of, the oscillation of the oscillation means is stopped and the second state is maintained. In the second state, when the determining means determines that the next switch pulse has been maintained for a predetermined time, the oscillating means is caused to start oscillating and holds the first state. In the first state in which the oscillation device is oscillating, it is possible to prevent a malfunction that the oscillation means stops oscillation due to external noise or chattering, and improve the reliability of the oscillation device.

Furthermore, the second device in which the oscillating device has stopped oscillating
In this state, the oscillating device does not start oscillating except when the switch pulse continues for the detection pulse time by the determining means, and thus low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an oscillator according to the invention.

FIG. 2 is a timing chart for explaining the operation of the oscillation device shown in FIG.

FIG. 3 is a timing chart for explaining an operation when chattering occurs when a switch 1 is released in the oscillation device shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Push switch 2 ... Resistor 3, 4 ... D-type flip-flop 5 ... Inverter 6 ... NOR circuit, 7, 8 ... D-type flip-flop 9 ... NOR circuit 10 ... D-type flip-flop 11 ... NAND circuit 12, 13, 14 ... Inverter 15 ... Resistor 16 ... Capacitor 17, 18, 19, 20 ... D-type flip-flop

Claims (1)

[Claims] 1. An oscillating device comprising switch means for generating a switch pulse and oscillating means for starting and stopping oscillation of the pulse based on the switch pulse of the switch means, wherein the oscillating means oscillates. Detection pulse output means for counting the pulses and outputting a detection pulse having a predetermined cycle, and determination means for determining whether or not the switch pulse has continued for the detection pulse time based on the detection pulse from the detection pulse output means. And a state in which the oscillating means is oscillating a pulse as a first state, and a state in which the oscillating means is oscillating a pulse as a second state, the determining means in the first state. When it is determined that the next switch pulse has been maintained for a predetermined time, the oscillation of the oscillating means is stopped, the second state is maintained, and the second state is set. In a certain case, when the determination means determines that the next switch pulse has been maintained for a predetermined time, the oscillation means is caused to start oscillating, and a state holding means for holding the first state is provided. Oscillator.