JPH0918903A - Exchange equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object of the present invention to provide a switching device capable of preventing an overcurrent due to an increase in a ringer current for calling a telephone. A switching device having a ringer signal generator 2, wherein the ringer signal generator 2 comprises a periodic signal generator 4 for generating a multi-phase periodic signal defining a ringing period, and a ringing period of the periodic signal. Of the active period of the ringing period signal is detected by the configuration having the detecting unit 8 for detecting the overlapping of the ringing period signal and the clearing unit 9 for clearing the periodic signal at the time of the detection, and the ringing period signal is output at the time of overlapping. clear.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching device having a ringer signal generator, and more particularly to a periodic signal generating circuit for ringer ringing.

[0002]

2. Description of the Related Art Button telephone devices and private branch exchanges (PBX)
In such switching devices, a ringer signal is provided for calling a single telephone (SLT).

Generally, a ringer signal has a frequency of 16 Hz, 75
A signal in which a Vrms sine wave is intermittently turned on for a period of 1 second on and 2 seconds off is used. Normally, the power supply unit has a built-in 16 Hz oscillator and amplifier so that a continuous ringer signal
Although it is sent to the extension i / f section for accommodating T and the connection / disconnection is performed there, the whole apparatus may be incorporated in the extension i / f section in a small device.

Here, it has been conventionally practiced to divide the ringing SLT into three systems due to the limitation of the current capacity of the ringer section. That is, as shown in FIG. 5A, the ringer signal is interrupted by a periodic signal having three types of phases. As a result, the ringer signal sent to the SLT is shown in FIG.
As shown in (b), the SLT rings for 1 second and rings for 2 seconds with a ring tone.

FIG. 3 is a block diagram showing the structure of a conventional exchange apparatus.

In the figure, SLTi / f1 is SLT7 ₁ , 7
_The ringer signal generator 2 is an interface for accommodating ₂ and 7 ₃ and is composed of a 16 Hz oscillator and an amplifier and generates a continuous ringer signal.

The power supply unit 3 has the ringer signal generator 2 built-in, and the ringing cycle generating unit 4 generates the ringing cycle signals 5 ₁ , 5 ₂ and 5 ₃ of FIG. 5A. The switch units 6 ₁ , 6 ₂ and 6 ₃ have ringing cycle signals 5 ₁ and 5 5 when receiving a call.
_The ringer signal is interrupted according to the outputs of ₂ and 5 ₃ , and the central control unit (CC) 12 controls the respective units of the exchange. Here, a multiphase signal such as a ringing cycle signal 5 _i (subscript i indicates 1 to 3) whose phases are regularly deviated can be easily created by a counter or the like.

The switch section 6 _i normally connects the SLT 7 _i to the call circuit side, but intermittently connects the SLT 7 _i to the ringer signal generator 2 side in accordance with the output of the ringing cycle signal 5 _i when an incoming call arrives.

As described above, the ringer signal is sent from the ringer signal generator 2 to the SLTs 7 ₁ , 7 ₂ and 7 ₃ via SLTi / f1 under the control of the CC 12. In the figure,
As for the connection line between SLTi / f1 and SLT 7 ₁ , 7 ₂ , and 7 ₃ , only the ringer signal path is shown, and the communication line is omitted.

When an incoming call arrives from the station line 11, the station line i / f10 detects it and notifies CC12. CC12
Controls SLTi / f1 to send a ringer signal to cause SLT7 _i to ring.

Specifically, the CC 8 controls the switch section 6 _i to set the incoming call operation mode. As a result, the switch sections 6 ₁ , 6 ₂ , and 6 ₃ are intermittently operated according to the ringing cycle signals 5 ₁ , 5 ₂ , and 5 ₃ shown in FIG.
_The ringer signal is sent to ₁ , 7 ₂ and 7 ₃ at the timing shown in FIG.

FIG. 4 is a block diagram showing details of the ringer signal path.

Z in the figure is the impedance of the ringer signal receiving circuit of the SLT, which is 2 kΩ according to the regulations of the terminal equipment.
It is specified to have the above impedance. The ringer signal flows through the route of the Tip line (T in the figure) -Z-Ring line (R in the figure), and the SLT sounds.

When SLT7 _i responds off-hook, SLTi / f1 detects and notifies CC12. C
C12 controls the switch unit 6 _i of SLTi / f1 to release the incoming call operation mode.

As a result, since the SLT 7 _i is connected to the communication circuit side, the ringer signal path is the ringing cycle signal 5
Always cut regardless of _i . Thus, the ringer signal transmission is stopped.

Further, CC 12 is a communication path switch 13
Is controlled to connect the station line i / f10 and SLTi / f1. As a result, the station line 11 and the SLT 7 _i are brought into a call state.

[0017]

However, in the above-mentioned conventional example, if the counter malfunctions due to noise or the like and the active periods of the ringing cycle signal 5 _i overlap, the SLTs of a limited number or more will ring. Then, when the number of ringing SLTs increases, the impedance Z of the ringer signal receiving circuit is increased.
Are connected in parallel, there is a risk that the value will decrease, the ringer current will increase, and overcurrent will flow.

An object of the present invention is to provide a switching device capable of preventing overcurrent due to an increase in ringer current for calling a telephone.

[0019]

SUMMARY OF THE INVENTION The present invention is a switching device having ringer signal generating means, wherein the ringer signal generating means includes periodic signal generating means for generating a multi-phase periodic signal defining a ringing period. It is characterized by further comprising: detection means for detecting overlapping of ringing periods of the periodic signal, and clear means for clearing the periodic signal at the time of detection.

[0020]

With the above configuration, the overlapping of the active periods of the ringing cycle signal is detected, and the output of the ringing cycle signal is cleared when the overlapping occurs.

[0021]

1 is a block diagram showing the structure of a switching device according to an embodiment of the present invention.

As shown, the exchange apparatus of this embodiment is
In addition to the configuration of FIG. 3, the ringing cycle generating section 4 is provided with a duplication detecting means 8 and a clearing means 9. Since the other configurations are common to those in FIG. 3, the same reference numerals are given and description thereof will be omitted.

FIG. 2 is a block diagram showing a detailed structure of the duplication detecting means 8 and the clearing means 9.

The duplication detecting means 8 includes gates 8 ₁ , 8 ₂ and 8
_{It is} composed of ₃ and 8 ₄ . The gate 8 ₁ is "1" when the ringing period signal (5 ₁ , 5 ₂ , 5 ₃ ) is (1, 0, 0).
Is output. Similarly, the gate 8 ₂ outputs "1" when (0, 1, 0), and the gate 8 ₃ outputs "1" when (0, 0, 1).

The gate 8 ₄ outputs the NOR (negative logical sum) of the outputs of the gates 8 ₁ , 8 ₂ and 8 ₃ . This output serves as a control signal for the stopping means 9.

The stopping means 9 comprises a 3-state gate 9 ₁ , a resistor 9 ₂ connected to its output, and a register 9 ₃ . The 3-state gate 9 ₁ receives the outputs 5 ₁ ′, 5 ₂ ′, and 5 ₃ ′ of the ringing cycle generator 4, and when the output of the register 9 ₃ is “0”, transfers the input to the output, 9 ₃
When the output of 1 is "1", the output is prohibited (high impedance state).

The set input S of the register 9 ₃ receives the output of the gate 8 ₄ and the reset input R receives the clock signal 4 ₁ of the ringing cycle generator 4. Clock signal 4
Reference numeral ₁ is a source oscillation clock of the ringing cycle signal 5 _i , and has a cycle of 1 second.

In normal operation, ringing cycle signals (5 ₁ , 5 ₂ ,
The possible values of (5 ₃ ) are (1, 0,
0), (0, 1, 0), or (0, 0, 1). That is, since there is no overlap of active periods, "1"
Is only one.

Ringing cycle signal 5 _i due to malfunction due to noise or the like
When the active periods of
Possible values of ₁ , 5 ₂ , 5 ₃ ) are values other than the above.

Therefore, (5 ₁ , 5 ₂ , 5 ₃ ) becomes (1,
Other than 0,0), (0,1,0), and (0,0,1), the output is forcibly cleared as a malfunction.

The gate 8 ₁ outputs "1" when (5 ₁ , 5 ₂ , 5 ₃ ) is (1, 0, 0), and outputs "0" at other times. The gate 8 ₂ has (5 ₁ , 5 ₂ , 5
_{When 3} ) is (0, 1, 0), "1" is output, and at other times, "0" is output. Gate 8 ₃ has (5 ₁ , 5
_{When 2} , 5 ₃ ) is (0, 0, 1), "1" is output, and at other times, "0" is output.

Since the gate 8 ₄ outputs the NOR (negative logical sum) of the outputs of the gates 8 ₁ , 8 ₂ and 8 ₃ ,
₁ , 5, ₂ , 5 ₃ ) are (1, 0, 0), (0, 1, 0),
When it is either (0, 0, 1), "0" is output, and when it is other than that, "1" is output. That is, "0" is output during normal operation, and "1" is output during malfunction.

When the gate 8 ₄ outputs "1", the register 9 ₃ is set by this, and the output Q becomes "1". Therefore, the gate 9 ₁ is in the output high impedance state. Since the resistor 92 pulls it down to the ground level, the output becomes "0". Thus (5 ₁ , 5 ₂ , 5 ₃ ) is cleared to (0, 0, 0),
The overlapping of ringing active periods is eliminated.

The register 9 ₃ is reset by the clock signal 4 ₁ every one second, and the output Q returns to "0". As a result, the gate 9 ₁ inputs (5 ₁ ', 5 ₂ ',
5 ₃ ') is transmitted to the output, so (5 ₁ , 5
The presence / absence of duplication is detected again by the duplication detecting means 8 with respect to ₂ , 5 ₃ ).

Next, the operation will be described with reference to the flowchart of FIG.

First, assuming that (5 ₁ , 5 ₂ , 5 ₃ ) is erroneously changed to (1, 1, 0) (S1), the gate 8 ₁
Outputs "0", the gate 8 ₂ outputs "0", and the gate 8 ₃ outputs "0" (S2). The output of the gate 8 ₄ In this state becomes "1" (S3).

Then, the register 9 ₃ is set, the output Q becomes "1", and the gate 9 ₁ becomes the output high impedance state (S4). Then, it is pulled down to the ground level by the resistor 9 ₂ and the output becomes “0” (S5). In this way, (5 ₁ , 5 ₂ , 5 ₃ ) is cleared to (0, 0, 0).

Since the register 9 ₃ is reset every 1 second (S6), (5 ₁ , 5 ₂ , 5 ₃ ) is cleared and the input state is transmitted to the output again at least 1 second after the clearing. (S7). If the malfunction has not been recovered, the process returns to S2 (S8). If it has been restored, the operation proceeds to a normal incoming call operation (S9).

As described above, when the ringing active period of the ringing cycle signal 5 _i overlaps, the output of 5 _i is cleared and the overlap is eliminated.

In the above embodiment, the ringing cycle signal is cleared by disabling the output by the 3-state gate, but the present invention can be performed by resetting the counter for generating the ringing cycle signal. The essence of does not change, and the same effect can be obtained.

Although the ringing cycle signal has three phases, the present invention is effective without being limited to this.

[0042]

As described above, according to the present invention,
In the switching device having the ringer signal generator, it is possible to prevent an overcurrent due to an increase in the ringer current.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a switching device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a duplication detecting unit and a clearing unit in the above embodiment.

FIG. 3 is a block diagram showing a configuration of a switching device in a conventional example.

FIG. 4 is a block diagram showing details of a ringer signal path in a conventional example.

FIG. 5 is a timing chart showing signal timing in a conventional example.

FIG. 6 is a timing chart showing signal timing in the above embodiment.

FIG. 7 is a flowchart showing an operation in the above embodiment.

[Explanation of symbols]

1 ... SLTi / f, 2 ... Ringer signal generator, 3 ... Power supply section, 4 ... Ring cycle generation section, 6 ₁ , 6 ₂ , 6 ₃ ... Switch section, 7 ₁ , 7 ₂ , 7 ₃ ... SLT, 8 ... Duplication detecting means, 9 ... Clearing means, 10 ... Station line i / f, 11 ... Station line, 12 ... CC, 13 ... Call path switch.

Claims (3)

[Claims] 1. A switching device having ringer signal generating means, wherein the ringer signal generating means includes a periodic signal generating means for generating a multi-phase periodic signal defining a ringing period, and a ringing period for the ringing signal of the periodic signal. An exchange apparatus comprising: detection means for detecting duplication and clear means for clearing the periodic signal at the time of detection. 2. The exchange device according to claim 1, wherein the periodic signal generating means is composed of a counter, and the clearing means resets the counter. 3. The exchange device according to claim 1, wherein the clearing means prohibits output of the periodic signal generating means.