JPH09200040A - Semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: A semiconductor integrated circuit having a small number of elements, a high driving force, and a high speed capable of logical operation of two or more inputs. An input terminal 1a, 1b, an output terminal 2 for outputting a logic signal, a P-channel MOS transistor 11 connected between the input terminal 1a and the output terminal 2, and a gate to which the input terminal 1a is connected, and a gate. Input terminal 1b
Is connected between the input terminal 1b and the output terminal 2, and the N-channel MOS transistor 12 whose input terminal 1a is connected to the gate and the input terminal 1b which is connected to the gate P A CMOS logic circuit 10 having a channel MOS transistor 14, and a high driving power BiCMOS driver 15 having an input terminal 16 to which a logic signal is input, an output terminal 17, an NPN bipolar transistor 20, an inverter circuit 21, and an N channel MOS transistor 25. Set up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a CMOS logic circuit and a BiCMOS logic circuit, and more particularly to an AND circuit and an OR circuit having a small number of elements.

[0002]

2. Description of the Related Art CM used in semiconductor integrated circuits
The OS logic circuit performs logical calculation by inverting the output of the NAND circuit by the inverter in the AND circuit, and similarly, in the OR circuit, inverting the output of the NOR circuit by the inverter. I was doing a logical calculation. However, in such a circuit, there is a problem that the number of calculation steps becomes two and the delay amount in signal transmission increases and the number of elements also increases, as described above.

Therefore, in order to solve the above problems, a semiconductor integrated circuit in which the number of calculation steps and the number of elements are reduced has been proposed. Regarding such a circuit, for example, Japanese Patent Laid-Open No.
The 2-input AND circuit and OR circuit disclosed in Japanese Patent Laid-Open No. 2-194737 will be described with reference to FIGS.

First, FIG. 15 shows the AND circuit. 1
a is the first input terminal, and A is the first input terminal 1
The first input signal inputted to a is a second input terminal, 1b is a second input terminal, and the second is a second input terminal inputted to this second input terminal 1b.
11 is a first P-channel MO in which the drain is connected to the output terminal 2, the source is connected to the first input terminal 1a, and the first input signal A is input to the gate.
A first N-channel MOS transistor of which the drain is connected to the output terminal 2, the source is connected to the first input terminal 1a, and the second input signal B is input to the gate of the S-transistor 12
The second N-channel MOS transistor 13 has a drain connected to the output terminal 2, a source connected to the second input terminal 1b, and a gate to which the first input signal A is input.
The second P-channel MOS transistor 14 has a drain connected to the output terminal 2, a source connected to the second input terminal 1b, and a gate to which the second input signal B is input.
It is a transistor.

The operation of the circuit thus configured will be described. When the high potential side of the input signal is “H” and the low potential side is “L”, the potential applied to the gate of the P-channel MOS transistor 11 is “L” when A = “L” and B = “L”. , The N-channel MOS transistor 12 is turned off because the potential applied to the gate is "L", and the N-channel MOS transistor 13 is turned off because the potential applied to the gate is "L". The MOS transistor 14 is turned on because the potential applied to its gate is "L". Therefore, “L” is output to the output terminal 2.

When A = “H” and B = “L”, the P-channel MOS transistor 11 is turned off because the potential applied to the gate is “H”, and the N-channel MOS transistor 12 is applied to the gate. Is off because the potential applied to the gate is "L", the N-channel MOS transistor 13 is on because the potential applied to the gate is "H", and the potential applied to the P-channel MOS transistor 14 is "L" because it is "L". It turns on. Therefore, “L” is output to the output terminal 2.

When A = “L” and B = “H”, the P-channel MOS transistor 11 is turned on because the potential applied to the gate is “L”, and the N-channel MOS transistor 12 is applied to the gate. Is on because the potential applied to the gate is "H", and turned off because the potential applied to the gate of the N-channel MOS transistor 13 is "L", and the potential applied to the gate of the P-channel MOS transistor 14 is "H". Turns off. Therefore, “L” is output to the output terminal 2.

When A = "H" and B = "H", the P-channel MOS transistor 11 is turned off because the potential applied to the gate is "H", and the N-channel MOS transistor 12 is applied to the gate. Is on because the potential applied to the gate is "H", the N-channel MOS transistor 13 is turned on because the potential applied to the gate is "H", and the potential applied to the P-channel MOS transistor 14 is "H". Turns off. Therefore, “H” is output to the output terminal 2.

Therefore, "H" is output to the output terminal 2 only when both the input signals A and B are "H", and "L" is output in the other cases, so that the output terminal 2 is output.
Then, an AND signal output is obtained.

FIG. 16 shows the OR circuit. 27 is a first N-channel MOS transistor whose drain is connected to the output terminal 2, whose source is connected to the first input terminal 1a, and whose gate receives the first input signal A. 28 is the drain whose output terminal 2 Connected to the source of the first input terminal 1
a first P-channel MOS transistor connected to a and having a gate to which the second input signal B is input; 29, a drain connected to the output terminal 2 and a source connected to the second input terminal 1b
A second P-channel MOS transistor having a gate connected to the first input signal A, a drain connected to the output terminal 2, a source connected to the second input terminal 1b, and a gate connected to the first input signal A. The second input signal B of the second input
N-channel MOS transistor.

The operation of the circuit thus configured will be described. When A = "L" and B = "L", N channel M
The OS transistor 27 is turned off because the potential applied to the gate is "L", the P-channel MOS transistor 28 is turned on because the potential applied to the gate is "L", and the P-channel MOS transistor 29 is applied to the gate. Potential is "L", it is turned on, and N channel M
The OS transistor 30 is turned off because the potential applied to its gate is "L". Therefore, “L” is output to the output terminal 4.

When A = "H" and B = "L", the N-channel MOS transistor 27 is turned on because the potential applied to the gate is "H", and the P-channel MOS transistor 28 is applied to the gate. Is on because the potential applied to the gate is "L", it is turned off because the potential applied to the gate of the P-channel MOS transistor 29 is "H", and the potential applied to the N-channel MOS transistor 30 is "L". Turns off. Therefore, "H" is output to the output terminal 4.

When A = “L” and B = “H”, the N-channel MOS transistor 27 is turned off because the potential applied to the gate is “L”, and the P-channel MOS transistor 28 is applied to the gate. Is turned off because the potential applied to the gate is "L", the P-channel MOS transistor 29 is turned on because the potential applied to the gate is "L", and the potential applied to the N-channel MOS transistor 30 is "H". It turns on. Therefore, "H" is output to the output terminal 4.

When A = “H” and B = “H”, the N-channel MOS transistor 27 is turned on because the potential applied to the gate is “H”, and the P-channel MOS transistor 28 is applied to the gate. Is off because the potential applied to the gate is "H", and is off because the potential applied to the gate is "H", and the potential applied to the N-channel MOS transistor 30 is "H". It turns on. Therefore, "H" is output to the output terminal 4.

Therefore, "L" is output to the output terminal 4 only when both the input signals A and B are "L", and "H" is output in the other cases.
Then, an OR signal output is obtained.

[0016]

However, in the semiconductor integrated circuit configured as described above, there is a problem that it is not possible to perform a logical operation with three or more inputs. or,
Since no driving means is provided and the driving ability depends on the driving force of the input signal, there is also a problem that the operation becomes slow when a large capacity is driven.

The present invention has been made in view of the above points, and a first object thereof is to obtain a semiconductor integrated circuit having a small number of elements and capable of performing a logical operation of three or more inputs. A second object is to obtain a semiconductor integrated circuit having a small number of elements, a high driving force, and a high-speed logical operation of two or more inputs.

[0018]

A semiconductor integrated circuit according to the present invention has N input terminals to which corresponding input signals of N input signals are respectively input, where N is an integer of 3 or more, An output terminal for outputting an output signal, N input nodes specifically connected to the N input terminals, an output node connected to the output terminal, and an input node of the N input nodes A P-channel MOS transistor connected between the input node and the output node and having the gate connected to the above-mentioned 1 input node, and connected in series between the 1 input node and the above-mentioned output node, and the above-mentioned N gates at each gate. Of the other input nodes are connected to N,
And N CMOS circuits each having an N channel MOS transistor of which the number is smaller by one.
P-channel MOS in each of the CMOS circuits
The one input node connected to the gate of the transistor is connected to the corresponding input terminal of the N input terminals.

Further, when N is an integer of 3 or more, N input terminals to which the corresponding input signals of the N input signals are respectively input, output terminals for outputting the output signals, and the N input terminals are provided. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. N to which the input node of 1 above is connected
A channel MOS transistor, which is connected in series between the input node 1 and the output node 1 and the remaining input node of the N input nodes is connected to each gate, and the number of P channels is 1 less than N. And N CMOS circuits having MOS transistors are provided.
The first input node connected to the gate of an N-channel MOS transistor of each of the N CMOS circuits is connected to a corresponding input terminal of the N input terminals. .

Further, when N is an integer of 2 or more, N input terminals to which the corresponding input signals of the N input signals are respectively input, output terminals for outputting a logic signal, and the N number of the above-mentioned N input terminals. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. P to which the input node of 1 above is connected
A channel MOS transistor, which is connected in series between the input node 1 and the output node 1 and the remaining input node of the N input nodes is connected to each gate, and the number of N channels is 1 less than N. N CMOS circuits having MOS transistors, and the N C
A CMOS logic circuit in which the above-mentioned 1 input node connected to the gate of a P-channel MOS transistor included in each MOS circuit is connected to a corresponding input terminal of the above N input terminals, and the above-mentioned logic signal is input. Input terminal, an output terminal for outputting an output signal, an NPN bipolar transistor connected between the power supply potential node and the output terminal and receiving the logic signal at the base, and an inversion of the logic signal receiving the logic signal. A BiCMOS driver having an inverter circuit for outputting a signal and an N-channel MOS transistor connected between the output terminal and the ground potential node and having a gate receiving an inverted signal of the logic signal is provided.

Further, when N is an integer of 2 or more, N input terminals to which the corresponding input signals among the N input signals are respectively input, output terminals for outputting a logic signal, and the N number of the above N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. N to which the input node of 1 above is connected
A channel MOS transistor, which is connected in series between the input node 1 and the output node 1 and the remaining input node of the N input nodes is connected to each gate, and the number of P channels is 1 less than N. N CMOS circuits having MOS transistors, and the N C
A CMOS logic circuit in which the one input node connected to the gate of an N-channel MOS transistor of each MOS circuit is connected to a corresponding input terminal of the N input terminals, and the logic signal is input. Input terminal, an output terminal for outputting an output signal, an NPN bipolar transistor connected between the power supply potential node and the output terminal and receiving the logic signal at the base, and an inversion of the logic signal receiving the logic signal. A BiCMOS driver having an inverter circuit for outputting a signal and an N-channel MOS transistor connected between the output terminal and the ground potential node and having a gate receiving an inverted signal of the logic signal is provided.

Further, when N is an integer of 2 or more, N input terminals to which the corresponding input signals of the N input signals are respectively input, output terminals for outputting a logic signal, and the N number of the above-mentioned N input terminals. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. P to which the input node of 1 above is connected
A channel MOS transistor, which is connected in series between the input node 1 and the output node 1 and the remaining input node of the N input nodes is connected to each gate, and the number of N channels is 1 less than N. N CMOS circuits having MOS transistors, and the N C
A CMOS logic circuit in which the above-mentioned 1 input node connected to the gate of a P-channel MOS transistor included in each MOS circuit is connected to a corresponding input terminal of the above N input terminals, and the above-mentioned logic signal is input. Input terminal, an output terminal for outputting an output signal, an NPN bipolar transistor connected between the power supply potential node and the output terminal and receiving the logic signal at the base, and a connection between the output terminal and the ground potential node. And a BiCMOS driver having a constant current generating circuit.

Further, when N is an integer of 2 or more, N input terminals to which the corresponding input signals of the N input signals are respectively input, output terminals for outputting a logic signal, and the N number of the above N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. N to which the input node of 1 above is connected
A channel MOS transistor, which is connected in series between the input node 1 and the output node 1 and the remaining input node of the N input nodes is connected to each gate, and the number of P channels is 1 less than N. N CMOS circuits having MOS transistors, and the N C
A CMOS logic circuit in which the one input node connected to the gate of an N-channel MOS transistor of each MOS circuit is connected to a corresponding input terminal of the N input terminals, and the logic signal is input. Input terminal, an output terminal for outputting an output signal, an NPN bipolar transistor connected between the power supply potential node and the output terminal and receiving the logic signal at the base, and a connection between the output terminal and the ground potential node. And a BiCMOS driver having a constant current generating circuit.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS. 1 is a circuit diagram of a main part of a 3-input CMOS AND circuit according to a first embodiment of the present invention. In FIG. 1, 1a, 1b, and 1c are input terminals of the AND circuit. Input signal A is input to input signals A and 1b, and input signal C is input to input signals 1c. Reference numeral 2 denotes an output terminal of the CMOS AND circuit, which outputs an output signal.

Reference numerals 3, 4, 5 denote three CMOS circuits respectively connected to the input terminals 1a, 1b, 1c and the output terminal 2, and reference numerals 31, 32, 33 denote input nodes of the CMOS circuit 3, respectively. Is connected to the input terminal 1a, 32 is connected to the input terminal 1b, and 33 is connected to the input terminal 1c.
1, 42 and 43 are input nodes of the CMOS circuit 4,
41 is the input terminal 1b, 42 is the input terminal 1c
3, the input terminals 1a are respectively connected, 51, 52,
Reference numeral 53 is an input node of the CMOS circuit 5, 51 is connected to the input terminal 1c, 52 is connected to the input terminal 1a, and 53 is connected to the input terminal 1b. Also, 34, 44, 54
Are output nodes of the CMOS circuits 3, 4, and 5, respectively.

FIG. 2 is a circuit diagram of a main part showing the CMOS circuit 3. Reference numerals 31 to 34 are the same as those shown in FIG. 1, respectively, and 35 is connected between the input node 31 and the output node 34 and has the gate connected to the input node 3
1 is a P-channel MOS transistor connected to
Reference numerals 36 and 37 are two N-channel MOS transistors connected between the input node 31 and the output node 34, the input node 32 is connected to the gate of 36, and the input node 33 is connected to the gate of 37.

FIG. 3 is a circuit diagram of an essential part showing the CMOS circuit 4. 41 to 44 are the same as those shown in FIG. 1, respectively, and 45 is connected between the input node 41 and the output node 44, and the input node 4 is connected to the gate.
1 is a P-channel MOS transistor connected to
Reference numerals 46 and 47 are two N-channel MOS transistors connected between the input node 41 and the output node 44, the input node 42 is connected to the gate of 46, and the input node 43 is connected to the gate of 47.

FIG. 4 is a circuit diagram of an essential part showing the CMOS circuit 5. Reference numerals 51 to 54 are the same as those shown in FIG. 1, respectively, and 55 is connected between the input node 51 and the output node 54, and the input node 5 is connected to the gate.
1 is a P-channel MOS transistor connected to
Reference numerals 56 and 57 are two N-channel MOS transistors connected between the input node 51 and the output node 54, the input node 52 is connected to the gate of 56, and the input node 53 is connected to the gate of 57.

Next, the operation of the 3-input CMOS AND circuit shown in FIGS. 1 to 4 will be described. Here, the high potential side of the input signal is "H" and the low potential side is "L".
And

First, the input signal A = “H” input to the input terminal 1a, and the input signal B = input to the input terminal 1b.
“H”, input signal C = “H” input to the input terminal 1c
In the case of, N-channel MOS transistors 36, 37, 4
Since the potentials applied to the respective gates of 6, 47, 56 and 57 are "H", all of them are turned on, and therefore "H" is output to the output terminal 2.

On the other hand, at least one of the input signals is "L".
In the case of, for example, the input signal A input to the input terminal 1a
= “L”, the input signal B input to the input terminal 1b =
“H”, input signal C = “H” input to the input terminal 1c
At this time, the P-channel MOS transistor 35 is turned on because the potential applied to the gate is "L", and the output node 3
“L” is output to 4. On the other hand, the potentials applied to the gates of the P-channel MOS transistors 45 and 55 are "H".
Therefore, it is turned off, and N-channel MOS transistor 4
6 and 57 are turned off because the potential applied to the gate is "L", and "H" is not output to the output nodes 44 and 54. Therefore, “L” is output to the output terminal 2.
Similarly, when at least one of the input signals is "L", "L" is output to the output terminal 2.

Therefore, in the 3-input CMOS AND circuit thus constructed, the output terminal 2 is provided only when the input signals A, B and C are all "H", although the number of elements is small. Since "H" is output and "L" is output in other cases, AND is applied to the output terminal 2.
A signal output will be obtained.

Similarly to the case of the three inputs described above, the number of CMOS circuits as constituent elements and a plurality of CMOS circuits which are included in the CMOS circuits and which are connected in series between the input node and the output node. By increasing the number of N-channel MOS transistors in a matched state, the A
An ND circuit may be configured, and in this case as well, as in the case of the above-described three inputs, the number of elements is small and the number of inputs is four or more.
An AND circuit of MOS can be obtained. Furthermore, this C
By using a driving means using a small amplitude, for example, a BiCMOS driver in the next stage of the MOS AND circuit,
The driving force can be increased and the operation speed can be increased.

Embodiment 2 The second embodiment of the present invention will be described below with reference to FIGS. FIG. 5 is a circuit diagram of a main part of a 3-input CMOS OR circuit showing a second embodiment of the present invention. In FIG.
b and 1c are input terminals of this OR circuit, for example, 1
Input signal A is input to a, input signal B is input to 1b, and input signal C is input to 1c. Reference numeral 2 is an output terminal of the OR circuit of the CMOS, which outputs an output signal.

Reference numerals 7, 8, 9 denote CMOS circuits, 71,
72 and 73 are input nodes of the CMOS circuit 7,
The input terminal 1a is connected to the input terminal 1b, the input terminal 1b is connected to the input terminal 72, and the input terminal 1c is connected to the input terminal 73.
Is an input node of the CMOS circuit 8. The input terminal 1b is connected to 81, the input terminal 1c is connected to 82, the input terminal 1a is connected to 83, and 91, 92, and 93 are CMOS.
It is an input node of the circuit 9, and 91 has an input terminal 1c,
The input terminal 1a is connected to 92, and the input terminal 1b is connected to 93. Also, 74, 84 and 94 are CMs, respectively.
The output nodes of the OS circuits 7, 8 and 9.

FIG. 6 is a circuit diagram of a main part showing the CMOS circuit 7. 71 to 74 are the same as those shown in FIG. 5, respectively, and 75 is connected between the input node 71 and the output node 74, and the input node 7 is connected to the gate.
1 is an N-channel MOS transistor connected to
Reference numerals 76 and 77 are two P-channel MOS transistors connected between the input node 71 and the output node 74, the input node 72 is connected to the gate of 76, and the input node 73 is connected to the gate of 77.

FIG. 7 is a circuit diagram of an essential part showing the CMOS circuit 8. Reference numerals 81 to 84 are the same as those shown in FIG. 5, respectively, and 85 is connected between the input node 81 and the output node 84, and has the gate connected to the input node 8
1 is an N-channel MOS transistor connected to
Reference numerals 86 and 87 are two P-channel MOS transistors connected between the input node 81 and the output node 84, the input node 82 is connected to the gate of 86, and the input node 83 is connected to the gate of 87.

FIG. 8 is a main part circuit diagram showing the CMOS circuit 9. Reference numerals 91 to 94 are the same as those shown in FIG. 5, respectively, and 95 is connected between the input node 91 and the output node 94 and has the gate connected to the input node 9
1 is an N-channel MOS transistor connected to
Reference numerals 96 and 97 are two P-channel MOS transistors connected between the input node 91 and the output node 94, the input node 92 is connected to the gate of 96, and the input node 93 is connected to the gate of 97.

Next, the operation of the 3-input CMOS OR circuit shown in FIGS. 5 to 8 will be described. Here, the high potential side of the input signal is "H" and the low potential side is "L".

First, the input signal A = “L” input to the input terminal 1a, and the input signal B = input to the input terminal 1b.
“L”, the input signal C = “L” input to the input terminal 1c
At the time of, P-channel MOS transistors 76, 77, 8
Since the potentials applied to the respective gates of 6, 87, 96 and 97 are "L", all of them are turned on, and therefore "L" is output to the output terminal 2.

On the other hand, at least one of the input signals is "H".
In the case of, for example, the input signal A input to the input terminal 1a
= “H”, input signal B input to the input terminal 1b =
“L”, the input signal C = “L” input to the input terminal 1c
At this time, the N-channel MOS transistor 75 is turned on because the potential applied to the gate is "H", and the output node 7
“H” is output to 4. On the other hand, the potential applied to the gates of the N-channel MOS transistors 85 and 95 is "L".
Therefore, it is turned off, and the P-channel MOS transistor 8
Since the potentials applied to the gates of the gates 6 and 97 are "H", they are turned off, and "L" is not output to the output nodes 84 and 94. Therefore, “H” is output to the output terminal 2.
Similarly, when at least one of the input signals is "H", "H" is output to the output terminal 2.

Therefore, in the 3-input CMOS OR circuit thus constructed, the output terminal 2 is provided only when the input signals A, B and C are all "L", although the number of elements is small. Since "L" is output and "H" is output in other cases, an OR signal output is obtained at the output terminal 2.

Further, in the same manner as in the case of three inputs described above, the number of CMOS circuits as constituent elements and a plurality of CMOS circuits included in the CMOS circuits and connected in series between the input node and the output node are included. By increasing the number of P-channel MOS transistors in the matched state, the O
The R circuit may be configured, and even in this case, the above 3
As in the case of input, CM with a small number of elements and 4 or more inputs
An OS OR circuit can be obtained. Furthermore, this CMO
By using a driving means using a small amplitude, for example, a BiCMOS driver in the next stage of the S OR circuit, the driving force can be increased and the operation can be performed at high speed.

Embodiment 3. The third embodiment of the present invention will be described below with reference to FIG. FIG. 9 shows a 2-input BiCMOS AND according to a third embodiment of the present invention.
FIG. 10 is a circuit diagram of a main part of the circuit. In FIG. 9, 10 is a 2-input CMOS AND circuit, and 1a and 1b are CMs.
It is an input terminal of the AND circuit of the OS, and for example, the input signal A is input to 1a and the input signal B is input to 1b. Reference numeral 2 denotes an output terminal of the CMOS AND circuit, which outputs a logic signal.

The drain of 11 is connected to the output terminal 2,
The source is connected to the input terminal 1a and the gate receives the input signal A
Is input to the P-channel MOS transistor, the drain of 12 is connected to the output terminal 2, and the source is to the input terminal 1a.
, An N-channel MOS transistor having a gate connected to the input signal B, a drain connected to the output terminal 2, a source connected to the input terminal 1b, and an N-channel MOS transistor receiving the input signal A at the gate. The transistor 14 is a P-channel MOS transistor having a drain connected to the output terminal 2, a source connected to the input terminal 1b, and a gate to which the input signal B is input.

Reference numeral 15 is a BiCMOS driver,
Reference numeral 16 is an input terminal of this driver to which the logic signal is input, 17 is an output terminal of this driver and outputs an output signal, and 18 and 19 are a power supply potential node and a ground potential node connected to this driver. .

20 is a power supply potential node 18 and an output terminal 17
NPN connected between the two and receiving the logic signal at the base
The bipolar transistor 21 is an inverter circuit that receives the logic signal and outputs an inverted signal thereof.
The P-channel MOS transistor 22 connected between the power supply potential node 18 and the output node 24 of the inverter circuit 21 and receiving the logic signal at its gate, and the ground potential node 19 and the output node 24 at its gate are connected to the gate. N-channel MOS transistor 2 for receiving the logic signal
Reference numeral 3 denotes an N-channel MOS transistor which is composed of 3 and which outputs an inverted signal of the logic signal to the output node 24 and receives the inverted signal at its gate and is connected between the output terminal 17 and the ground potential node 19.

Next, the operation of the 2-input BiCMOS AND circuit configured as shown in FIG. 9 will be described. Here, the high potential side of the input signal is "H" and the low potential side is "L".

First, the input signal A = “H” input to the input terminal 1a, and the input signal B = input to the input terminal 1b.
When "H", N-channel MOS transistors 12 and 1
Since the potentials applied to the respective gates of 3 are "H", they are turned on, and therefore the logic signal "H" is output to the output terminal 2. Here, the logic signal "H" is lower than "H" of the input signals A and B by the amount of the threshold voltage of the N-channel MOS transistors 12 and 13.

Next, the logic signal is input to the input terminal 16 of the BiCMOS driver 15. At this time, the potential applied to the base of the NPN bipolar transistor 20 is "H", and the inverted signal of the logic signal output from the inverter circuit 21 and applied to the gate of the N-channel MOS transistor 25 is "L". , N channel MO
The S transistor 25 is turned off, and the output signal “H” is output to the output terminal 17. Here, the output signal "H" is amplified by this BiCMOS driver and becomes closer to "H" of the input signals A and B than the logic signal "H".

On the other hand, at least one of the input signals is "L".
In the case of, for example, the input signal A input to the input terminal 1a
= “L”, the input signal B input to the input terminal 1b =
When the potential is "H", the P-channel MOS transistor 11 is turned on because the potential applied to the gate is "L", while the P-channel MOS transistor 14 is turned off because the potential applied to the gate is "H". Similarly, the N-channel MOS transistor 13 is turned off because the potential applied to its gate is "L", and "L" is output to the output terminal 2. Here, this logical signal "L" is the P channel MO.
The threshold voltage of the S-transistor 11 is higher than "L" of the input signal A by the magnitude of the threshold voltage.

Next, the logic signal is input to the input terminal 16 of the BiCMOS driver 15. At this time, the potential applied to the base of the NPN bipolar transistor 20 is "L", and the inverted signal of the logic signal output from the inverter circuit 21 and applied to the gate of the N-channel MOS transistor 25 is "H". , N channel MO
The S transistor 25 is on, and the output signal “L” is output to the output terminal 17. Here, the output signal "L" is amplified by this BiCMOS driver as compared with the logic signal "L", and comes closer to "L" of the input signal A.

Therefore, in the 2-input BiCMOS AND circuit thus constructed, the output terminal 17 is "H" only when both the input signals A and B are "H" although the number of elements is small. Is output, and in other cases, "L" is output.
An ND signal output will be obtained. In addition, BiCMOS
Since the driver is used as the driving means, the driving force is large and high speed operation is possible.

Further, instead of the 2-input CMOS AND circuit 10, a C having 3 or more inputs shown in the first embodiment is used.
A MOS AND circuit may be used, and in this case as well, as in the case of the two inputs described above, a BiCMOS AND circuit having three or more inputs and having a small number of elements can be obtained.

Embodiment 4 Embodiment 4 of the present invention will be described below with reference to FIG. FIG. 10 shows a 2-input BiCMOS O according to a fourth embodiment of the present invention.
FIG. 11 is a circuit diagram of an essential part of the R circuit, and in FIG. 10, 26 is 2
Input CMOS OR circuit, 1a and 1b are C
It is an input terminal of a MOS OR circuit. For example, an input signal A is input to 1a and an input signal B is input to 1b. Reference numeral 2 is an output terminal of the CMOS OR circuit, which outputs a logic signal.

The drain of 27 is connected to the output terminal 2,
The source is connected to the input terminal 1a and the gate receives the input signal A
Is input to the N-channel MOS transistor, the drain of 28 is connected to the output terminal 2, and the source is to the input terminal 1a.
, A P-channel MOS transistor having a gate to which an input signal B is input, and a P-channel MOS transistor having a drain connected to the output terminal 2, a source connected to the input terminal 1b, and an input signal A input to the gate. The transistor 30 is an N-channel MOS transistor having a drain connected to the output terminal 2, a source connected to the input terminal 1b, and an input signal B input to the gate.

Reference numeral 15 is a BiCMOS driver,
Reference numeral 16 is an input terminal of this driver to which the logic signal is input, 17 is an output terminal of this driver and outputs an output signal, and 18 and 19 are a power supply potential node and a ground potential node connected to this driver. .

20 is a power supply potential node 18 and an output terminal 17
NPN connected between the two and receiving the logic signal at the base
The bipolar transistor 21 is an inverter circuit that receives the logic signal and outputs an inverted signal thereof.
A P-channel MOS transistor 22 connected between the power supply potential node 18 and the output node 24 of the inverter circuit 21 and receiving the logic signal at its gate, and a ground potential node 19 and the output node 24 are connected at its gate. It is composed of an N-channel MOS transistor 23 which receives a logic signal, and outputs an inverted signal of the logical signal to the output node 24, and 25 receives the inverted signal at its gate, and the output terminal 1
N-channel M connected between 7 and ground potential node 19
OS transistor.

Next, the operation of the 2-input BiCMOS OR circuit configured as shown in FIG. 10 will be described. Here, the high potential side of the input signal is "H" and the low potential side is "L".

First, the input signal A = “L” input to the input terminal 1a, and the input signal B = input to the input terminal 1b.
When "L", P-channel MOS transistors 28 and 2
Since the potentials applied to the respective gates of 9 are "L", they are turned on, and therefore the logic signal "L" is output to the output terminal 2. Here, the logic signal "L" is higher than the "L" of the input signals A and B by the magnitude of the threshold voltage of the P channel MOS transistors 28 and 29.

Next, the logic signal is input to the input terminal 16 of the BiCMOS driver 15. At this time, the potential applied to the base of the NPN bipolar transistor 20 is “L”, and the potential is output from the inverter circuit 21 to be N
Since the inversion signal of the logic signal applied to the gate of the channel MOS transistor 25 is “H”, the N channel M
The OS transistor 25 is turned on, and the output signal “L” is output to the output terminal 17. Here, the output signal "L" is amplified by this BiCMOS driver and becomes closer to "L" of the input signals A and B than the logic signal "L".

On the other hand, at least one of the input signals is "H".
In the case of, for example, the input signal A input to the input terminal 1a
= “H”, input signal B input to the input terminal 1b =
When it is "L", the N-channel MOS transistor 27 is turned on because the potential applied to the gate is "H", while the P-channel MOS transistor 29 is turned off because the potential applied to the gate is "H". Similarly, the N-channel MOS transistor 30 is turned off because the potential applied to its gate is "L", and "H" is output to the output terminal 2. Here, this logic signal "H" is the N channel MO.
It is lower than "H" of the input signal A by the amount of the threshold voltage of the S transistor 27.

Next, the logic signal is input to the input terminal 16 of the BiCMOS driver 15. At this time, the potential applied to the base of the NPN bipolar transistor 20 is “H”, and the potential is output from the inverter circuit 21 and is N.
Since the inversion signal of the logic signal applied to the gate of the channel MOS transistor 25 is "L", the N channel M
The OS transistor 25 is turned off, and the output signal “H” is output to the output terminal 17. Here, the output signal "H" is amplified by this BiCMOS driver as compared with the logic signal "H", and comes closer to "H" of the input signal A.

Therefore, in the two-input BiCMOS OR circuit thus configured, the output terminal 17 is "L" only when both the input signals A and B are "L" although the number of elements is small. Is output, and in other cases, "H" is output, so that OR is applied to the output terminal 17.
A signal output will be obtained. Further, since the BiCMOS driver is used as the driving means, the driving force is large and the high speed operation becomes possible.

Further, instead of the 2-input CMOS OR circuit 26, a CM having 3 or more inputs shown in the second embodiment is used.
An OR circuit of OS may be used, and in this case as well,
Similar to the case of two inputs, it is possible to obtain a BiCMOS OR circuit having three or more inputs with a small number of elements.

Embodiment 5 The fifth embodiment of the present invention will be described below with reference to FIG. FIG. 11 shows a 2-input BiCMOS A according to a fifth embodiment of the present invention.
It shows an ND circuit. The fifth embodiment is different from the third embodiment only with respect to the BiCMOS driver 15, and the other points are the same as those of the third embodiment described above.

In the third embodiment, the BiCMOS driver 15 has a structure including the NPN bipolar transistor 20, the inverter circuit 21 and the N-channel MOS transistor 25. However, in the fifth embodiment, the BiCMOS driver 15 has the Bi structure.
As shown in FIG. 11, the CMOS driver 15 is connected between the power supply potential node 18 and the output terminal 17, and has an NPN bipolar transistor 20 for receiving a logic signal output from the CMOS AND circuit 10 at its base and a ground potential. The structure is provided with a constant current generation circuit 31 that is connected between the node 19 and the output terminal 17 and generates a constant current.

AND of such two-input BICMOS
Since the circuit has the above structure,
In addition to having the same effect as the third embodiment, it has the effect of having a smaller number of elements.

Further, as the constant current generating circuit 31, specifically, for example, as shown in FIG. 12, an N channel MOS transistor 32 having a gate to which a constant voltage V is applied is applied.
May be used, and in this case also, the above-mentioned effects are obtained. At this time, the constant voltage V may be a power supply voltage or a chip select signal.

Further, a 2-input CMOS AND circuit 10
Instead of the above, the CMOS AND circuit having three or more inputs shown in the first embodiment may be used, and in this case also, the above-described effect is obtained.

Embodiment 6 FIG. The sixth embodiment of the present invention will be described below with reference to FIG. FIG. 13 shows a 2-input BiCMOS O according to a sixth embodiment of the present invention.
It shows an R circuit. In the sixth embodiment,
The BiCMOS driver 15 is different from that of the fourth embodiment, and the other points are the same as those of the above-described fourth embodiment.

In the fourth embodiment, the BiCMOS driver 15 has a structure including the NPN bipolar transistor 20, the inverter circuit 21, and the N-channel MOS transistor 25. However, in the fifth embodiment, the BiCMOS driver 15 has a Bi structure.
As shown in FIG. 11, the CMOS driver 15 is connected between a power supply potential node 18 and an output terminal 17, and has an NPN bipolar transistor 20 for receiving a logic signal output from a CMOS OR circuit 26 at its base and a ground potential. The structure is provided with a constant current generation circuit 31 that is connected between the node 19 and the output terminal 17 and generates a constant current.

Since such a 2-input BICMOS OR circuit has the structure as described above, it has the same effect as that of the fourth embodiment and further has the effect of having a smaller number of elements.

Further, as the constant current generating circuit 31, specifically, for example, as shown in FIG. 14, an N-channel MOS transistor 32 having a gate to which a constant voltage V is applied.
May be used, and in this case also, the above-mentioned effects are obtained. At this time, the constant voltage V may be a power supply voltage or a chip select signal.

Further, instead of the 2-input CMOS OR circuit 26, the C having 3 or more inputs shown in the second embodiment is used.
A MOS OR circuit may be used, and in this case as well, the above-mentioned effects are obtained.

[0076]

The semiconductor integrated circuit according to the present invention has the advantage that it has a small number of elements and can perform logical operations of three or more inputs. Further, the number of elements is small, the driving force is high, and there is an effect that a logical operation of two or more inputs can be performed at a high speed.

[Brief description of drawings]

FIG. 1 is a 3-input CM showing a first embodiment of the present invention.
An equivalent circuit diagram of an AND circuit of the OS.

FIG. 2 is a main part circuit diagram showing a CMOS circuit 3 according to the first embodiment of the present invention.

FIG. 3 is a main part circuit diagram showing a CMOS circuit 4 according to the first embodiment of the present invention.

FIG. 4 is a main part circuit diagram showing a CMOS circuit 5 according to the first embodiment of the present invention.

FIG. 5 is a 3-input CM showing a second embodiment of the present invention.
An equivalent circuit diagram of the OR circuit of the OS.

FIG. 6 is a main part circuit diagram showing a CMOS circuit 7 according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of essential parts showing a CMOS circuit 8 according to a second embodiment of the present invention.

FIG. 8 is a main part circuit diagram showing a CMOS circuit 9 according to a second embodiment of the present invention.

FIG. 9 is a two-input Bi showing the third embodiment of the present invention.
An equivalent circuit diagram of a CMOS AND circuit.

FIG. 10 is a 2-input B showing the fourth embodiment of the present invention.
An equivalent circuit diagram of an iCMOS OR circuit.

FIG. 11 is a 2-input B showing the fifth embodiment of the present invention.
An equivalent circuit diagram of an iCMOS AND circuit.

FIG. 12 is a 2-input B showing the fifth embodiment of the present invention.
An equivalent circuit diagram of an iCMOS AND circuit.

FIG. 13 is a 2-input B showing the sixth embodiment of the present invention.
An equivalent circuit diagram of an iCMOS OR circuit.

FIG. 14 is a 2-input B showing the sixth embodiment of the present invention.
An equivalent circuit diagram of an iCMOS OR circuit.

FIG. 15 is an equivalent circuit diagram of a conventional 2-input CMOS AND circuit.

FIG. 16 is an equivalent circuit diagram of a conventional 2-input CMOS OR circuit.

[Explanation of symbols]

1a, 1b, 1c input terminals, 2 output terminals, 3,
4, 5, 7, 8, 9 CMOS circuit, 10 CMOS
AND circuit 11, 14 P-channel MOS transistor, 12, 1
3 N-channel MOS transistor, 15 BiCMO
S driver, 16 BiCMOS driver input terminal, 17 BiCMOS driver output terminal, 18
Power supply potential node, 19 ground potential node, 20 NP
N bipolar transistor, 21 inverter circuit,
22 P-channel MOS transistor, 23, 25 N
Channel MOS transistor, 24 Output node of inverter circuit, 26 CMOS OR circuit, 27, 30
N channel MOS transistor, 28, 29 P channel MOS transistor, 31 constant current generating circuit,
32 N-channel MOS transistor.

Claims (7)

[Claims] 1. N input terminals to which the corresponding input signals of N (N is an integer of 3 or more) input signals are respectively input, output terminals for outputting an output signal, and the N input terminals. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. A P-channel MOS transistor to which the above-mentioned 1 input node is connected, connected in series between the above-mentioned 1 input node and the output node, and the remaining input nodes of the above N input nodes are connected to respective gates. And N CMOS circuits having N channel MOS transistors less than N by 1 and connected to the gates of the P channel MOS transistors of each of the N CMOS circuits. The semiconductor integrated circuit according to claim 1, wherein each of the input nodes is connected to a corresponding input terminal of the N input terminals. 2. N input terminals to which corresponding input signals of N (N is an integer of 3 or more) input signals are respectively input, output terminals for outputting an output signal, and the N input terminals. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. An N-channel MOS transistor to which the above-mentioned 1 input node is connected, is connected in series between the above-mentioned 1 input node and the output node, and the remaining input nodes of the above-mentioned N input nodes are connected to respective gates. And N CMOS circuits having P channel MOS transistors less than N by 1 and connected to the gates of the N channel MOS transistors of each of the N CMOS circuits. The semiconductor integrated circuit according to claim 1, wherein each of the input nodes is connected to a corresponding input terminal of the N input terminals. 3. N input terminals to which corresponding input signals of N (N is an integer of 2 or more) input signals are respectively input, output terminals for outputting a logic signal, and the N input terminals. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. A P-channel MOS transistor to which the above-mentioned 1 input node is connected, connected in series between the above-mentioned 1 input node and the output node, and the remaining input nodes of the above N input nodes are connected to respective gates. And N CMOS circuits having N channel MOS transistors less than 1 by N, and connected to the gates of the P channel MOS transistors of each of the N CMOS circuits. A CMOS logic circuit in which each of the input nodes is connected to a corresponding input terminal of the N input terminals, an input terminal to which the logic signal is input, and an output terminal to output an output signal; An NPN bipolar transistor connected between a power supply potential node and the output terminal to receive the logic signal at its base, an inverter circuit for receiving the logic signal and outputting an inverted signal of the logic signal, the output terminal and the ground potential node A semiconductor integrated circuit including a BiCMOS driver having an N-channel MOS transistor connected between the two and having a gate receiving an inverted signal of the logic signal. 4. N input terminals to which corresponding input signals of N (N is an integer of 2 or more) input signals are respectively input, output terminals for outputting a logic signal, and the N input terminals. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. An N-channel MOS transistor to which the above-mentioned 1 input node is connected, is connected in series between the above-mentioned 1 input node and the output node, and the remaining input nodes of the above-mentioned N input nodes are connected to respective gates. And N CMOS circuits having P channel MOS transistors less than N by 1 and connected to the gates of the N channel MOS transistors of each of the N CMOS circuits. A CMOS logic circuit in which each of the input nodes is connected to a corresponding input terminal of the N input terminals, an input terminal to which the logic signal is input, and an output terminal to output an output signal; An NPN bipolar transistor connected between a power supply potential node and the output terminal to receive the logic signal at its base, an inverter circuit for receiving the logic signal and outputting an inverted signal of the logic signal, the output terminal and the ground potential node A semiconductor integrated circuit including a BiCMOS driver having an N-channel MOS transistor connected between the two and having a gate receiving an inverted signal of the logic signal. 5. N input terminals to which corresponding input signals of N (N is an integer of 2 or more) input signals are input respectively, output terminals for outputting a logic signal, and the N input terminals. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. A P-channel MOS transistor to which the above-mentioned 1 input node is connected, connected in series between the above-mentioned 1 input node and the output node, and the remaining input nodes of the above N input nodes are connected to respective gates. And N CMOS circuits having N channel MOS transistors less than 1 by N, and connected to the gates of the P channel MOS transistors of each of the N CMOS circuits. A CMOS logic circuit in which each of the input nodes is connected to a corresponding input terminal of the N input terminals, an input terminal to which the logic signal is input, and an output terminal to output an output signal; A semiconductor including a BiCMOS driver having an NPN bipolar transistor connected between a power supply potential node and the output terminal and receiving the logic signal at the base, and a constant current generating circuit connected between the output terminal and the ground potential node. Integrated circuit. 6. N input terminals to which corresponding input signals of N (N is an integer of 2 or more) input signals are respectively input, output terminals for outputting a logic signal, and the N input terminals. N input nodes that are specially connected to the input terminals, output nodes that are connected to the output terminals, and are connected between one of the N input nodes and the output node, and to the gate. An N-channel MOS transistor to which the above-mentioned 1 input node is connected, is connected in series between the above-mentioned 1 input node and the output node, and the remaining input nodes of the above-mentioned N input nodes are connected to respective gates. And N CMOS circuits having P channel MOS transistors less than N by 1 and connected to the gates of the N channel MOS transistors of each of the N CMOS circuits. A CMOS logic circuit in which each of the input nodes is connected to a corresponding input terminal of the N input terminals, an input terminal to which the logic signal is input, and an output terminal to output an output signal; A semiconductor including a BiCMOS driver having an NPN bipolar transistor connected between a power supply potential node and the output terminal and receiving the logic signal at the base, and a constant current generating circuit connected between the output terminal and the ground potential node. Integrated circuit. 7. The semiconductor integrated circuit according to claim 5, wherein the constant current generating circuit includes an N-channel MOS transistor having a gate to which a constant voltage is applied.