JPH09200044A - Steady-state error reduction system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a PLL circuit with an excellent transient response and a steady-state characteristic by calculating an offset of a signal received by a VCO(voltage controlled oscillator) and adding the offset to a control signal of the VCO. SOLUTION: An input signal (a) at an input terminal 1 is given to an input terminal 3 of a phase comparator 2 and a frequency division signal (c) outputted from an output terminal 22 of a frequency divider 21 is given to an input terminal 4 of the phase comparator 2. The phase comparator 2 gives a phase error signal (b) of both signals to an input terminal 7 of a filter 6. The filter 6 applies filtering processing to the phase error signal (b) according to a coefficient (e) loaded from a terminal 8 to input the filter coefficient and a filter output signal (d) from its output terminal 9 is fed to an adder 10 and an input terminal 15 of a steady-state discrimination device 14. The steady-state discrimination device 14 discriminates the PLL operation whether or not it is in a locking state or in a steady-state based on the filter output signal (d) and provides a signal (f) to an offset calculation device 17. The offset calculation device 17 calculates the offset of the digital control signal (g) based on the signal (f) and provides an output of it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
In particular, it relates to a method of reducing a steady phase error of a PLL circuit.

[0002]

2. Description of the Related Art When a clock signal synchronized with an input signal is generated, a phase locked loop (Phase Locked Loo
p; "PLL") circuit is used. This PLL
In the circuit, voltage controlled oscillator (Voltage Controlled)
A steady phase error occurs because the control voltage of the oscillator (called "VCO") is generated from the phase error between the input signal and the VCO output signal.

In order to reduce the steady phase error, it is sufficient to increase the loop gain, but in this case, there is a problem that stability in the steady state is deteriorated.

FIG. 5 is a block diagram for explaining a conventional stationary phase error reducing method. In this conventional method, the phase comparator 41, the filter 43, the VCO 46, and the frequency divider 44 form a feedback loop, and
An integrator circuit 42 for integrating the phase error signal is provided between the phase comparator 41 and the output end of the filter 43, and a second feedback signal for integrating the phase error is added to the output of the filter 43 to obtain a steady phase error. Is intended to be reduced.

In the steady state, the input signal (x) of the VCO 46 falls to a steady state and becomes a constant. This signal (x) is the same as the output signal (v) of the integrating circuit 42 and the phase comparator.
The steady phase error is given by the signal (v) because it is given by the sum (output of the adder 45) of the output signal (w) obtained by processing the phase error signal (u) which is the output of 41 by the filter 43. It is reduced by the size.

However, in this method, when the time constant of the integrating circuit 42 is small, the phase error signal (u) is reduced and the signal (w) remains small for a certain period of time.
Output signal (v) also becomes smaller, resulting in signal (w)
Needs to be large, which is achieved by increasing the phase error signal (u). When the phase error signal (u) continues to increase for a certain period, the output signal (v) of the integrating circuit 42 also increases and the phase error signal (u) gradually decreases.

The above-mentioned state is constantly repeated, and as a result, the oscillation of the steady phase error occurs. If the time constant of the integrating circuit is increased in order to suppress this vibration, the operation in the pulling process becomes slow and the PLL circuit has poor response characteristics.

FIG. 6 is a PLL circuit proposed in Japanese Patent Application Laid-Open No. 60-182820, which eliminates a stationary phase error and improves the response characteristic to a discontinuous signal input.
It is a block diagram which shows the structure of the system which reduces a stationary phase error.

Input signal (α) and reference crystal oscillator
Based on the comparison signal (ε) by the frequency comparator 50 with the output signal (β) of 49, the ROM (read only memory) 52 is converted into the signal (ζ), and the digital / analog converter (“D
/ A converter ”) 53 generates an analog signal (θ) to reduce the stationary phase error.

In order to optimize the ROM 52, it is necessary to create a table from the individual characteristics of the crystal oscillator 49 and VCO 57.

[0011]

As described above, as shown in FIG.
The conventional method shown in (1) has a problem that an oscillation phenomenon appears in the steady phase error or the pull-in response characteristic is slow due to the time constant of the integrating circuit.

Further, in the method shown in FIG. 6, in order to optimize the characteristics, it is necessary to create ROM data from the individual characteristics of the crystal oscillator and VCO.

Therefore, the present invention has been made in view of the above circumstances, and an object thereof is not to depend on the characteristics of the VCO and to cause the oscillation phenomenon of the steady phase error without causing the steady phase error. It is to provide a PLL circuit which has excellent transient response characteristics and good steady-state characteristics.

[0014]

In order to achieve the above object, the present invention provides a phase comparator for performing phase comparison between an input signal and a frequency-divided signal as a method for reducing a stationary phase error, and A filter that performs a filtering process on the output signal of the phase comparator, a coefficient setting device that sets a filter coefficient in the filter, and it is determined from the output signal of the filter whether the PLL operation is a pull-in process state or a steady state. A stationary determination device, an adder that adds the output signal of the filter and an offset value, an offset calculator that calculates an offset value from the output signal of the adder, and a digital / analog conversion of the output signal of the adder. D /
An A converter, a voltage controlled oscillator (VCO) that operates using the output signal of the D / A converter as a control signal, and the VCO
And a frequency divider that generates a frequency-divided signal by frequency-dividing the output signal of 1.

According to the present invention, the steady phase error is reduced by calculating the offset value of the signal input to the VCO and then adding it to the control signal of the VCO.
Further, the filter coefficient for filtering the phase error signal is switched between the pulling state and the steady state to improve the transient response characteristic and the steady characteristic.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

Referring to FIG. 1, the input signal (a) input from the input terminal 1 is input to one input terminal 3 of the phase comparator 2. The frequency-divided signal (c) output from the output terminal 22 of the frequency divider 21 is input to the other input terminal 4 of the phase comparator 2. The phase comparator 2 has an input signal (a) and a divided signal (c).
And the phase error signal (b) is supplied from the output end 5 to the input end 7 of the filter 6.

The filter 6 filters the phase error signal (b) according to the filter coefficient (e) loaded from the input terminal 8 which is a terminal for inputting a filter coefficient, and outputs from the output terminal 9 the filter output signal ( d) adder
10 and the input terminal 15 of the steady state determiner 14.

The adder 10 performs an addition operation on the filter output signal (d) and the offset value (h), and outputs the addition result digital control signal (g) to a digital / analog converter ("D / A converter"). ”) 24 and an input terminal 19 of the offset calculator 17.

The D / A converter 24 performs D / A conversion of the digital control signal (g) and supplies the analog control signal (i) from the output end 26 to the input end 28 of the VCO 27.

The VCO 27 oscillates at a frequency according to the analog control signal (i) and supplies the clock signal (j) from the output terminal 29 to the output terminal 30 and the input terminal 23 of the frequency divider 21.

The frequency divider 21 frequency-divides the clock signal (j) and supplies the frequency-divided signal (c) from the output end 22 to the input end 4 of the phase comparator 2.

The coefficient setter 11 selects the filter coefficient (e) based on the steady state determination signal (f) input from the input terminal 13 and supplies it from the output terminal 12 to the input terminal 8 of the filter 6.

The steady-state judging device 14 judges from the filter output signal (d) inputted from the input terminal 15 whether the PLL operation is in the pull-in process state or the steady state, and the steady-state judging signal (f). Is supplied to the input terminal 13 of the coefficient setter 11 and the input terminal 20 of the offset calculator 17.

The offset calculator 17 calculates the offset value of the digital control signal (g) when the steady state is settled based on the input steady judgment signal (f), and the offset value (h) is sent to the adder 10. Supply.

FIG. 2 is a block diagram showing an example of the configuration of the offset calculator 17. Referring to FIG. 2, the digital control signal (g) input from the input terminal 19 is supplied to the adder 59 and the delay device 31-1.

The delay device 31-1 has a digital control signal (g).
The delay signal (g1) is supplied to the adder 59 and the delay unit 31-2 at the next stage. This is repeated N stages, and the delay unit 31-N supplies the delay signal (gN) to the adder 59.

The adder 59 receives the input N + 1 signals,
That is, the digital control signal (g) and the delayed signal (g
1), the delayed signal (g2), ..., The delayed signal (gN) are added, and the added signal (k) is supplied to the divider 32.

The divider 32 divides the addition signal (k) by N + 1 and supplies the average value (l) to the selector 33. The selector 33 selects the average value (l) in the steady state using the steady determination signal (f) input from the input terminal 20 as a selection control signal, and the value “m” in the pulling process state. 0 "is selected to output the output signal (h) to the output terminal 18.

FIG. 3 is a block diagram showing an example of the configuration of the steady state determiner 14. Referring to FIG. 3, the filter output signal (d) input from the input terminal 15 is supplied to the subtractor 35 and the delay device 34. The delay device 34 delays the filter output signal (d) and supplies the delay signal (m) to the subtractor 35.

The subtractor 35 subtracts the smaller value from the larger value of the filter output signal (d) and the delay signal (m),
The subtraction signal (o) is supplied to the comparator 36.

The comparator 36 receives the subtraction signal (o) and "Th".
Is compared with a preset threshold value (p) indicated by, and when the subtraction signal (o) is equal to or greater than the threshold value (p), the pull-in process state is set; (F) is output to the output terminal 16.

FIG. 4 is a block diagram showing an example of the configuration of the coefficient setting unit 11. Referring to FIG. 4, in the selector 39, the steady determination signal (f) input from the input terminal 13 is used as a selection control signal to read the coefficient for the pull-in process state from the ROM 37 in the pull-in process state, and in the steady state. , The steady-state coefficient is read from the ROM 38 and the filter coefficient (e) is supplied to the output terminal 12.

[0034]

As described above, according to the present invention,
By calculating the offset value from the control signal given to the VCO, the steady phase error signal is reduced by a method with excellent versatility that does not cause the oscillation phenomenon of the steady phase error signal and does not depend on the characteristics of the VCO. Is possible. Further, according to the present invention, by switching the filter coefficient between the steady state and the pulling process state of the PLL, it is possible to realize a PLL circuit having excellent transient response characteristics and steady characteristics.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an offset calculator in one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a steady state determiner according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of an offset calculator according to an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional PLL circuit that reduces a stationary phase error.

FIG. 6 is a diagram showing a configuration of a conventional PLL circuit for improving response characteristics.

[Explanation of symbols]

1, 3, 4, 7, 8, 13, 15, 19, 20, 23, 25, 28 Input terminal 5, 9, 12, 16, 18, 22, 26, 29, 30 Output terminal 2 Phase comparator 6 Filter 10, 59 Adder 11 Coefficient setter 14 Steady-state judgment device 17 Offset calculator 21 Frequency divider 24 D / A converter 27 VCO 31-1, 31-2 to 31-N Delay device 32 Divider 33 Selector 34 Delay device 35 Subtractor 36 Comparator 37, 38 ROM 39 Selector

Claims (7)

[Claims] 1. A phase comparator for performing a phase comparison between an input signal and a frequency-divided signal, a filter for filtering an output signal of the phase comparator, and a coefficient setter for setting a filter coefficient in the filter. A steady state determiner that determines whether the PLL operation is a pull-in process state or a steady state from the output signal of the filter; an adder that adds the output signal of the filter and an offset value; and the adder , An offset calculator for calculating an offset value from the output signal, a D / A converter for digital / analog converting the output signal of the adder, and a voltage control for operating the output signal of the D / A converter as a control signal An oscillator (referred to as “VCO”) and a frequency divider that divides the output signal of the VCO to generate a divided signal are provided to reduce a stationary phase error. PL to
L circuit. 2. The offset calculator outputs an offset value when it is determined to be in a steady state based on a steady-state determination signal output from the steady-state determiner, and supplies the offset value to the adder. The PLL circuit according to claim 1, wherein: 3. The coefficient setting device sets predetermined filter coefficients in the filter according to a pull-in process state and a steady state based on a steady state determination signal output from the steady state determiner. The PLL according to claim 1.
circuit. 4. The offset calculator, when in a steady state,
2. The PLL circuit according to claim 1, wherein a predetermined number of time-series signals, which are output signals of the adder, are averaged and output as an offset value. 5. The steady state determiner compares a difference between an output signal of the filter and a delayed signal of the output signal of the filter with a predetermined threshold value to determine a pull-in process / steady state. The PLL circuit according to claim 1, which is characterized in that. 6. A phase comparator for comparing the phases of an input signal and a divided signal, a filter for filtering the output of the phase comparator, and a voltage control for inputting the output of the filter as a control voltage signal. In a control system of a phase locked loop circuit (PLL circuit) in which an oscillator (VCO) and a frequency divider that divides the output of the voltage controlled oscillator form a loop, control input to the voltage controlled oscillator The offset value is sequentially derived from the voltage signal, the offset value is added to the output of the filter and supplied as the control voltage signal of the voltage controlled oscillator, and the filter coefficient of the filter is changed according to the pull-in process state and the steady state. A steady phase error reduction method for a PLL circuit characterized in that it is variably set. 7. When the PLL operation settles into a steady state,
An offset value derived from a predetermined number of time series data of the control voltage signal input to the voltage controlled oscillator is added to the output of the filter, and in the pulling process state, the offset value is set to a predetermined fixed value. 7. The steady phase error reduction method for a PLL circuit according to claim 6, wherein.