JPH09200057A - Coded information processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize excellent quantized noise for all frequency bands by preventing increase in a high frequency noise level in the case of noise shaping processing. SOLUTION: Coded information of a PCM digital audio signal or the like received from an input terminal 1 is fed to a noise shaping circuit 2 and an HPF 4, a high frequency component of the signal processed by the noise shaping circuit 2 is eliminated by an LPF 3 and the low frequency signal and the high frequency signal whose low frequency component is eliminated by the HPF 4 and whose bit number is increased by a bit number conversion section 7 are added by an adder 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code information processing apparatus for reducing quantization noise in a low region by performing noise shaping processing on code information such as a PCM digital audio signal. The present invention relates to a code information processing device suitable for increasing the resolution to about a bit.

[0002]

2. Description of the Related Art Noise shaping refers to, for example, Japanese Patent Laid-Open No. 4-72906 and Japanese Patent Laid-Open No. 7-15281, in which the amplitude-frequency characteristic of quantization noise of a digital signal is modified according to the auditory sensitivity characteristic. However, this is a method of reducing noise in the middle and low frequencies where the sensitivity is good, and correspondingly increasing noise in the high range where the sensitivity is low, to reduce the noise perceptually. FIG. 27 shows each quantization noise when noise shaping is not performed and when noise shaping is performed. The quantization noise level of digital audio data (without noise shaping in the figure) is determined by the number of quantization bits, and the noise spectrum becomes uniform with respect to frequency. On the other hand, in the first-order noise shaping, the noise spectrum has a differential characteristic,
The noise level in the low frequency band is improved compared to that before the processing, but instead, the noise level in the high frequency band is increased. Further, this tendency becomes remarkable in the secondary noise shaping.

Therefore, in noise shaping, as the low frequency noise is reduced, the high frequency noise increases and the noise level cannot be lowered over the entire audible band.
In the conventional method, as shown in FIG. 28, 3 kHz to 4 kHz
Focusing on the fact that the sensitivity of the human ear is good at Hz and is poor at 15 kHz or higher, the noise level is sufficiently lowered in the region where the sensitivity of the human ear is good in order to make the quantization noise difficult to hear.

[0004]

By the way, it is said that human ears cannot hear high frequency components of 20 kHz or more. Based on this, the sampling frequency of digital audio equipment is set to 44.1 kHz for CD and 48 kHz for DAT, but some people can hear high frequency components of 20 kHz or more, and in recent years, It has been reported that components of music of 20 kHz or more activate α waves of brain waves and affect perception of sound quality. Especially,
It is said that the S / N difference in dynamic characteristics due to burst input appears in the sense of hearing.

Therefore, when a frequency band wider than the current CD and DAT is required, the noise level in the high frequency band increases in the conventional noise shaping, so that the S / N ratio deteriorates.

In view of the above-mentioned conventional problems, the present invention provides a code information processing apparatus capable of preventing an increase in noise level in a high frequency band and realizing good quantization noise in the entire band when performing noise shaping processing. The purpose is to provide.

[0007]

In order to achieve the above object, the present invention provides a low band in which quantization noise is reduced by noise shaping processing and a high band in which noise shaping processing is not performed and the number of bits is increased. Is to be synthesized. That is, according to the present invention, noise shaping means for performing noise shaping processing on code information to reduce quantization noise, and low-frequency band of the signals processed by the noise shaping means, in which the quantization noise is reduced by noise shaping processing. A low-pass filter that passes a band, a high-pass filter that passes a high band that the low-pass filter does not pass in the code information, and a bit number increasing means that increases the number of bits of a signal in a band that has passed the high-pass filter, There is provided a code information processing device having a synthesizing unit for synthesizing a signal in a band that has passed through the low-pass filter and a signal whose bit number has been increased by the bit number increasing unit. Further, the low-pass filter and the high-pass filter are first and second QMF division units that divide each input signal into sub-bands, respectively, and the synthesizing unit is one of the sub-bands divided by the first QMF division unit. A low-frequency subband in which quantization noise is reduced by noise shaping processing;
Among the sub-bands divided by the QMF dividing unit, the other high-frequency sub-band whose number of bits is increased by the bit number increasing means is combined. Further, the code information is an audio signal, and the noise shaping means has a frequency characteristic according to a hearing characteristic.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of a code information processing apparatus according to the present invention, and FIG.
2 is an equivalent circuit diagram for explaining the processing of the noise shaping circuit of FIG. 3, FIG. 3 is a graph showing the characteristics of the noise shaping circuit of FIGS. 1 and 2, and FIG. 4 is the characteristics of the low-pass filter and the high-pass filter of FIG. 6 is a graph showing the characteristics when the output signals of the bit number conversion unit are added.

In FIG. 1, code information such as a PCM digital audio signal input through the input terminal 1 is shown in FIG.
Is applied to a noise shaping circuit 2 and a high pass filter (HPF) 4 which are shown in detail in FIG. Then, the high frequency component of the signal processed by the noise shaping circuit 2 is removed by the low pass filter (LPF) 3, the low frequency component is removed by this low frequency signal and the HPF 4, and the number of bits is increased by the bit number converter 7. The high frequency signals are added by the adder 5 and output via the output terminal 6.

The noise shaping circuit 2 will be described with reference to FIGS. 2 and 3. Noise shaping circuit 2
Is the spectrum e (ω) of the quantization noise e (where ω is the angular frequency) that is transformed according to the auditory characteristics to reduce the noise in the middle and low frequencies where the ear is sensitive, and the noise in the high range where the sensitivity is poor. Is configured to increase the
As shown in FIG. 2, the subtractor 111, the adder 112, the quantizer 113, the subtractor 114, and the feedback filter 1
It can be represented by an equivalent circuit consisting of 15.

Referring to FIG. 2, first, the dither will be described. Generally, when the signal level is low, the quantized waveform has a rectangular wave shape, and the distortion of the quantized harmonic component of the signal occurs in the spectrum. Therefore, in order to prevent this, after adding subtle dither noise to the signal (adder 11
By quantizing (quantizer 113) to 2), the quantization noise e can be corrected to a flat spectrum. Furthermore, since the stepwise nonlinear quantization characteristic is linearized by adding dither, it is possible to generate a signal having an amplitude smaller than the quantization step width. Although the noise increases by the amount of dither, the dither can be subtracted by using self-dither that generates dither from the digital audio data sequence itself on the reproducing side.

The quantization noise e including dither is filtered by the filter H.
When feedback is given to the subtractor 111 through (z),
Quantization noise spectrum after shaping e '(ω)
Becomes e ′ (ω) = [1−H (ω)] e (ω). Since the spectrum e (ω) of the quantization noise e is flat if an appropriate dither is added, the spectrum e ′ (ω) of the quantization noise after shaping is obtained.
Is weighted by | 1-H (ω) |.

Therefore, the desired shaping characteristic | 1
Feedback filter H based on −H (ω) |
(Z) can be designed. Further, the characteristic H (ω) can be variably controlled by an adaptive filter (variable filter). FIG. 3 shows, as an example, a shaping characteristic matched with a minimum audible threshold characteristic by using a 32-tap FIR (finite length impulse response) filter. The quantization noise is most strongly reduced in a band of about 15 kHz or less and at about 4 kHz. However, it is increasing in the band of approximately 15 kHz or higher.

Therefore, as shown in FIG. 4A, the low-pass filter (LPF) 3 has a characteristic of passing a band of about 15 kHz or less of the signal processed by the noise shaping circuit 2 and cutting a band of about 15 kHz or more. Have
On the other hand, the high-pass filter (HPF) 4 is conversely about 15 kHz.
It has a characteristic of passing a band of z or more and cutting a band of approximately 15 kHz or less. Therefore, as shown in FIG. 4B, the quantization noise of the signal obtained by synthesizing the low frequency signal that has passed through the LPF 3 and the high frequency signal whose number of bits has increased by the number of bits conversion unit 7 decreases in the entire band. Can be made.

FIG. 5 shows a modification in which the embedded data channel is used to prevent noise increase due to the addition of dither in the noise shaping circuit 2. This circuit can be equivalently represented by subtractors 111, 112a, 16-b bit quantizer 113a, subtractor 114, feedback filter 115, randomizer 116, and adder 117. As described above, since it is possible to reduce the quantized noise on the auditory sense by the noise shaping, the low-frequency signal is quantized by 16-b bits, and the lower b
The ADPCM-encoded high frequency signal is embedded in the bits as additional data (adder 117).

In this case, the additional data is randomized (randomizer 116) and used as dither, and 16-b
Subtract from the signal in front of the bit quantizer 113a (subtractor 1
12a) and the same dither is added to the quantized data (adder 117) to cancel the dither component. Therefore, when the encoded 16-bit data is reproduced, a low-frequency signal that is noise-shaping and quantized with 16-b bits is obtained. Further, since the lower-order b bits of the 16-bit data are dithers, this is taken out and reverse randomized. Then, additional data can be obtained.
Such techniques are described, for example, in M.M. A. Gerzon and
P. G. FIG. Craven, “A High Rate
Buried Data Channel for A
audioCD, "(High-Rate Bellied Data Channel for Audio CDs) 94th AES Convention, Berlin Convention 1993 Spring.

FIG. 6 shows QMF as LPF3 and HPF4.
(Quadrature Mirror Filter) Using the dividing units 3a and 4a, the QMF combining unit 5 is used as the adder 5.
An example using a is shown. The QMF dividers 3a and 4a divide the input signal into n subbands, and the QMF combiner 5
a combines the low-frequency subband divided by the QMF dividing unit 3a and the high-frequency subband divided by the QMF4a dividing unit and having the increased number of bits by the bit number conversion unit 7.

FIG. 7A shows the noise level of the signal synthesized by the QMF synthesizer 5a, and FIG. 7B shows the subband. FIG. 7 shows DC to 24 kHz as an example.
The band of is divided into 12 sub-bands in units of 2 kHz,
A case is shown in which a sub-band of 14 kHz or less divided by the QMF dividing unit 3a and a sub-band of 14 kHz or more in which the number of bits is increased by the bit number converting unit 7 by being divided by the QMF dividing unit 4a are combined, and all the quantization noise is It can be reduced in bandwidth. The number of subbands M = 1
2 is an example and may be divided into another number, for example, 24.

Next, the bit conversion section 7 will be described in detail with reference to FIGS. The bit conversion unit 7 shown in FIG. 8 indicates one sub-band, and the delay circuit 103, the addition circuit 104, the signal waveform change mode detection unit 105 shown in detail in FIG. 9, and (K- N) It is composed of a bit signal generator 106, a variable delay unit 107 and a delay signal generator 108, and increases N bits to K bits. For example, N is 16, K is 20, and (K-N) is 4
It is. Detection unit 105 of signal waveform change mode shown in FIG.
Is generally composed of a signal waveform change information generation unit 51, a signal waveform change mode information generation unit 52, and a signal waveform change interval information generation unit 53.

The signal waveform change information generation unit 51 has a D-type flip-flop (DFF) 9, a magnitude comparator 10, an exclusive OR circuit 11 and an AND circuit 12, and a signal waveform change mode information generation unit 52. Is DFF13
15 to 15 and exclusive OR circuits 16 and 17. The generation unit 53 of the interval information of the signal waveform change uses the address counter 18
, DFFs 19 to 21, subtractors 22 and 23, and comparator 2
4 The (KN) bit signal generator 106 is shown in FIG.
0 in detail, the waveform data generator 4 in the extreme value section
8 and a calculation unit 4 for calculating N bits of 1 LSB / Ns
9, an inverter 56, a waveform data generator 54 other than the extreme value section, selectors 57 and 58, a control circuit 55 and an O.
It has an R circuit 59.

Next, the configuration and operating principle of the bit number converting section 7 will be described in detail with reference to FIGS. 13 to 17 and 21 to 24. In FIG. 13, points a to n are a → b → c →
A curve S that is connected by a thick line like d → e → f → g → h → i → j → k → l → m → n has a predetermined sampling period Ts (= reciprocal of sampling frequency fs) of the analog signal. The original analog signal which shows the state of the change of the digital value when sampled and quantized at a resolution of 1 / N of 2 for each, that is, a resolution of 1 LSB of N bits, and which generates the digital value indicated by the curve S is , Exists in the region surrounding the curve S as shown by the broken line in the figure. Note that the timings t1, t2, t3 in FIG.
Indicates the sampling time points for each sampling period Ts.

Here, between the analog signal used to obtain the N-bit code information obtained by conversion into a digital signal and the analog signal obtained by restoring the N-bit code information, There is an error of ± 0.5 LSB with respect to 1 LSB having a resolution of 1 / N of 2. This point is N
The bit code information is converted into N bit code information of a plurality of subbands by the QMF dividing units 3a and 4a (band division N bit code information in a substantially decimated state).
The same applies to the analog signal obtained by reconstructing and the analog signal in the individual frequency band corresponding to the frequency band to which the N-bit code information of the individual subband described above belongs. In the following description, “bandwidth N
The "bit code information" and the "subband N bit code information" may be simply described as "N bit code information".

The bit number conversion unit 7 performs bit number conversion on N-bit code information obtained by quantizing the analog signal with a resolution of 1 / N of 2 to obtain K-bit code information having a relationship of K> N. In order to obtain, when the value of the “N-bit code information” changes in a sequential increasing trend or a decreasing trend on the time axis, the N-bit code information of each sampling cycle Ts is changed. 2 for the length (number of sampling periods Ts) of the period (section) in which the values are the same and for the value of the N-bit code information in the period adjacent to the period.
The N-bit code information that differs by a resolution LSB of 1 / N is compared with the length of a period (section) continued as N-bit code information for each sampling period Ts.

When the period lengths of the two adjacent sections are different from each other, the midpoint of the section having the shorter period length of the two adjacent sections and the section having the longer period length of the two adjacent sections. The (K-N) -bit additional code information that can represent a straight line connecting the point of the position corresponding to 1/2 of the short period length from the boundary between the two sections at is generated.

When two adjacent sections have the same period length, a straight line connecting the midpoints of the two sections can be represented (K-N).
Generate bit additional code information. Then, the additional code information is continued to the least significant digit of the N-bit code information to generate K-bit code information. Further, when the value of the N-bit code information described above is the N-bit code information in the section corresponding to the extreme value, it is predetermined according to the period length of the section (K−N ) Bit additional code information is continued to the least significant digit of N-bit code information and K
Generate bit sign information.

In FIGS. 14A and 21A, (K−N) -bit additional code information is made continuous with respect to the least significant digit of N-bit code information to generate K-bit code information. A case where the curve Sn on a staircase shown by a thick solid line is the time of N-bit code information when an analog signal is converted into a digital signal with a resolution of 1 / N of 2 It shows the change on the axis. Further, the curve S (k−n) on the stairs shown by the thin solid line and the curve S shown in FIG.
(K−n) indicates the change on the time axis of the (K−N) -bit additional code information obtained as described above.

In FIGS. 14 (a) and 21 (a),
A curve Sn indicated by the points a → b → c → d → e → f shows a change on the time axis of N-bit code information, and the bit number conversion unit 7
Then, when the value of the N-bit code information shows a tendency to increase or decrease sequentially on the time axis, a period in which the value of the N-bit code information for each sampling period Ts continues in the same state. Length of (section) (for example, point a → b, point c →
The period length of the section indicated by d etc.) is
When each of the two sections has the same section length as compared with each other, the additional code information of (K−N) bits shown as a straight line connecting the midpoints of the sections in the two sections is compared. generate. For example, in FIG. 14A and FIG. 21A, a section a → b having the same period length.
And the section c → d, the two sections are shown as a straight line connecting the midpoint h of the section a → b and the midpoint i of the section c → d (K−
N) bits of additional code information are generated.

Next, when the value of the N-bit code information has a tendency to increase or decrease sequentially on the time axis, the value of the N-bit code information for each sampling period Ts is the same. The length of the period (section) that continued in the state (for example, point a
→ b, the period length of the section indicated by points c → d, etc.)
When two adjacent period lengths are different from each other in comparison with each other, the midpoint of the shorter period length and the boundary between the two periods in the longer period length (K-N) -bit additional code information shown as a straight line connecting points at positions corresponding to ½ of the short period length is generated.

For example, in the case of sections c → d and e → f shown in FIGS. 14 (a) and 21 (a), in the midpoint i of the short section c → d and the section e → f of a long period length. Two sections c
→ d, e → f 1 / the length of the short section c → d from the boundary d
It is shown as a straight line connecting the positions 1 corresponding to 2 (K-
N) Generate additional code information of bits.

Further, when the period during which the value of the N-bit code information for each sampling period Ts is the same is the extreme value section, it is set in advance corresponding to the period length of the section ( K
-K) N-bit additional code information is generated by continuing to the least significant digit of the N-bit code information to generate K-bit code information. The extreme value section is, for example, FIG.
It is shown in FIGS. 17 and 22 to 24. FIG. 14 (b)
Shows how (K−N) -bit additional code information is set for the extreme value section, and shows the case where the N-bit code information section is Ts and 3Ts as an example.

In FIG. 14B, when the period length of the extreme value section is Ts, the (K−N) -bit additional code information in the period Ts is the point o → p → q → r of the period Ts. The area is set to have the same size as the rectangular area surrounded by, that is, an area indicated by diagonal lines. In the case of 3Ts, the (K−N) -bit additional code information in the period 3Ts has the same size as the rectangular region surrounded by the points s → u → v → z in the period 3Ts, that is, as a shaded region. Is set.

As described above, the N-bit code information is originally ± 0.5 with respect to the N-bit resolution LSB.
Since the error of the LSB is included, the point o → in FIG.
A rectangular area surrounded by p → q → r, points s → u → v → z
For a rectangular area surrounded by, rectangles with different heights in the range of ± 0.5 LSB o → p ′ → q ′ → r or o →
p "→ q" → r, s → u '→ v' → z or s → u "→
You may set like v ″-> z.

In FIG. 15, the extreme value intervals are Ts, 2Ts and 3T.
s, 4Ts, 5Ts, 6Ts, 7Ts, 8Ts, 9Ts
In this case, the additional code information of each (K-N) bit is shown. Further, FIG. 16 shows that the extreme value sections are 10Ts, 11Ts,
In the case of 12Ts, 13Ts, and 14Ts, FIG. 17 shows the additional code information of each (K−N) bit in the case where the extreme value sections are 15Ts and 16Ts. Similarly, in FIG. 22, when the extreme value section is Ts to 6Ts, in FIG. 23, the extreme value section is 7T.
In the case of s to 13 Ts, FIG.
The additional code information of each (K-N) bit in the case of 16 Ts is shown. Such (K-N) -bit additional code information is used as the “extreme-value section waveform data generator” 4 shown in FIG.
It is stored in advance in the ROM within 8 and is output when the section length of the extreme value is applied as an address.

The input terminal 6 of the bit number converter 7 shown in FIG.
The N-bit code information of the subband applied to 0 is applied to the delay circuit 103 and the “signal waveform change mode detection unit” 105. The N-bit code information applied to the delay circuit 103 is delayed by a fixed time according to the processing time of the circuits 105 to 108, and then the addition circuit 104 adds (K−N) bits from the variable delay unit 107. The sign information is added to the sign information, and K-bit sign information is output via the output terminal 61.

The N-bit code information applied to the "signal waveform change mode detecting section" 105 is the signal waveform change mode information and the interval for the N-bit digital signal of the sub-band by the circuit shown in detail in FIG. Is detected, (K-
N) Bit signal generator 106 and delay control signal generator 10
8 is applied.

In the (K−N) bit signal generator 106,
When the N-bit code information of the sub-band changes in a sequential increasing trend or a decreasing trend on the time axis, the value of the N-bit code information for each sampling period Ts is the same. The length (number of sampling periods Ts) of the periods (sections) continued in Step 2 is compared for adjacent sections. If the period lengths of two adjacent sections are different from each other, the two adjacent sections are compared. A (K-N) -bit line that represents the straight line connecting the middle point of the section with the shorter period length and the position corresponding to 1/2 of the shorter period length from the boundary of the two sections with the longer period length. The additional code information is generated and output to the variable delay unit 107.

When the period lengths of two adjacent sections are the same, (K-N) -bit additional code information representing a straight line connecting the midpoints of the two sections is generated and the variable delay unit is generated. When the sub-band N-bit code information is present in the extreme value section, the addition of (K−N) bits is performed from the ROM in the extreme value section waveform data generating unit 48 shown in FIG. The code information is read and output to the variable delay unit 107.

The variable delay unit 107 delays the (K−N) -bit additional code information and applies it to the adder circuit 104. This delay amount is calculated by the delay control signal generator 108.
It is determined based on the signal waveform change information, the signal waveform change mode information, and the signal waveform change interval information detected by the “signal waveform change mode detection unit” 105. Adder circuit 104
Then, N of the sub-band delayed by the delay circuit 103
Band-divided (K−N) -bit additional code information is added to the least significant digit of the bit code information to generate band-divided K-bit code information.

Next, the "signal waveform change mode detecting section" 105 shown in FIG. 9 will be described in detail. Detection unit 105
Sub-band N-bit code information is applied to the input terminal 25 of the clock signal pulse Pfs
Is applied. The clock signal pulse Pfs is a pulse having the same frequency as the sampling frequency fs, and when the signal to be processed is an audio signal, for example, 48 kHz or 88.
2 kHz is used.

N of the sub-band applied to the input terminal 25
The sign information of the bit is the magnitude comparator 1
It is applied to the input terminal A of 0 and the data terminal D of the DFF 9. The clock signal signal pulse Pfs is applied to the clock terminal CK of the DFF 9, and the output signal of the Q terminal of the DFF 9 is applied to the input terminal B of the magnitude comparator 10. DFF9 is a clock signal signal pulse P
Every time fs is input, N-bit code information of the subband one sampling period Ts before is output to the input terminal B of the magnitude comparator 10.

The magnitude comparator 10 has three output terminals (A> B), (A = B), (A <B), and when the input signal is A> B, the output terminal (A> B). Only H (high level) and other output terminals (A = B),
(A <B) is set to L (low level). When the input signal is A = B, only the output terminal (A = B) is set to H and the others are set to L, and when the input signal is A <B, the output terminal (A
Only <B) is H and the other are L. It should be noted that such a magnitude comparator 10 is, for example, 74
HC85 can be used.

The exclusive OR circuit 11 has two output terminals (A> B) and (A> A) of the magnitude comparator 10.
Each output signal of <B) is applied, and the output terminal (A>)
The signal of B) is D in the signal waveform change mode information generation unit 52.
It is applied to the data terminal D and the output terminal 35 of the FF 13.
The exclusive OR circuit 11 has output terminals (A> B), (A <B
When only one of the output signals of B) is H, the H signal is output. Here, since the output signals of the output terminals (A> B) and (A <B) cannot be at H at the same time, an OR circuit may be used instead of the exclusive OR circuit 11.

The AND circuit 12 includes an exclusive OR circuit 11
When the inverted signal (Pfs bar signal) of the clock signal pulse Pfs is applied as the gate pulse and the AND circuit 12 is shifted by one sampling period Ts and the value of each adjacent digital data is different. To P
The clock signal CLK is output at the timing of the fs bar signal. The clock signal CLK is supplied to each clock terminal C of the DFFs 13 to 15 in the signal waveform change mode information generating section 52.
K and the DFF in the generator 53 of the interval information of the signal waveform change
It is applied to each clock terminal CK of 19 to 21 and the output terminal 33.

The clock signal CLK will be described with reference to FIG. In FIG. 11, symbols a, b, and h-o are analog representations of how the signal level of the N-bit code information of the subband applied to the input terminal 25 changes, and Pfs
1, Pfs2 to Pfs19 are clock signal pulses Pfs
Shows the timing of Pfs1 bar, Pfs2 bar ~ P
The fs19 bar indicates the timing of the Pfs bar signal applied to the AND circuit 12.

When the signal level of the N-bit code information of the sub-band changes as shown by codes a, b, and h-o, the digital data of the signal level "a" is output at the timing of the clock signal pulse Pfs1. It is applied to the input terminal A of the magnitude comparator 10 and the data terminal D of the DFF 9. In this case, since the digital data applied to the input terminal B of the magnitude comparator 10 is indefinite "?", The magnitude comparator 10
The output of is also indeterminate "?".

Next, the clock signal pulse P after one sampling period Ps from the timing of the clock signal pulse Pfs1
At the timing of fs2, the signal level "b"(>
Since the digital data "a") is applied to the input terminal A of the magnitude comparator 10 and the signal level "a" is applied to the input terminal B, the output terminal (A>
Only B) becomes H. Therefore, the output terminal (A> B)
Is H when the digital data is increasing (indicated as (>, U) in the figure). When the output terminal (A> B) of the magnitude comparator 10 becomes H at the timing of the clock signal pulse Pfs2, the output signal of the exclusive OR circuit 11 becomes H, and the AND circuit 12 becomes the gate pulse (P> P).
fs2 bar) at the timing when the clock signal C is applied
Output LK2.

At the next timing of the clock signal pulse Pfs3, since the digital data of the same signal level "b" is applied to the input terminals A and B of the magnitude comparator 10, only the output terminal (A = B) becomes H, As a result, the output signal of the exclusive OR circuit 11 becomes L at the timing of the clock signal pulse Pfs2, and as a result, the output signal of the AND circuit 12 does not output the clock signal CLK even when the gate pulse (Pfs3 bar) is applied. .

At the next timing of the clock signal pulse Pfs4, the digital data of the signal level “C” (> “B”) is input to the input terminal A of the magnitude comparator 10.
Since the signal level "b" is applied to the input terminal B as well as being applied to the input terminal B, only the output terminal (A> B) becomes H,
The output signal of the exclusive OR circuit 11 becomes H, and the AND circuit 12 outputs the clock signal CLK3 at the timing when the gate pulse (Pfs4 bar) is applied.

At the next timing of the clock signal pulse Pfs5, since the digital data of the same signal level "C" is applied to the input terminals A and B of the magnitude comparator 10, only the output terminal (A = B) becomes H, As a result, the output signal of the exclusive OR circuit 11 becomes L at the timing of the clock signal pulse Pfs5, and as a result, the output signal of the AND circuit 12 does not output the clock signal CLK even when the gate pulse (Pfs5 bar) is applied. .

At the next timing of the clock signal pulse Pfs6, the digital data of the signal level "d"(>"c") is input to the input terminal A of the magnitude comparator 10.
Since the signal level “C” is applied to the input terminal B while being applied to the input terminal B, only the output terminal (A> B) becomes H,
The output signal of the exclusive OR circuit 11 becomes H, and the AND circuit 12 outputs the clock signal CLK4 at the timing when the gate pulse (Pfs6 bar) is applied.

At the next timing of the clock signal pulse Pfs7, the digital data of the signal level "e"(<"d" is applied to the input terminal A of the magnitude comparator 10 and the signal level "d" is input to the input terminal B). Since it is applied, only the output terminal (A <B) becomes H. Therefore, the output terminal (A <B) becomes H when the digital data tends to decrease (indicated as (<, D) in the figure. ).
In this case, the output signal of the exclusive OR circuit 11 becomes H at the timing of the clock signal pulse Pfs7, and the AND circuit 12 outputs the clock signal CLK5 at the timing when the gate pulse (Pfs7 bar) is applied.

The following clock signal pulses Pfs8 to Pf
Since the operation at the timing of s19 is the same, the description thereof will be omitted, but as is clear from the above description, the timing of the clock signal pulse Pfsi (i = 1, 2, ...) Applied at each sampling cycle Ts. In, the output terminal (A> B) or (A <B) of the magnitude comparator 10 becomes H only when the N-bit digital data tends to increase or decrease. Then, the AND circuit 12 outputs the clock signal CLKi (i = 1, 2 ...)
Similarly, is output only when the N-bit digital data tends to increase or decrease.

D in the signal waveform change mode information generating section 52
Each of the FFs 13 to 15 outputs data from the data terminal D (A above) every time the clock signal CLK is applied to each clock terminal CK.
> B), and the DFFs 19 to 21 in the signal waveform change interval information generation unit 53 have the clock terminals CK.
The data of the data terminal D (the output data of the address counter 18) is read every time the clock signal CLK is applied to. Here, the magnitude comparator 10 at the timing of the clock signal CLKi (i = 1, 2 ...)
Whether the output signal (A> B) of H is in the H state or the L state, the N-bit digital data at the timing of the clock signal CLKi (i = 1, 2 to) tends to increase or decrease on the time axis. Output signal (A
> B) is in the H state when increasing, and is in the L state when decreasing.

Referring to FIG. 11 and FIG. 12,
The N-bit digital data at the timing of the clock signal CLKi (i = 1, 2 ...) Has an increasing tendency on the time axis, and the clock signal pulse Pfsi (i = 1, 2, 1).
At the timings (a) to (b), the H signal (A> B) is taken in by the DFF 13 in the signal waveform change mode information generating section 52, as shown in FIGS. 11 and 12, when the number i of the clock signal CLKi is 2. ~ 4, 12-14, 1
It is each timing of 7, 18, 21-27.

Further, the digital data at the generation timing of the clock signal CLKi tends to decrease on the time axis, and the L signal (A> B) is generated at the timing of the clock signal pulse Pfsi (i = 1, 2 ...). As shown in FIGS. 11 and 12, the timing at which the signal waveform change mode information is fetched by the DFF 13 is 5-11, 15, 16, 19, when the number i of the clock signal CLKi is:
20 timings.

As described above, the signal (A> B) fetched by the DFFs 13 to 15 in the signal waveform change mode information generating section 52 for each clock signal CLKi is "DF" in FIG.
"F13 input", "DFF13 output", "DFF14"
Output ”and“ output of DFF15 ”.
It should be noted that "U" indicates the H state and "D" indicates the L state.

Referring to FIG. 9, "output of DFF 13"
And "output of DFF 14" are applied to the exclusive OR circuit 16, and "output of DFF 14" and "output of DFF 15" are applied to the exclusive OR circuit 17. Further, "output of exclusive OR circuit 16" and "output of exclusive OR circuit 17" are shown in FIG. 12, and in this case, "1" indicates an H state and "0" indicates an L state. There is. Further, in FIG. 12, "d", "ru", "ka", "ta", "so", and "ne" shown in the column of "extreme position of signal waveform" are
It corresponds to N-bit data to be processed.

Here, as shown in FIG.
Of the N-bit data of “e”, the N-bit data in the extreme value section is only “2” from the number i of the clock signal CLKi when the “output of the exclusive OR circuit 16” becomes “1”. DF by the clock signal CLKi with the smaller number i-2
It can be seen that it is taken into F13. Instead, the N-bit data in the extreme value section is clocked by the clock signal CL when the “output of the exclusive OR circuit 17” becomes “1”.
The clock signal CLKi of the number i-3, which is smaller than the number i of Ki by "3", may be taken into the DFF 13. As a result, the output signals of the exclusive OR circuits 16 and 17 are the (K-N) bit signal generator 10 shown in FIG.
6 and the "extreme position information" of the delay control signal generator 108 (output terminals 33, 3 in FIG. 9).
2).

In FIG. 9, the address counter 18 in the signal waveform change interval information generating section 53 has a sampling cycle T.
The clock signal pulse Pfs having s is counted and the address value is sequentially supplied to the data terminals of the DFFs 19 to 21. Therefore, the DFFs 19 to 21 sequentially read the output value (address value) of the address counter 18 for each clock signal CLKi applied to the clock terminal CK,
Therefore, the output value (address value) of the address counter 18 is DFF19 → DFF2 for each clock signal CLKi.
0 → transferred to the DFF 21. The output signals of the DFFs 19 to 21 are output via the output terminals 27, 30, and 31, respectively.
Are output to the (K-N) bit signal generator 106 and the delay control signal generator 108, and the output signals of the DFFs 19 and 20 are output to the subtractor 22 and the output signals of the DFFs 20 and 21 are output to the subtractor 23. Is applied.

Here, each output value N of the subtracters 22 and 23
1 and N2 are the difference between the address values between the adjacent clock signals CLK on the time axis, but as described above, the address counter 18 counts the clock signal pulse Pfs having the sampling period Ts, and therefore the output The value N1,
N2 represents how many times the sampling period Ts is the interval between adjacent clock signals CLK on the time axis. The output values N1 and N2 are applied to the comparator 24 and
The output terminals 28 and 36 are shown in FIG. 8 (K-
N) Bit signal generator 106 and delay control signal generator 10
8 is output. The comparator 24 compares the input values N1 and N2 and outputs the smaller value Ns to the (K−N) bit signal generator 106 and the delay control signal generator 108 shown in FIG. 8 via the output terminal 29.

[0061]

[Table 1] Next, the (KN) bit signal generator 106 will be described in detail with reference to FIG. First, the input terminals 37-
Signals from the output terminals 27 to 36 shown in FIG. 9 are applied to 46, and the corresponding relationship is output terminal 27 → input terminal 43 〃 28 → 〃 37 〃 29 → 〃 39 〃 30 → 〃 44 〃 31 → 〃 45. 〃 32 → 〃 46 〃 33 → 〃 38 〃 34 → 〃 41 〃 35 → 〃 40 〃 36 → 〃 42.

The waveform data generator 48 in the extreme value section is shown in FIG.
As described with reference to FIG. 4 (b) and FIGS. 15 to 17, an additional code of (K−N) bits that has the same area as the rectangle according to the period length of the extreme value section in the N-bit data. It has a ROM in which information is stored in advance. Then, the generator 48 uses the numerical value N1 input from the subtractor 22 of FIG. 9 via the input terminal 37 as an address, and the period of the extreme value section input from the exclusive OR circuit 16 of FIG. 9 via the input terminal 38. The (K-N) -bit additional code information corresponding to the above is output to the selector 57.

That is, when the signal indicating the extreme value section is "1", the numerical value N1 indicates how many times the sampling period Ts is used. As shown in FIGS. 15 to 17, the waveform data of a predetermined extreme value section is previously stored in the ROM for each period length of the extreme value section.
Can be stored in and read out from. For example, FIG. 18 (b)
Extreme value section N1 = Ts · k (k = 1, 2 ...)
18C, it is possible to generate (K-N) -bit additional code information as shown in FIG. 18C. Here, when the signal “1” indicating the extreme value section is applied to the selector 57, the additional code information of (K−N) bits is the selector 57, O.
It is applied to the variable delay unit 107 shown in FIG. 8 via the R circuit 59 and the output terminal 47.

The “arithmetic unit for performing N-bit 1LSB / Ns arithmetic” 49 compares the 1LSB value of N-bit data as the dividend within the “signal waveform change interval information generating unit” 53 shown in FIG. The sampling period Ts is defined by the numerical value Ns input from the output terminal 29 via the output terminal 29 through the output terminal 29, that is, the shorter period length of two adjacent sections (one period length when the period lengths are the same). Division is performed using the numerical value Ns expressed as a unit as a divisor. Then, the calculation unit 49
Supplies the calculation result (1 LSB / Ns) and the numerical value Ns to the “waveform data generator other than the extreme value section” 54.

"Waveform data generator other than the extreme value section" 54
Includes a magnitude comparator 10 shown in FIG.
Based on the signal (A> B) input from the output terminal 35 through the input terminal 40 (that is, “1” in the case of an increasing tendency and “0” in the case of a decreasing tendency), the N-bit data to be processed is the time. If there is an increasing or decreasing tendency on the axis,
When the length of a period in which N-bit data for each sampling period Ts continues with the same value is different between two adjacent sections, or is the same, and the two adjacent sections are extremal sections. 21A and FIG.
The (K-N) -bit additional code information as described in (1) is generated.

FIGS. 19 and 26 show the original band-divided N-bit code information waveform K1.fwdarw.K2.fwdarw.
K3 → K4 → K5 → K6 → K7 → K8 and its (K-
An example of (N) -bit waveform data is shown. In addition, 2
Even if the increase is LSB or more, since the increase for 1 LSB is extracted, it is the same as the increase for 1 LSB. In the example shown in FIGS. 19A and 26A, the section of the signal level “KU” has the period length of the numerical value N1, and the section of the signal level “YA” adjacent to this section has the period length of the numerical value N2. Therefore, there is a relationship of N1> N2. In this case, the numerical value supplied to the “waveform data generator other than the extreme value section” 54 is N2, and the numerical value N2 (Ns) is 16 (16 clock signal pulses Pfs in one sampling period Ts). ).

The boundary position β between the “KU” section and the “YA” section is indicated by the address value applied to the control circuit 55 from the DFF 19 and the output terminal 27 through the input terminal 43 shown in FIG. , Furthermore, the starting point position α of the section “K”
Is indicated by an address value applied to the control circuit 55 from the DFF 21, the output terminal 31 and the input terminal 45 shown in FIG. "Waveform data generator other than the extreme value section" 54
Is equipped with a memory, an arithmetic circuit, etc., and is centered on the boundary position β and has a position “0” of Ns / 2 in the section “K” to an N in the section “Y”.
Additional code information having the following values is generated for each of the positions "0" to "16" up to the position "16" of s / 2.

[0068]

[Table 2] First, the additional code information at the position "0" in the section "K" is set to "0". Position "1" in section "ku"
~ The additional code information of "7" is as follows. Position “1” = (1 LSB of N bits) / Ns (= N
2) Position “2” = 2 × (1 LSB of N bits) / Ns (= N
2) Position “3” = 3 × (1 LSB of N bits) / Ns (= N
2) Position “4” = 4 × (1 LSB of N bits) / Ns (= N
2) Position “5” = 5 × (1 LSB of N bits) / Ns (= N
2) Position “6” = 6 × (1 LSB of N bits) / Ns (= N
2) Position “7” = 7 × (1 LSB of N bits) / Ns (= N
2)

[0069]

[Table 3] Boundary position β (position "8") and positions "9" to "1"
The additional code information of "6" is as follows. Position “8” = 8 × (1 LSB of N bits) / Ns
(= N2) -N-bit 1 LSB position “9” = 9 × (N-bit 1 LSB) / Ns
(= N2) −1 LSB position of N bits “10” = 10 × (1 LSB of N bits) / Ns
(= N2) −1 LSB position of N bits “11” = 11 × (1 LSB of N bits) / Ns
(= N2) −1 LSB position of N bits “12” = 12 × (1 LSB of N bits) / Ns
(= N2) −1 LSB position of N bits “13” = 13 × (1 LSB of N bits) / Ns
(= N2) −1 LSB position of N bits “14” = 14 × (1 LSB of N bits) / Ns
(= N2) −1 LSB position of N bits “15” = 15 × (1 LSB of N bits) / Ns
(= N2) −1 LSB position of N bits “16” = 16 × (1 LSB of N bits) / Ns
(= N2) -one LSB of N bits

By performing the above calculation, the waveform K1 → K2 → K3 → K4 → K5 → K based on the original band-divided N-bit code information in the two adjacent sections “KU” and “YA”.
From 6 → K7 → K8, from position δ (= position K3, “0”) to position ε as shown in FIGS. 19B and 26C.
Additional code information up to (= position K7, "16") is generated.

Here, the above description is for the case where the signal of (A> B) = 1 is supplied, that is, the case of the increasing tendency, but the signal of (A> B) = 0 is supplied. The same applies to the case, that is, the case of a decreasing tendency.
In this case, in FIG. 19 (a) and FIG. 26 (a), the signal level in the section "K" is 1L from the section in the section "Y".
Assuming that it is lower by SB, centering on the boundary position β, the Ns / 2 position “0” of the section “K” to the Ns of the section “Ya”.
Additional code information having the following values is generated for each of the positions "0" to "16" up to the position "16" of / 2.

[0072]

[Table 4] Position “0” = 16 × (1 LSB of N bits) / Ns (=
N2) -N-bit 1 LSB position “1” = 15 × (N-bit 1 LSB) / Ns (=
N2) -N bit 1 LSB position "2" = 14 x (N bit 1 LSB) / Ns (=
N2) -N-bit 1 LSB position “3” = 13 × (N-bit 1 LSB) / Ns (=
N2) -N-bit 1 LSB position "4" = 12 * (N-bit 1 LSB) / Ns (=
N2) -N-bit 1 LSB position “5” = 11 × (N-bit 1 LSB) / Ns (=
N2) -N-bit 1 LSB position "6" = 10 × (N-bit 1 LSB) / Ns (=
N2) -N-bit 1 LSB position "7" = 9 x (N-bit 1 LSB) / Ns (=
N2) -1 LSB of N bits

[0073]

[Table 5] Boundary position β (position "8") and positions "9" to "1"
The additional code information of "6" is as follows. Position “8” = 8 × (1 LSB of N bits) / Ns (=
N2) Position “9” = 7 × (1 LSB of N bits) / Ns (=
N2) Position “10” = 6 × (1 LSB of N bits) / Ns (=
N2) Position “11” = 5 × (1 LSB of N bits) / Ns (=
N2) Position “12” = 4 × (1 LSB of N bits) / Ns (=
N2) Position “13” = 3 × (1 LSB of N bits) / Ns (=
N2) Position “14” = 2 × (1 LSB of N bits) / Ns (=
N2) Position “15” = 1 × (1 LSB of N bits) / Ns (=
N2) Position "16" = 0

“Waveform data generator other than the extreme value section” 54
Stores the (K-N) -bit additional code information that has been subjected to the above calculation in the memory, and then reads it from the memory under the control of the control circuit 55 and outputs it to the selector 58. And
A signal in the extreme value section input from the exclusive OR circuit 16 of FIG. 9 via the input terminal 38 is applied to the selector 58 as a selection signal via the inverter 56. The −N) bit additional code information is transmitted via the selector 58, the OR circuit 59 and the output terminal 47 to
Is applied to the variable delay unit 107 shown in FIG.

The variable delay unit 107 continuously adds the (K−N) -bit additional code information to the least significant digit of the N-bit code information delayed by the delay circuit 103 for a fixed time. Then, the data is delayed and output to the addition circuit 104. The variable delay unit 107 is composed of, for example, a RAM, and the write timing and the read timing are controlled by the delay control signal generating unit 108.

FIG. 20 shows the delay circuit 103 for the N-bit code information S of the subband applied to the input terminal 60.
Based on the coded information Sd delayed by a certain time by the above, and the coded information S, the “detection unit of the change mode of the signal waveform” 10
5 shows the addition timing of the (K-N) -bit code information Sa generated by the 5 and (K-N) -bit signal generation unit 106 and delayed by the variable delay unit 107. Note that FIG.
0 and the stepwise waveform Sa ′ shown in FIG.
As described with reference to FIGS. 20 and 26, when obtaining additional code information to be generated corresponding to one section from the boundary position of two adjacent sections, 1 LSB of N bits is used.
The calculated value of Sa before subtracting is shown.

Next, the operation of the delay control signal generator 108 for controlling such that the (K−N) -bit additional code information is continuously added to the least significant digit of the N-bit code information will be described. . For the delay control signal generator 108, the clock signal CLK from the output terminal 34, the address value Ns from the output terminal 29, and the boundary position from the output terminal 30 from the “signal waveform change mode detector” 105. The address value, the period length of the extreme value section from the output terminal 28, the information indicating the extreme value section from the output terminal 33, the address value of the start position of the section from the output terminal 31, the clock signal Pfs, etc. are applied. It The delay control signal generation unit 108 uses these pieces of information, and (K-N) -bit additional code information existing at a position separated by the sampling period Ts from the boundary position between two adjacent sections or the start position of the extreme value section. The delay time given to the variable delay unit 107 is calculated and applied to the variable delay unit 107.

[0078]

As described above, according to the present invention, the low band in which the quantization noise is reduced by the noise shaping process and the high band in which the noise shaping process is not performed and the number of bits is increased are combined. Therefore, when noise shaping processing is performed, it is possible to prevent an increase in the noise level in the high frequency band and realize good quantization noise in the entire band.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a code information processing device according to the present invention.

FIG. 2 is an equivalent circuit diagram for explaining processing of the noise shaping circuit of FIG.

FIG. 3 is a graph showing characteristics of the noise shaping circuit of FIGS. 1 and 2.

FIG. 4 is a graph showing the characteristics of the low-pass filter and the high-pass filter of FIG. 1 and the characteristics when the output signals of the low-pass filter and the bit number conversion unit are added.

FIG. 5 is an equivalent circuit diagram for explaining processing of a modified example of the noise shaping circuit of FIGS. 1 and 2.

FIG. 6 is a block diagram showing an embodiment of a code information processing apparatus of a second example.

FIG. 7 is a diagram showing a combination of a low-frequency side subband divided by the low-frequency side QMF division unit and a high-frequency side subband divided by the high-frequency side QMF division unit and having an increased number of bits by the bit number conversion unit of FIG. It is a graph which shows the characteristic at the time of doing.

FIG. 8 is a block diagram showing in detail the bit number conversion unit of FIG. 1.

FIG. 9 is a block diagram showing in detail a detection unit for detecting a variation of the signal waveform shown in FIG.

10 is a block diagram showing in detail a (KN) bit signal generator of FIG.

11 is a timing chart showing main signals of the bit number conversion unit of FIG.

12 is an explanatory diagram showing main signals of a bit number conversion unit in FIG.

FIG. 13 is an explanatory diagram showing a quantization error of N-bit digital data.

FIG. 14 shows (K− for digital data of N bits.
It is explanatory drawing (a) which shows the additional code information of N) bit, and explanatory drawing (b) which shows the additional code information of (KN) bit in the case where the area which has an extreme value is one sampling period.

FIG. 15 is an explanatory diagram showing (K−N) -bit additional code information in a case where a section having an extreme value has a sampling period of 1 to 9;

FIG. 16 is an explanatory diagram showing (K−N) -bit additional code information in a case where a section having an extreme value has a sampling period of 10 to 14;

FIG. 17 is an explanatory diagram showing (K−N) -bit additional code information in a case where a section having an extreme value has 15 and 16 sampling periods.

FIG. 18 is an explanatory diagram showing an area of N-bit digital data and (K−N) -bit additional code information in a section having an extreme value.

FIG. 19 is an explanatory diagram showing a method of calculating additional code information of (K−N) bits.

FIG. 20 is an explanatory diagram showing an addition timing of N-bit digital data and (K−N) -bit additional code information.

FIG. 21 shows (K− for digital data of N bits;
It is explanatory drawing which shows the additional code information of N) bit.

FIG. 22 is an explanatory diagram showing (K−N) -bit additional code information in a case where a section having an extreme value has a sampling period of 1 to 6;

FIG. 23 is an explanatory diagram showing (K−N) -bit additional code information in a case where a section having an extreme value has a sampling period of 7 to 13.

FIG. 24 is an explanatory diagram showing (K−N) -bit additional code information in a case where a section having an extreme value has 14 to 16 sampling periods.

FIG. 25 is an explanatory diagram showing areas of N-bit digital data and (K−N) -bit additional code information in a section having an extreme value.

FIG. 26 is an explanatory diagram showing a method of calculating additional code information of (K−N) bits.

FIG. 27 is a graph showing each quantization noise when noise shaping is not performed and when noise shaping is performed.

FIG. 28 is a graph showing an equal loudness curve of an audio signal.

[Explanation of symbols]

2 noise shaping circuit (noise shaping means) 3 low-pass filter (LPF) 4 high-pass filter (HPF) 5 adder (combining means) 3a, 4a QMF dividing section 5a QMF combining section 7 bit number converting section (bit number increasing means)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03H 17/02 641 9274-5J H03H 17/02 641N H03M 1/08 H03M 1/08 Z 7/30 9382-5K 7/30 A

Claims (3)

[Claims] 1. A noise shaping means for reducing quantization noise by subjecting code information to noise shaping processing, and a low-frequency band in which quantization noise is reduced by noise shaping processing among signals processed by the noise shaping means. A low-pass filter to pass, of the code information, a high-pass filter to pass a high band that the low-pass filter does not pass, a bit number increasing means to increase the number of bits of the signal of the band passed the high-pass filter, A code information processing device, comprising: a synthesizing unit that synthesizes a signal in a band that has passed through a low-pass filter and a signal having the number of bits increased by the number of bits increasing unit. 2. The low-pass filter and the high-pass filter each divides each input signal into sub-bands.
A second QMF division unit, wherein the synthesizing means includes a low-frequency subband of which the quantization noise is reduced by noise shaping processing among the subbands divided by the first QMF division unit; 2. The code information processing apparatus according to claim 1, wherein, out of the sub-bands divided by the QMF dividing unit, another high-frequency sub-band whose number of bits is increased by the bit number increasing means is combined. 3. The code information processing apparatus according to claim 1, wherein the code information is an audio signal, and the noise shaping means has a frequency characteristic according to a hearing characteristic.