JPH09200280A - Frequency offset compensator - Google Patents

Abstract

(57) Abstract: A frequency offset compensating device capable of reducing the power consumed for calculating a phase compensation value without degrading the accuracy of phase error compensation. SOLUTION: A phase compensating means 9 for compensating a phase error caused by a frequency offset of received data after detection by using a phase error compensating value, and a judging means 10 for making a quadrant judgment on an output of the phase compensating means, Phase error estimating means 4 for estimating a phase error from the correlation value between the received data after detection and the data after quadrant determination and outputting the phase error compensation value to the phase compensating means 4.
In the frequency offset compensating apparatus including :, the phase error estimating means calculates the correlation value S ′ · D between the conjugate complex data S ′ of the received data S after detection calculated by the phase error estimating means and the output D of the determining means, and The complex multiplication result | S | ² of the reception data S and its conjugate complex data S ′ is accumulated over N symbols, respectively, and the phase error compensation value Ψ ′ is calculated for every N symbols using these accumulated values. To do. Since the calculation of the phase error compensation value is performed once every N symbols instead of every symbol, power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency offset compensating apparatus used for a data receiving apparatus such as digital mobile communication, and more particularly to reducing power consumption for calculation.

[0002]

2. Description of the Related Art A data receiving device for digital mobile communication or the like demodulates a received signal into a baseband signal, converts it into a digital signal, and then judges the digital data at the time of symbol identification to reproduce the data. At this time, if there is a frequency error (frequency offset) between the carrier frequency of the received signal and the oscillation frequency of the reference oscillator of the receiving device used for demodulation or the like, an error occurs in the determination result. Therefore, the data receiving device is provided with a device for compensating for this frequency offset.

FIG. 5 shows an example of a π / 4 shift QP.
1 shows a frequency offset compensating device of a conventional TDMA data receiving device that receives an SK modulated wave.

This apparatus has an input terminal 81 to which an in-phase component X at the time of symbol identification of waveform-shaped baseband waveform data is applied, and an orthogonal component Y of the waveform-shaped baseband waveform data at the time of symbol identification. Of the waveform data X and Y applied to the input terminals 81 and 82 and the in-phase component of the cosine and sine of the modulation phase difference of the received π / 4 shift QPSK modulated wave signal, respectively. I, the phase error is estimated from the baseband delay detection circuit 83 that outputs as the quadrature component Q, the output signal S (nT) of the baseband delay detection circuit 83 and the determination result,
Phase error estimation circuit that outputs a phase compensation value for each symbol
84 and the phase compensation value supplied from the phase error estimation circuit 84, the output signal S (n
The phase compensation circuit 87 for compensating the phase error caused by the frequency offset included in T) and the output of the phase compensation circuit 87
It comprises a judgment circuit 88 for judging a value, a decoder 89 for converting the output of the judgment circuit 88 into binary serial data, and a reception data output terminal 90 for outputting the output of the decoder 89 as reception data.

Further, the phase error estimation circuit 84 calculates a correlation between the output signal S (nT) of the baseband delay detection circuit 83 and the output signal D (nT) of the judgment circuit 88.
And an adaptive calculation circuit 86 that calculates the phase compensation value using the calculation result of the correlation calculation circuit 85.

In this device, the input terminal 81 and the input terminal 82 are
At the symbol identification time point nT (n: positive integer, T: symbol period), the in-phase component X (nT) and the quadrature component Y (nT) of the waveform-shaped baseband waveform data are applied respectively, and the baseband delay is applied. It is supplied to the detection circuit 83.

The baseband differential detection circuit 83 performs differential detection on the waveform data X (nT) and Y (nT), and calculates the cosine and sine of the modulation phase difference of the π / 4 shift QPSK modulated wave signal, respectively. It is output as an in-phase component I (nT) and a quadrature component Q (nT). Here, when the output of the baseband differential detection circuit 83 is expressed as a complex signal S (nT) having the in-phase signal as the real part and the quadrature component as the imaginary part, it becomes as shown in (Equation 1). (Equation 1) S (nT) = I (nT) + jQ (nT) Similarly, the complex expression of the phase compensation value output from the phase error estimation circuit 84 is Ψ ′ ((n−1) T) (this In the specification, the complex conjugate is represented by "'"), and the complex expression of the output of the determination circuit 88 is D (nT). The phase error estimation circuit 84 is
The phase error caused by the frequency offset is estimated, and the conjugate complex number Ψ '((n-1) T) of the estimated value Ψ ((n-1) T).
Is output as a phase compensation value.

The phase compensation circuit 87 converts the output S (nT) of the baseband delay detection circuit 83 into the output Ψ'of the phase error estimation circuit 84.
Phase compensation is performed with ((n-1) T), and S (nT) .Ψ '((n-1)
T) is output. When the decision circuit 88 makes a four-valued decision on the output of the phase compensation circuit 87 and outputs D (nT), the phase error estimation circuit 84 gives the D (nT) and S (nT) Ψ '((n- 1)
Error with ε (n) (= D (nT) −S (nT) · Ψ ′ ((n−
1) T)) so that the sum of squares of S ((n + 1))
The estimated value Ψ (nT) of the phase error with respect to T) is obtained, and its conjugate complex number, that is, the phase compensation value Ψ ′ (nT) is output.

At this time, the phase error estimation circuit 84 performs the correlation calculation shown in (Equation 2) to calculate the phase compensation value Ψ '(nT). (Equation 2) Ψ ′ (nT) = {Σ _k λ ^nk · S ′ (kT) · D (kT)} / {Σ _k λ
^nk · | S (kT) | ² } (Σ _k is added from k = 1 to n) where λ is a forgetting coefficient, and the value is determined within the range of 0 <λ ≦ 1.

The correlation calculation circuit 85 of the phase error estimation circuit 84 is
Using the output signal of the baseband differential detection circuit 83 and the output signal of the determination circuit 88, S '(n
T) / D (nT) correlation calculation is performed, and the adaptive calculation circuit 86
Performs calculation by the adaptive algorithm shown in (Equation 2) using the calculation result of the correlation calculation circuit 85.

When the phase error estimation circuit 84 outputs the phase compensation value Ψ '(nT) thus obtained, the phase compensation circuit 87 uses this phase compensation value Ψ' (nT) to determine the symbol identification time point one symbol later. (N + 1) T baseband differential detection circuit
The phase error is compensated for the output S ((n + 1) T) of 83, and the decision circuit 88 makes a four-value decision on the output of the phase compensation circuit 87 in which the phase error is compensated. The decoder 89 includes a decision circuit 88.
Is converted into binary serial data, and the converted data is output from the output terminal 90 as received data.

As described above, the conventional frequency offset compensating apparatus performs the calculation shown in (Equation 2) for each symbol,
The phase error compensation value is updated for each symbol. As a result, highly accurate phase error compensation is performed.

[0013]

However, the conventional frequency offset compensating apparatus has a problem that the power consumption increases because it performs a complicated adaptive calculation for each symbol.

The present invention solves these conventional problems, and provides a frequency offset compensator capable of reducing the power consumed for calculating the phase compensation value without degrading the accuracy of phase error compensation. Is intended.

[0015]

Therefore, in the frequency offset compensating apparatus of the present invention, in estimating the phase error,
The correlation value calculated for each symbol is accumulated over N symbols, and the phase error compensation value is calculated for each N symbol using this accumulated value.

Therefore, the correlation values are added between N symbols, and the phase error compensation value is calculated once every N symbols. Therefore, compared with the conventional device that calculates the phase error compensation value for each symbol, the power consumption can be reduced without lowering the phase error compensation accuracy.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a phase compensating means for compensating a phase error due to a frequency offset of received data after detection using a phase error compensating value, and a phase compensating means. The phase error due to the frequency offset is estimated from the correlation means between the received data after detection and the data after quadrant determination, and the phase error compensation value is output to the phase compensation means. In the frequency offset compensating apparatus including the phase error estimating means, the phase error estimating means calculates the correlation value S between the conjugate complex data S ′ of the received data S after detection calculated by the phase error estimating means and the output D of the determining means. '· D, and the reception data S after detection and its conjugate complex data S' complex multiplication result between | S | ^2, accumulated over between N symbols respectively, each N symbols using these accumulated values Is obtained by so as to calculates the phase error compensation value, the calculation of the phase error compensation value, rather than being performed per symbol, is performed by dividing the once N symbols.

According to a second aspect of the present invention, the phase error estimating means includes a correlation calculating circuit for calculating a correlation value S'.D for each symbol, and a correlation value S '.
D and the complex multiplication result | S | ² calculated from the received data S after detection are accumulated for N symbols between N symbols, and the output of this N symbol addition circuit An adaptive arithmetic circuit that performs an average operation using an adaptive algorithm and updates the average value Z of the cumulative values of the correlation value S ′ · D and the average value R of the cumulative values of the complex multiplication result | S | ² for each N symbol. And an estimated error correction circuit that calculates a phase error compensation value for every N symbols from the output of this adaptive operation circuit, and the accumulated value of S ′ · D and | S
The cumulative value of | ² is averaged using an adaptive algorithm, and the average calculation result of the cumulative values of S ′ · D is divided by the average calculation result of the cumulative values of | S | ² to calculate the phase error compensation value. .

According to a third aspect of the present invention, the phase error estimating means includes a correlation calculation circuit for calculating the correlation value S'.D for each symbol, and a correlation value S '. Output from the correlation calculation circuit.
D and the complex multiplication result | S | ² calculated from the received data S after detection are accumulated for N symbols between N symbols, and the output of this N symbol addition circuit The moving average calculation between L × N symbols is performed, and the moving average value Z of the cumulative value of the correlation value S ′ · D and the moving average value R of the cumulative value of the complex multiplication result | S | ² are updated every N symbols. And an estimated error correction circuit that calculates a phase error compensation value for every N symbols from the output of this moving average circuit. The moving average value Z of the cumulative value of S ′ · D is The phase error compensation value is calculated by dividing by the moving average value R of the cumulative value of S | ² .

According to a fourth aspect of the present invention, the estimation error correction circuit corrects the phase error compensation value within the compensable range when the calculated phase error compensation value exceeds the compensable range. Therefore, the failure of the compensating operation of the phase compensating means can be prevented.

According to a fifth aspect of the present invention, there is provided conversion means for converting the phase error compensation value output from the phase error estimation means into frequency control data for the reference oscillator, and this conversion means provides the frequency control for the reference oscillator. When the above is performed, the past phase error compensation value of the phase error estimating means is reset, and the frequency deviation of the reference oscillator can be corrected based on the phase error compensation value.

According to a sixth aspect of the present invention, the averaging means for averaging the frequency control data output from the converting means and outputting the averaged frequency control data to the reference oscillator is provided, and the averaged frequency control data is used. Thereby, the frequency deviation of the reference oscillator can be stably controlled.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) The frequency offset compensating apparatus of the first embodiment is an apparatus for performing frequency offset compensating of a TDMA data receiving apparatus which receives a π / 4 shift QPSK modulated wave, and is as shown in FIG. In addition, the phase error estimation circuit 4 outputs the output signal S of the baseband delay detection circuit 3.
Correlation calculation circuit 5 that outputs a complex correlation value S ′ (nT) · D (nT) between the conjugate signal S ′ (nT) of (nT) and the output signal D (nT) of the determination circuit 10, and a correlation calculation circuit 5 from the output and the output of the baseband differential detection circuit 3 | S (n
T) | ² for each N symbols, and an N-symbol addition circuit 6 and an adaptive calculation circuit 7 for performing an average calculation using an adaptive algorithm on the output of the N-symbol addition circuit 6.
And an estimated error correction circuit that calculates a phase error compensation value for each N symbols using the output of the adaptive operation circuit 7 and further performs correction within the compensable range when the compensation value exceeds the compensable range. 8 and. Other configurations are the same as those of the conventional device (FIG. 5).

Next, the operation of this device will be described.

At the input terminal 1 and the input terminal 2, symbol identification time points nT (n: positive integer, T: symbol period, N × m).
≦ n <N × (m + 1), m: positive integer, N: average number of symbols), the in-phase component X (nT) and the quadrature component Y (nT) of the waveform-shaped baseband waveform data are applied, These components are the baseband differential detection circuit 3
Is supplied to.

The baseband differential detection circuit 3 performs differential detection on the waveform data X (nT) and Y (nT) to obtain π /
The cosine and sine of the modulation phase difference of the 4-shift QPSK modulated wave signal are output as an in-phase component I (nT) and a quadrature component Q (nT), respectively. The output of the baseband differential detection circuit 3 is expressed as a complex signal as follows. (Equation 3) S (nT) = I (nT) + jQ (nT) Further, the phase compensation value output by the phase error estimation circuit 4 for every N symbols is expressed in complex as Ψ ′ (m−1), and the determination circuit 10 The output of is expressed as D (nT) in a complex manner.

The phase compensation circuit 9 outputs the output S (nT) of the baseband delay detection circuit 3 to the output Ψ'of the phase error estimation circuit 4.
(m-1) phase-compensates and outputs S (nT) .psi. '(m-1), and the decision circuit 10 makes a four-value decision on the output of the phase compensation circuit 9 and outputs D (nT). Then, the phase error estimation circuit 4
The error between this D (nT) and the output of the phase compensation circuit 9 is ε (n) =
The estimated value Ψ (m) of the phase error is obtained so that the sum of squares of D (nT) −S (nT) · Ψ ′ (m−1) is minimized, and its conjugate complex number, that is, the phase compensation value Ψ ′. Output (m).

At this time, the phase error estimation circuit 4 calculates the phase compensation value Ψ '(nT) by performing the correlation calculation shown in (Equation 4). (Equation 4) Ψ ′ (m) = Σ _i λ ^mi {Σ _k S ′ (kT) · D (kT)} / Σ _i λ ^mi {Σ _k | S (nT) | ² } = AZ (m) / AR (m) where Z (m) = Σ _k S ′ (kT) · D (kT) R (m) = Σ _k | S (nT) | ² AZ (m) = Σ _i λ ^mi {Σ _k S '(kT) ・ D (kT)} = Σ _i λ
^mi · Z (m) AR (m) = Σ _i λ ^mi {Σ _k | S (nT) | ² } = Σ _i λ ^mi · R
(m) (Σ _i is added from i = 1 to m, Σ _k is added from k = 1 to N) Here, λ is a forgetting coefficient, and a value is determined within a range of 0 <λ ≦ 1.

The correlation calculation circuit 5 of the phase error estimation circuit 4 is
The correlation calculation of S ′ (kT) · D (kT) shown in (Equation 4) is performed for each symbol, and the correlation calculation result is supplied to the N-symbol addition circuit 6.

The N-symbol addition circuit 6 adds the output of the correlation calculation circuit 5 over N symbols, and outputs the output signal S (nT) of the baseband delay detection circuit 3 and its conjugate complex signal S '( nT) complex multiplication result | S (nT) | ² is added over N symbols, and Z (m), R
Output (m) once every N symbols.

The adaptive arithmetic circuit 7 uses Σ _i λ ^mi · Z (m) and Σ _i λ ^mi · R (m) shown in (Equation 4) for Z (m) and R (m) to obtain λ Is used to perform an average calculation, and AZ (m) and AR (m) are output as the calculation results.

The estimation error correction circuit 8 outputs AZ (m) and AR (m) from the adaptive operation circuit 7 once every N symbols.
Then, the next phase error compensation value Ψ ′ (m) is calculated by AZ (m) / AR (m). When the phase compensation value exceeds the compensable range, the phase compensation value is corrected to a value within the compensable range and output.

As described above, the phase compensation value Ψ '(m) output from the phase error estimating circuit 4 is constant over N symbols, and the phase compensating circuit 9 determines the symbol identification time point nT (N × N).
When m ≦ n <N × (m + 1)), the phase compensation value Ψ ′ (m−
Phase compensation is performed using 1). During this period, the phase error estimation circuit 4 calculates the phase compensation value Ψ '(m) for performing the phase compensation for the next N symbols.

Then, the phase compensation circuit 9 uses the phase compensation value Ψ '(m) obtained by the phase error estimation circuit 4 to determine the symbol identification time point nT (N × (m + 1) ≦ n <N × (m + 2)).
The phase error caused by the frequency offset in (1) is compensated, and the determination circuit 10 determines the output of the phase compensation circuit 9 in which the phase error is compensated from four values. The decoder 11 is a decision circuit
The output of 10 is converted into binary serial data, and the converted data is output from the output terminal 12 as received data.

As described above, the frequency offset compensating apparatus of the first embodiment does not calculate the phase error compensation value for each symbol, but only performs addition for N symbols.
The addition value is used to perform an average calculation by an adaptive algorithm once every N symbols to calculate a phase compensation value for each N symbols, and the phase error is compensated using this phase compensation value. Therefore, the power consumption required for the calculation can be reduced as compared with the conventional one.

(Embodiment 2) The frequency offset compensating apparatus according to the second embodiment is N-valued when calculating the phase compensation value.
Calculate the moving average of the cumulative value between symbols.

In this apparatus, as shown in FIG. 2, the phase error estimation circuit 24 replaces the adaptive operation circuit with S '(nT) .D (nT) and | output from the N-symbol addition circuit 26. S
(nT) | ² , using the cumulative value between N symbols, L ×
A moving average circuit 27 for calculating a moving average of N symbols, updating the moving average value for every N symbols, and outputting the updated value to an estimation error correction circuit 28 is provided. Other configurations are the same as those of the first embodiment (FIG. 1).

The phase error estimation circuit 24 determines the determination result D (nT) of the determination circuit 30 and the output S (nT) ψ 'of the phase compensation circuit 29.
Error from (m−1) ε (n) = D (nT) −S (nT) · Ψ ′ (m
Phase compensation value Ψ ′ such that the sum of squares of −1) is minimized.
(m) is calculated by the following equation (5). (Equation 5) Ψ ′ (m) = E [Σ _k S ′ (kT) · D (kT)] / E [Σ _k | S (nT) | ² ] = AZ (m) / AR (m) Z (m) = Σ _k S ′ (kT) · D (kT) R (m) = Σ _k | S (nT) | ² AZ (m) = E [Σ _k S ′ (kT) · D (kT) ] = E [Z
(m)] AR (m) = E [Σ _k | S (nT) | ² ] = E [R (m)] (Σ _k is added from k = 1 to N) E [•] is the average operation And L × N symbols (L,
N: Positive integer) is calculated.

The correlation calculation circuit 25 of the phase error estimation circuit 24 is
The correlation calculation of S ′ (kT) · D (kT) shown in (Equation 5) is performed for each symbol, and the correlation calculation result is supplied to the N-symbol addition circuit 26.

The N-symbol addition circuit 26 is a correlation calculation circuit.
The outputs of 25 are added over N symbols, and the result of complex multiplication of the output signal S (nT) of the baseband differential detection circuit 23 and its conjugate complex signal S ′ (nT) | S (nT) | ² Are added over N symbols, and Z (m), R
Output (m) once every N symbols.

The moving average circuit 27 has moving averages E [Z (m)] and E [R of the Z (m) and R (m) over L × N symbols.
(m)] is calculated and the updated values AZ (m) and AR (m) of the moving average are output to the estimation error correction circuit 28 every time Z (m) and R (m) are input.

The estimation error correction circuit 28 outputs AZ (m) and AR (m) from the moving average circuit 27 once every N symbols.
Then, the next phase error compensation value Ψ ′ (m) is calculated by AZ (m) / AR (m). When the phase compensation value exceeds the compensable range, the phase compensation value is corrected to a value within the compensable range and output.

As described above, the frequency offset compensating apparatus according to the second embodiment does not calculate the phase error for each symbol, but only performs addition for N symbols and uses the addition value to set 1 to N symbols. By performing the moving average calculation every time, the phase compensation value is calculated for every N symbols, and the phase error is compensated using this phase compensation value.
Therefore, the power consumption required for the calculation can be reduced as compared with the conventional one.

(Third Embodiment) The frequency offset compensating apparatus of the third embodiment has a mechanism for controlling the frequency of the reference oscillator based on the phase compensation value.

As shown in FIG. 3, this apparatus uses a reference oscillator 48 which supplies an oscillating frequency as an operation reference of the data receiving apparatus and a phase compensation value Ψ ′ output from the phase error estimation circuit 44 to the reference oscillator 48. Phase error estimation circuit when the signal is converted to the control signal and the frequency of the reference oscillator 48 is controlled.
The converter circuit 47 outputs a reset signal for resetting the past phase compensation values of 44. Other configurations are the same as those of the first or second embodiment.

The phase error estimation circuit 44 of this apparatus performs the correlation calculation of (Equation 4) or (Equation 5), and the S at the symbol identification time point nT (N × (m + 1) ≦ n <N × (m + 2)).
The phase compensation value ψ ′ (m) for compensating the phase error of (nT) is output to the phase compensation circuit 45 and the conversion circuit 47.

The conversion circuit 47 converts this phase compensation value Ψ '(m) into a control signal for correcting the frequency deviation of the reference oscillator 48, and controls the oscillation frequency of the reference oscillator 48 by this control signal, Correct the deviation. In addition, the conversion circuit 47
Outputs a reset signal to the phase error estimating circuit 44 when the frequency of the reference oscillator 48 is controlled, and resets the past phase compensation value in the phase error estimating circuit 44.

As described above, the frequency offset compensating apparatus of the third embodiment can control the frequency of the reference oscillator by the phase compensation value output from the phase error estimating circuit of the first or second embodiment. it can.

(Fourth Embodiment) As shown in FIG. 4, the frequency offset compensating apparatus according to the fourth embodiment has a conversion circuit 67.
An averaging circuit 68 for averaging the frequency control data of the reference oscillator 69 output from Other configurations are 3rd
Is the same as the embodiment (FIG. 3).

In this device, when the conversion circuit 67 converts the phase compensation value Ψ '(m) and outputs a control signal for correcting the frequency deviation of the reference oscillator 69, the averaging circuit 68 causes the conversion circuit 67 to operate. The output of is averaged, the averaged control signal is sent to the reference oscillator 69, the oscillation frequency is controlled, and the frequency deviation is corrected.

When the frequency of the reference oscillator 69 is controlled, the conversion circuit 67 outputs a reset signal to the phase error estimation circuit 64 to reset the past phase compensation value in the phase error estimation circuit 64. The averaging circuit 68 is a reference oscillator 69.
Even when the frequency control is performed, the control signal for the reference oscillator 69 is held without being reset, and the averaging with the past control signal is subsequently performed.

As described above, the frequency offset compensating apparatus of the fourth embodiment averages the control signal for the reference oscillator, so that the oscillation frequency of the reference oscillator can be stably controlled.

In the embodiment, the case where the received wave is π / 4 shift QPSK modulation has been described, but the present invention can be applied to other modulation methods.

[0055]

As is apparent from the above description, the frequency offset compensating apparatus of the present invention reduces the power consumption required for calculating the phase error compensation value without degrading the accuracy of compensating the phase error caused by the frequency offset. It can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frequency offset compensating apparatus according to a first embodiment of the present invention,

FIG. 2 is a block diagram showing a configuration of a frequency offset compensating apparatus according to a second embodiment of the present invention,

FIG. 3 is a block diagram showing a configuration of a frequency offset compensating apparatus according to a third embodiment of the present invention,

FIG. 4 is a block diagram showing a configuration of a frequency offset compensating apparatus according to a fourth embodiment of the present invention,

FIG. 5 is a block diagram showing a configuration of a conventional frequency offset compensating apparatus.

[Explanation of symbols]

 1, 2, 21, 22, 41, 42, 61, 62, 81, 82 Input terminals 3, 23, 43, 63, 83 Baseband differential detection circuit 4, 24, 44, 64, 84 Phase error estimation circuit 5, 25,85 Correlation calculation circuit 6,26 N-symbol addition circuit 7,86 Adaptive calculation circuit 8,28 Estimated error correction circuit 9,29,45,65,87 Phase compensation circuit 10,30,46,66,88 Judgment circuit 11, 31, 49, 70, 89 Decoder 12, 32, 50, 71, 90 Output terminal 27 Moving average circuit 47, 67 Conversion circuit 48, 69 Reference oscillator 68 Average circuit

Claims (6)

[Claims] 1. A phase compensating means for compensating a phase error caused by a frequency offset of received data after detection using a phase error compensating value, a judging means for making a quadrant judgment with respect to an output of the phase compensating means, and a detection. A frequency offset compensating apparatus comprising: a phase error estimating means for estimating a phase error caused by a frequency offset from a correlation value between the received data after the quadrant determination and a phase error estimating means for outputting the phase error compensation value to the phase compensating means. , The correlation value S ′ · D between the conjugate complex data S ′ of the received data S after detection calculated by the phase error estimation means for each symbol and the output D of the determination means, and the received data S after detection. its conjugate complex data S 'and the complex multiplication result of | S | ² and accumulated over between N symbols each, calculating child said phase error compensation value every N symbols using these accumulated values Frequency offset compensating apparatus according to claim. 2. The phase error estimating means calculates a correlation value S ′ · D for each symbol, a correlation value S ′ · D output from the correlation calculation circuit, and after detection. The complex multiplication result | S |
² , an N-symbol addition circuit for accumulating N symbols each, and an average operation using an adaptive algorithm for each N symbol are performed on the output of the N-symbol addition circuit, and the correlation value S ′ is calculated for each N symbol. An average value Z of accumulated values of D and an average value R of accumulated values of the complex multiplication result | S | ²
2. The frequency offset compensating apparatus according to claim 1, further comprising: an adaptive arithmetic circuit that updates the phase error compensation circuit and an estimation error correction circuit that calculates the phase error compensation value for every N symbols from the output of the adaptive arithmetic circuit. . 3. The phase error estimating means calculates a correlation value S ′ · D for each symbol, a correlation value S ′ · D output from the correlation calculation circuit, and after detection. The complex multiplication result | S |
² , N-symbol addition circuit for accumulating N symbols each, and a moving average calculation between L × N symbols for every N symbols for the output of the N-symbol addition circuit,
A moving average circuit for updating the moving average value Z of the cumulative value of the correlation value S ′ · D and the moving average value R of the cumulative value of the complex multiplication result | S | ² for every N symbols; 2. An estimation error correction circuit for calculating the phase error compensation value for every N symbols from the output of the above.
The frequency offset compensating device according to. 4. The estimation error correction circuit corrects the phase error compensation value within the compensable range when the calculated phase error compensation value exceeds the compensable range. 2. The frequency offset compensating device according to 2 or 3. 5. A conversion means for converting the phase error compensation value output from the phase error estimation means into frequency control data of a reference oscillator, wherein the conversion means performs frequency control of the reference oscillator. The frequency offset compensating apparatus according to claim 1, wherein the past phase error compensation value of the phase error estimating means is reset. 6. The frequency offset compensator according to claim 5, further comprising averaging means for averaging the frequency control data output from the converting means and outputting the averaged data to the reference oscillator.