JPH0955774A - Frequency offset compensator - Google Patents

Abstract

(57) [Abstract] (Correction) [PROBLEMS] To provide a frequency offset compensating device capable of reducing power consumption while maintaining compensation accuracy of a phase error. SOLUTION: The phase error estimating means is compared with a first phase error estimating means 4 having excellent initial convergence characteristics and a second phase error estimating means having a second phase error estimating means inferior in initial convergence characteristics but low power consumption. The phase error estimating means 5 and the switching means 6 operate the first phase error estimating means at the time of initial pull-in and operate the second phase error estimating means at the time of burst reception. Excellent initial convergence characteristics during initial pull-in
Of the phase error estimating means operates to quickly converge the frequency offset, and at the time of the subsequent burst reception, the second phase error estimating means consuming less power operates to maintain the convergence state of the frequency offset. Continue to compensate for errors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency offset compensating device used in a TDMA data receiving device for digital mobile communication, and more particularly to realizing low power consumption.

[0002]

2. Description of the Related Art In TDMA digital mobile communication, data addressed to each receiving device is transmitted in a time division manner. For example, in the case of 3-slot multiplexing, the data receiving apparatus receives one of the slots sent three times as a slot addressed to itself, and the reception interval of the slot addressed to itself is set to 20 msec. There is.

The data receiving apparatus detects the received signal and decodes the data, but if there is a frequency offset between the modulation on the transmitting side and the demodulation on the receiving side at this time, correct decoding cannot be performed. Therefore, the receiving device uses a frequency offset compensating device to compensate for this frequency offset.

Conventionally, in this frequency offset compensating apparatus, a method has been developed in which an error caused by the frequency offset is estimated from the decoding result of the immediately preceding symbol, and the frequency offset of the next symbol is compensated based on the estimated amount. ing. In this device, the received signal is, for example, π of TDMA.
In the case of a / 4-shift QPSK modulated wave signal, as shown in FIG. 6, the input terminal 31 to which the in-phase component X at the time of symbol identification of the waveform-shaped baseband waveform data is applied, and the waveform-shaped base The input terminal 32 to which the orthogonal component at the time of symbol identification of the waveform data of the band is applied, and the waveform data X and Y applied to the input terminals 31 and 32.
And the cosine and sine of the modulation phase difference of the received π / 4 shift QPSK modulated wave signal are respectively in-phase component I,
Baseband differential detection circuit 33 that outputs as quadrature component Q
And a phase error estimation circuit 34 that estimates a phase error from the output signals I and Q of the baseband delay detection circuit 33 and the output signals I ′ and Q ′ of a determination circuit 36 described later and outputs a phase compensation value.
And a phase compensation circuit 35 for compensating for a phase error caused by a frequency offset contained in the output signals I and Q of the baseband delay detection circuit 33 using the phase compensation value output from the phase error estimation circuit 34, and a phase compensation A decision circuit 36 for making a four-value decision on the output of the circuit 35, a decoder 37 for converting the output of the decision circuit 36 into binary serial data, and a reception data output terminal 38 for outputting the output of the decoder 37 as reception data. Is equipped with.

The phase error estimation circuit 34 moves N symbols of the complex correlation value between the output signals I and Q of the baseband delay detection circuit 33 and the output signals I'and Q'of the determination circuit 36 as the phase error compensation value. The average value Ψ * (* represents a conjugate complex number),
Data is updated and output for each symbol. This Ψ *
Is a conjugate complex number of the phase error estimated value Ψ. Further, the phase compensation circuit 35 uses the value of Ψ * to compensate the phase error caused by the frequency offset contained in the output signals I and Q of the baseband differential detection circuit 33.

The operation of this device will be described. At the symbol identification time point nT (n: positive integer, T: symbol period), the in-phase component X (nT) of the waveform data of the baseband waveform-shaped at the input terminal 31 and the base waveform-shaped at the input terminal 32. Orthogonal component Y (nT) of band waveform data
Are applied and are respectively supplied to the baseband differential detection circuit 33. The baseband differential detection circuit 33 performs differential detection on the waveform data X (nT) and Y (nT) to find the phase difference between one symbol, and calculates the cosine of the modulation phase difference of the π / 4 shift QPSK modulated wave signal. And sine are output as an in-phase component I (nT) and a quadrature component Q (nT), respectively. here,
When the output of the baseband differential detection circuit 33 is expressed as a complex signal S (nT) having the in-phase signal in the real part and the quadrature component in the imaginary part, it becomes as shown in (Equation 1).

S (nT) = I (nT) + jQ (nT) (Equation 1) Similarly, the complex expressions of the output of the phase error estimation circuit 34 and the output of the determination circuit 36 are respectively expressed by Ψ * ((n-1 ) T), D (nT)
And

Therefore, the estimated value Ψ (nT) of the phase error caused by the frequency offset is phase-compensated to S (nT), the output of the phase compensation circuit 35, and the determination circuit for this output.
It is selected so that the mean square of the error ε (n) with the output of 36 is minimized. The phase compensation circuit 35 is a baseband delay detection circuit 33.
Using the conjugate complex number Ψ * ((n−1) T) of the estimated value Ψ ((n−1) T) of the phase error output from the phase error estimation circuit 34 for the output S (nT) of Phase compensation is performed, S (nT)
・ Output Ψ * ((n-1) T). The error between the output of the phase compensating circuit 35 and the result D (nT) obtained by the determination circuit 36 performing four-valued determination on this output is ε (n) = D (nT) −S (nT) · Ψ * ((n-1) T). When the phase error estimated value Ψ (nT) is selected so that the root mean square of ε (n) is minimized, the phase compensation value Ψ * (nT), which is the conjugate complex number of the phase error estimated value, is It is obtained by performing the correlation calculation shown in (Equation 2) in the estimation circuit 34.

Ψ * (nT) = {E [S * (nT) · D (nT)]} / {E [| S (nT) | ² ]} (Equation 2) where E [·] is an average operation In this case, the moving average of N symbols (N: positive integer) is used.

The phase error estimation circuit 34 outputs the phase compensation value Ψ * (nT) thus obtained to the phase compensation circuit 35, and the phase compensation circuit 35 uses this phase compensation value Ψ * (nT) to obtain 1 Compensating for the phase error caused by the frequency offset at S ((n + 1) T) of the symbol identification time (n + 1) T after the symbol,
The decision circuit 36 makes a four-value decision on the output in which the phase error is compensated. The output of the determination circuit 36 is converted into binary serial data by the decoder 37 and output as output data from the output terminal 38.

As described above, in the conventional frequency offset compensating apparatus, the calculation shown in (Equation 2) is performed for each symbol, and the compensation value of the phase error is updated for each symbol. Therefore, it is possible to perform highly accurate phase error compensation with excellent initial convergence characteristics.

[0012]

However, in the conventional frequency offset compensating apparatus, the power consumption becomes large because the complex moving average calculation is always performed for each symbol regardless of the initial pull-in and the burst reception. was there.

The present invention is intended to solve such conventional problems, and an object of the present invention is to provide a frequency offset compensating apparatus capable of reducing power consumption while maintaining phase error compensation accuracy.

[0014]

Therefore, in the present invention, a phase error for estimating a phase error caused by a frequency offset from a correlation value between received data after detection and data after quadrant determination and outputting a phase compensation value In a frequency offset compensating device comprising an estimating means and a phase compensating means for compensating for a phase error of received data after detection using the phase error compensating value, the phase error estimating means is provided with a first initial characteristic excellent in convergence property. Of the first phase error estimating means and the second phase error estimating means which is inferior to the first phase error estimating means in initial convergence characteristics but consumes less power, and the first phase error estimating means is operated at the time of initial pull-in. , And switching means for operating the second phase error estimating means at the time of burst reception.

Further, the first phase error estimating means includes a correlation calculating means for calculating the correlation value between the conjugate complex data of the received data after detection and the complex data after the quadrant determination for each symbol, and the correlation calculating means. The moving average means calculates the moving average value of the output correlation values over N symbols and outputs the moving average value as a phase compensation value for each symbol.

Further, the first phase error estimating means uses a correlation calculating means for calculating a correlation value between the conjugate complex data of the received data after detection and the complex data after the quadrant determination for each symbol, and an adaptive algorithm. The average value of the correlation values output from the correlation operation means is calculated, and the result of the average operation is output as a phase compensation value for each symbol.

Further, the second phase error estimating means is composed of a correlation calculating means for calculating the correlation value between the conjugate complex data of the received data after detection and the complex data after the quadrant determination for each symbol, and the correlation calculating means. The inter-slot averaging means calculates the average value of the output correlation values over one slot and outputs this average value as a phase compensation value for each slot.

Further, the second phase error estimating means includes a correlation calculating means for calculating the correlation value between the conjugate complex data of the received data after detection and the complex data after the quadrant determination for each symbol, and the correlation calculating means. The N-symbol averaging means calculates the average value of the output correlation values over N symbols and outputs the average value as a phase compensation value for every N symbols.

[0019]

Therefore, when the received signal is initially pulled in, the first phase error estimating means having an excellent initial convergence characteristic compensates for the phase error and the frequency offset is quickly converged. At the time of burst reception after the initial pull-in, the second phase error estimating means consuming a small amount of power operates to continue compensating the phase error while maintaining the converged state of the frequency offset. As a result, the power consumption can be reduced while maintaining the compensation accuracy with a high phase error.

Further, by averaging the correlation value between the conjugate complex data of the received data after detection and the complex data after quadrant determination, the error between the received data in which the phase error is compensated and the data after quadrant determination is minimized. Phase compensation value can be obtained, and as this averaging operation, a moving average calculation of N symbols or an averaging calculation using an adaptive algorithm is performed, and the calculation result is output for each symbol to obtain the initial convergence characteristic. An excellent first phase error estimation means can be configured. Further, as this averaging operation, the average of one slot and the simple average of N symbols are calculated, and the calculation result is
By outputting every slot or every N symbols,
It is possible to configure a second phase error estimation unit that has a small amount of calculation and consumes less power.

[0021]

【Example】

(First Embodiment) The frequency offset compensating apparatus of the first embodiment performs frequency offset compensation on the waveform-shaped baseband waveform data of the received TDMA .pi. / 4 shift QPSK modulated wave signal. As shown in FIG. 1, this device has a moving average value Ψ ₁ * of N symbols of complex correlation values between the output signals I and Q of the baseband differential detection circuit 3 and the output signals I ′ and Q ′ of the determination circuit 9. A first phase error estimation circuit 4 for updating and outputting data for each symbol,
The average value Ψ ₂ * of one complex slot of the complex correlation values of the output signals I and Q of the baseband differential detection circuit 3 and the output signals I ′ and Q ′ of the determination circuit 9 is updated by outputting the data for each slot. A second phase error estimation circuit 5 for selecting the output of the first phase error estimation circuit 4 at the time of initial pull-in, and a switch 6 for selecting the output of the second phase error estimation circuit 5 at the time of burst reception, It is provided with first and second phase error estimating circuits 4 and 5 and a control circuit 7 for controlling the switch 6.
Other configurations are the same as those of the conventional device (FIG. 6).

The first phase error estimation circuit 4 is shown in FIG.
As shown in FIG. 3, a correlation calculation circuit 12 that performs a correlation calculation between the output signals I and Q of the baseband delay detection circuit 3 and the output signals I ′ and Q ′ of the determination circuit 9, and the complex calculation circuit 12 And a moving average circuit 13 for updating and outputting the data of the moving average value Ψ ₁ * of N symbols of the correlation value for each symbol.

Further, the second phase error estimation circuit 5 has the same structure as that of FIG.
As shown in (b), the correlation calculation circuit 14 for performing a correlation calculation between the output signals I and Q of the baseband delay detection circuit 3 and the output signals I ′ and Q ′ of the determination circuit 9, and the output of the correlation calculation circuit 14 The average value Ψ ₂ * for one slot of the complex correlation value is
An inter-slot averaging circuit 15 for updating and outputting data for each slot is provided.

Next, the operation of this frequency offset compensator will be described. First, the operation at the time of initial pull-in will be described.

Symbol identification time point nT (n: positive integer, T:
(Symbol period), the in-phase component X (nT) of the waveform-shaped baseband waveform data at the input terminal 1 and the quadrature component Y (nT) of the waveform-shaped baseband waveform data at the input terminal 2 Applied to the baseband differential detection circuit 3 respectively.
Outputs a signal represented by S (nT) = I (nT) + jQ (nT) in complex representation, as in the conventional device.

At the time of initial pull-in, the control circuit 7
Operates the first phase error estimation circuit 4 and stops the second phase error estimation circuit 5 by the control signal. Also,
The switch 6 is controlled so that the output of the first phase error estimation circuit 4 is selected and output to the phase compensation circuit 8. The control circuit 7 controls this control based on, for example, the reception time interval of the slot.

Correlation calculation circuit of the first phase error estimation circuit 4
To S12, S (nT) is input from the baseband differential detection circuit 3, and D (nT), which is the result of the four-valued determination of the output of the phase compensation circuit 8 from the determination circuit 9, is input. . The correlation calculation circuit 12 uses these signals to perform S * (nT) · D (nT) correlation calculation for each symbol. 1
The result of the correlation calculation S * (nT) · D (nT) for each symbol is output to the moving average circuit 13, and the moving average circuit 13 outputs this S *
The moving average over N symbols of (nT) · D (nT) is calculated by the following equation (Equation 3). Ψ ₁ * (nT) = {E [S * (nT) · D (nT)]} / {E [| S (nT) | ² ]} (Equation 3) However, E [•] is an averaging operation. This represents obtaining a moving average of N symbols.

The moving average circuit 13 sets the moving average calculation result to 1
It is updated for each symbol and output. This Ψ ₁ * (nT) is
The phase error estimation circuit 34 of the conventional device (FIG. 6) described above
Is the same as the phase compensation value Ψ * (nT) output from, and the estimated value Ψ (nT) of the phase error due to the frequency offset.
Is an error .epsilon.
This corresponds to the phase compensation value when the root mean square of (n) is selected to be the minimum.

The switch 6 converts this Ψ ₁ * (nT) into Ψ * (n
It is output to the phase compensation circuit 8 as T). Phase compensation circuit 8
Uses this phase compensation value Ψ * (nT) to compensate for the phase error at S ((n + 1) T) at the symbol identification time (n + 1) T one symbol after, and the determination circuit 9 The four-valued judgment of the output in which the phase error is compensated is performed. The output of the decision circuit 9 is converted into binary serial data by the decoder 10 and output from the output terminal 11 as received data.

Next, the operation during burst reception will be described. At the symbol identification time point nT of the m-th slot, the in-phase component X (nT) of the waveform-shaped baseband waveform data at the input terminal 1 and the orthogonal component of the waveform-shaped baseband waveform data at the input terminal 2 Baseband differential detection circuit 3 to which Y (nT) is applied and which are supplied
Outputs a signal represented by S (nT) = I (nT) + jQ (nT) in complex representation.

At the time of burst reception, the control circuit 7 operates the second phase error estimation circuit 5 and stops the first phase error estimation circuit 4 by the control signal. Further, the switch 6 is controlled so that the output of the second phase error estimation circuit 5 is selected and output to the phase compensation circuit 8.

Correlation calculation circuit of the second phase error estimation circuit 5
Similar to the correlation calculation circuit 12 of the first phase error estimation circuit 4, S (nT) is input from the baseband delay detection circuit 3 to D, and D (nT) is input from the determination circuit 9 to 14 for correlation calculation. circuit
14 uses these signals for S * (n
Correlation calculation of T) / D (nT) is performed. The result of the correlation calculation S * (nT) / D (nT) for each symbol is the inter-slot averaging circuit 1
5 and the inter-slot averaging circuit 15 outputs this S * (n
The average of one slot of T) · D (nT) is calculated by the following equation (Equation 4). Ψ ₂ * (m) = {E [S * (nT) · D (nT)]} / {E [| S (nT) | ² ]} (Equation 4) However, E [•] is an averaging operation. 1 represents obtaining an average for one slot. The inter-slot averaging circuit 15
₂ * (m) is updated for each slot and output.

The switch 6 converts this Ψ ₂ * (m) into Ψ * (m)
Is output to the phase compensation circuit 8. The phase compensation circuit 8 is
Phase compensation of received data is performed using this phase compensation value Ψ * (m). That is, the phase compensation value Ψ * (m) is constant over one slot, and in the mth slot, the phase compensation circuit 8 calculates the phase obtained by the second phase error estimation circuit 5 from the data one slot before. Phase compensation is performed using the compensation value Ψ * (m-1). At this time, the second phase error estimation circuit 5 simultaneously performs the phase compensation value Ψ * for performing the phase compensation of the next slot.
Calculate (m). The phase compensation value Ψ * (m) is used by the phase compensation circuit 8 to compensate for the phase error of the received data in the (m + 1) th slot of the next slot.

As described above, the frequency offset compensating apparatus according to the first embodiment uses the first phase error estimation circuit having the excellent initial convergence characteristic to reduce the frequency offset for a short period at the initial pull-in when a large frequency offset is expected. At the time of burst reception after the initial pull-in, the second phase error estimation circuit with low power consumption is used to compensate for the phase error while maintaining the converged frequency offset state. Therefore, it is possible to reduce power consumption while performing highly accurate compensation.

(Second Embodiment) As shown in FIG. 3B, the frequency offset compensating apparatus of the second embodiment outputs from the correlation calculating circuit 18 as an averaging circuit of the second phase error estimating circuit 5. An N-symbol averaging circuit 19 for calculating an average value Ψ ₂ * of N symbols of the complex correlation value and updating and outputting the data for each N symbol is provided. Other configurations are the same as those of the device of the first embodiment (FIGS. 1 and 2).

In this apparatus, at the time of initial pull-in, the state shown in FIG.
The first phase error estimation circuit 4 shown in (a) performs the same operation as in the first embodiment.

On the other hand, at the time of burst reception, the second phase error estimating circuit 5 operates, and the correlation calculating circuit 18 of the second phase error estimating circuit performs the correlation calculation of S * (nT) · D (nT), The N-symbol averaging circuit 19 uses the S * (nT) .D (n
The average of N symbols of T) is calculated by the following equation (Equation 5).

Ψ ₂ * (i) = {E [S * (nT) · D (nT)]} / {E [| S (nT) | ² ]} (Equation 5) where E [·] is the average This is an operation and represents obtaining an average between N symbols. The N-symbol averaging circuit 19 updates this Ψ ₂ * (i) for every N symbols and outputs it.

The phase compensation value Ψ * (i) is constant over N symbols, and the symbol identification time nT (N × i ≦ n
When T <N × (i + 1)), the phase compensation circuit 8 uses Ψ * (i-1)
To compensate the phase of the received data. At this time
At the same time, the phase error estimation circuit 5 calculates the phase compensation value Ψ * (i) for performing the phase compensation for the next N symbols.
This phase compensation value Ψ * (i) is calculated by the phase compensation circuit 8 at the symbol identification time point nT (N × (i + 1) ≦ nT <N × (i + 2)).
It is used to compensate for the phase error in the received data.

As described above, in the frequency offset compensating apparatus of the second embodiment, the second phase error estimating circuit calculates the average of correlation values among N symbols at the time of burst reception. This calculation requires a smaller amount of calculation and can be executed with less power consumption than the case where a moving average of N symbols is calculated. Further, by appropriately setting the value of N, it is possible to avoid a decrease in phase error compensation accuracy during burst reception.

(Third Embodiment) In the frequency offset compensating apparatus of the third embodiment, as shown in FIG. 4A, in the first phase error estimating circuit 4, the complex correlation value output from the correlation calculating circuit 20 is output. As a circuit for processing, an adaptive arithmetic circuit 21 for arithmetically calculating an average value Ψ ₁ * by an adaptive algorithm of a complex correlation value and updating and outputting data for each symbol is provided. Other configurations are the same as those of the device of the first embodiment (FIGS. 1 and 2).

In this apparatus, the first phase error estimation circuit 4 operates during the initial pull-in, and the correlation calculation circuit 20 causes S *.
Correlation calculation of (nT) · D (nT) is performed, and the correlation calculation result of S * (nT) · D (nT) is output for each symbol. According to 6), the calculation by the adaptive algorithm is performed.

Ψ ₁ * (nT) = {Σλ ^nk · S * (kT) · D (kT)} / {Σλ ^nk · | S (kT) | ² } (Σ adds k from 1 to n) ( (6) Here, λ is a forgetting coefficient, and a value is determined within the range of 0 <λ ≦ 1. The value of λ ^nk decreases as k decreases,
The weighting is performed so that the recent data whose convergence of the frequency offset has advanced is more important than the old data.

The adaptive operation circuit 21 outputs the operation result of (Equation 6) for each symbol, and this Ψ ₁ * (nT) is sent from the switch 6 to the phase compensation circuit 8 as the phase compensation value Ψ * (nT). Is output. The phase compensation circuit 8 uses the phase compensation value Ψ * (n
T) is used to identify the symbol after one symbol (n + 1) T
Compensate for the phase error due to the frequency offset in the received data of 1.

The operation at the time of burst reception is the same as that of the first embodiment.

As described above, the frequency offset compensating apparatus according to the third embodiment uses the first phase error estimating circuit that performs the initial convergence with high accuracy and speed according to the adaptive algorithm at the time of initial pull-in, and thus the phase error based on the frequency offset. And a phase error is compensated by using a second phase error estimation circuit having low power consumption during burst reception.

(Fourth Embodiment) As shown in FIGS. 5A and 5B, the frequency offset compensating apparatus of the fourth embodiment uses the adaptive arithmetic circuit 25 in the first phase error estimating circuit 4, Second
An N-symbol averaging circuit 27 is used for the phase error estimating circuit 5 of FIG. Therefore, at the time of initial pull-in, the same operation as the first phase error estimation circuit 4 described in the fourth embodiment is performed, and at the time of burst reception, the same operation as the second phase error estimation circuit 5 described in the second embodiment is performed. To do.

The apparatus of the fourth embodiment has the effects described in the second and fourth embodiments together.

In the above embodiment, the received signal is TD.
The case of the MA π / 4 shift QPSK modulated wave signal has been described, but the frequency offset compensating apparatus of the present invention can of course also perform frequency offset compensation for other received signals.

[0050]

As is apparent from the above description of the embodiments, the frequency offset compensating apparatus of the present invention is compared with the first phase error estimating circuit having excellent initial convergence characteristics and the first phase error estimating circuit. Then, the first phase error estimation circuit is operated at the time of initial pull-in and the second phase error estimation circuit is operated at the time of burst reception by using the second phase error estimation circuit having low power consumption but low power consumption. It's working.
Therefore, power consumption can be reduced while realizing highly accurate compensation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frequency offset compensating apparatus according to an embodiment of the present invention,

2A is a block diagram of a first phase error estimation circuit in the first embodiment, FIG. 2B is a block diagram of a second phase error estimation circuit in the first embodiment, FIG.

3A is a block diagram of a first phase error estimation circuit in a second embodiment, FIG. 3B is a block diagram of a second phase error estimation circuit in a second embodiment, FIG.

4A is a block diagram of a first phase error estimation circuit in a third embodiment, FIG. 4B is a block diagram of a second phase error estimation circuit in a third embodiment, FIG.

5A is a block diagram of a first phase error estimation circuit in a fourth embodiment, FIG. 5B is a block diagram of a second phase error estimation circuit in a fourth embodiment, FIG.

FIG. 6 is a block diagram illustrating a configuration of a conventional frequency offset compensator.

[Explanation of symbols]

 1, 2, 31, 32 Input terminal 3, 33 Baseband differential detection circuit 4 First phase error estimation circuit 5 Second phase error estimation circuit 6 Switch 7 Control circuit 8, 35 Phase compensation circuit 9, 36 Judgment circuit 10 , 37 Decoder 11, 38 Output terminals 12, 14, 16, 18, 20, 22, 24, 26 Correlation calculation circuit 13, 17 Moving average circuit 15, 23 Slot average circuit 19, 27 N symbol average circuit 21, 25 Adaptive arithmetic circuit 34 Phase error estimation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadashi Kayada 4-3-1, Tsunashimahigashi, Kohoku-ku, Yokohama-shi, Kanagawa Matsushita Communication Industrial Co., Ltd.

Claims (5)

[Claims] 1. A phase error estimating means for estimating a phase error caused by a frequency offset from a correlation value between received data after detection and data after quadrant determination, and outputting a phase compensation value.
In a frequency offset compensating device comprising a phase compensating means for compensating a phase error of received data after detection using the phase error compensating value, the phase error estimating means comprises a first phase error excellent in initial convergence characteristic. The estimation means and the second phase error estimation means which is inferior to the first phase error estimation means in initial convergence characteristics but consumes less power, and the first phase error estimation means at the time of initial pull-in are operated. A frequency offset compensating apparatus comprising: a switching unit that operates the second phase error estimating unit when a burst is received. 2. The correlation calculating means for calculating the correlation value between the conjugate complex data of the received data after the detection and the complex data after the quadrant determination, for each symbol, the first phase error estimating means, And a moving average means for calculating a moving average value of the correlation value output from the correlation calculating means over N symbols and outputting the moving average value as the phase compensation value for each symbol. The frequency offset compensating apparatus according to claim 1. 3. The correlation calculating means for calculating the correlation value between the conjugate complex data of the received data after the detection and the complex data after the quadrant determination, wherein the first phase error estimating means is adaptive for each symbol. And an adaptive calculation means for calculating an average of the correlation values output from the correlation calculation means by using an algorithm and outputting the result of the average calculation for each symbol as the phase compensation value. The frequency offset compensating apparatus according to claim 1. 4. The correlation calculating means for calculating the correlation value between the conjugate complex data of the received data after the detection and the complex data after the quadrant determination, for each symbol, the second phase error estimating means, An inter-slot averaging means for computing an average value of the correlation values output from the correlation computing means over one slot and outputting the average value as the phase compensation value for each slot. Item 4. The frequency offset compensating apparatus according to items 1 to 3. 5. The correlation calculating means for calculating the correlation value between the conjugate complex data of the received data after the detection and the complex data after the quadrant determination, for each symbol, the second phase error estimating means, And an inter-N-symbol averaging means for computing an average value of the correlation values output from the correlation computing means over N symbols and outputting the average value as the phase compensation value for every N symbols. Claims 1 to 3
The frequency offset compensating device according to.