JPH09204777A - Semiconductor memory, device for driving data signal of circuit to desired level, circuit for driving first and second signals to desired level, dynamic random access memory structure, driving data signal to desired level And a method of driving the first and second signals to a desired level - Google Patents

Abstract

A method and apparatus for overdriving a signal received by a sense amplifier circuit. An overdrive circuit drives sensed signals BLSA, BLWL to a voltage level greater than a normal level for a time interval 60. The length of the time interval corresponds to the position of the sense amplifier circuit relative to the sense enable circuit. Upon completion of the overdrive operation, the normalization circuit drives the sensed signal to the normal level for the second time interval 62, thereby preparing for the next memory cycle and again bringing the signal to the desired precharge level. Can be set to 63.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to semiconductor circuit design, and more particularly to a method and apparatus for controlled overdrive of sense amplifier circuits.

[0002]

2. Description of the Related Art In digital logic, an input / output data signal must meet a voltage level defined by either "high" (hereinafter abbreviated as H) or "low" (hereinafter abbreviated as L). . However, typical integrated circuits or "chips" that utilize digital logic also include data signals at various voltage levels. As a result, a sense amplifier circuit is used to interpret, or "sort", the data signal, driving the data signal to a target voltage level of H or L, thereby providing for other digital circuits on the chip. Generating the proper voltage. For example, capacitor-type memory cells for dynamic random access memory (“DRAM”) devices use very small bit signals. The sense amplifier circuit provided in the DRAM discriminates the bit signal by comparing the precharge level defined as a level between the H level and the L level of the memory cell with the bit signal. When the level of the bit signal is higher than the precharge level, the sense amplifier circuit interprets the signal as H or a signal of logical value 1 and sets the bit signal to H.
Drive to the target voltage of. On the other hand, when the level of the bit signal is lower than the precharge level, the sense amplifier circuit interprets the signal as L or a signal of logical value 0 and drives the bit signal to the target voltage of L.

As technology advances, the speed and accuracy of sense amplifier circuits becomes more important. For this reason, chip designers have tried various ways to increase the speed of signal separation. For example, Dhong et al., US Pat.
No. 257, 232 teaches a method of overdriving a sense amplifier circuit in order to increase the speed of signal separation.

[0004]

However, although the method of the above-mentioned US patent succeeds in quickly separating the signals, it has the following problems. One such problem is that this overdrive process is inaccurate because the bit signal does not end at the target voltage level of H or L when the sense is complete. Therefore, the bit signal does not return to the desired precharge level during the equalization period. Instead, the voltage rises above normal (overshoot) during sensing, causing the bit signal to return to an offset (offset) level. As a result, the precharge level changes and the sense amplifier circuit will not correctly interpret the next bit signal.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method and apparatus for achieving signal classification quickly by overdriving signals while maintaining the accuracy of sense amplifier operation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a method and apparatus for overdriving a signal received by a sense amplifier circuit. To this end, the overdrive circuit drives the sensed signal to a voltage level greater than the normal level for a period of time. The period of overdriving the signal corresponds to the position of the sense amplifier circuit relative to the sense enable circuit.
When the overdrive is complete, the normalization circuit drives the sensed signal to the normal level for the second time interval, thereby preparing for the next memory cycle and setting the signal back to the desired precharge level.

According to the present invention described above, the sense amplifier can quickly separate the bit lines while maintaining accuracy.

Also, according to the present invention, the length of time for overdriving the signal is directly related to the relative position of the sense amplifier with respect to the sense enable circuit.

[0011]

DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 1, reference numeral 10 designates a memory device, which is one embodiment of the present invention. Although the device 10 is a 256 Mbit dynamic random access memory (“DRAM”) as the preferred embodiment of the present invention, the present invention is not limited to application to DRAM, but any device that requires accurate and fast signal amplification. It should be understood that the present invention can be applied to the integrated circuit of

Device 10 includes a number of control signal pads and power pads. The control signal pads include address pads 12a and 12b, each of which is connected to an external controller (not shown). The power supply pads include a positive power supply (VDD) pad 12c and a ground potential power supply (VSS) pad 12d, each of which is connected to an external power supply (not shown). Device 10 also includes a set of array blocks of memory cells (eg, array block 14) and a group of main address decoders (eg, column decoder 16 and row decoder 18). This array block is selected via the main address decoders 16 and 18 by the signals from the address pads 12a and 12b. Taking array block 14 as a representative of the remaining array blocks, it is further divided into a number of sub-arrays. Each of the sub-arrays is generally designated by the reference character A and will be described in more detail later in connection with FIG.

Referring to FIG. 2, the device 10 has a voltage circuit 20 for generating an internal voltage V1 in addition to the power supplies VDD and VSS. The voltage circuit 20 includes an array power supply (VARY) generator 22, a resistor R1, a transistor 24, and an operational amplifier (OP amplifier) OA1. The VARY generator 22 has VSS <VARY <
It is a conventional voltage generator for generating a voltage VARY which is VDD.

In normal operation, no current flows through resistor R1, so voltage V1 is equal to VARY. As a result, O
The output of P-amp OA1 is VOP equal to VSS and transistor 24 remains off. However, during an overdrive operation, an external power supply (described below) pulls V1 above VARY. This causes the output of the op amp, VOP, to be greater than VSS and transistor 24 is turned on, resulting in V1 being pulled to ground. As V1 is pulled down by transistor 24, a state is reached in which V1 equals VARY. At this time, the output VOP of the OP amplifier becomes equal to VSS again, and the transistor 24 is turned off.

The array block 14 will now be described, with a few sub-arrays and circuits associated with the array block 14 being described. However, the description of the array block 14, the individual sub-arrays of the array block 14, the individual bits of the sub-array, and the circuits around the sub-array is made in a small number only for ease of description. Accordingly, the following description is a simplified version of the preferred embodiment, which is intended to be illustrative of the invention and not limiting.

Referring to FIG. 3, the array block 14 includes m × n sub-arrays Ax, y (1 ≦ x ≦ m, 1 ≦ y ≦.
n). Sub-arrays are referenced in column, row format and include sub-arrays A1,1 to Am, n.
The row of subarray Ax, 1 consists of the subarray closest to the center of device 10 (FIG. 1).
The x, n row consists of the subarray furthest from the center of this device. Each sub-array Ax, y includes a sense amplifier area SAx, y and an overdrive control circuit OVx,
y is connected. For example, the sense amplifier area SA1,
1 and the overdrive control circuit OV1,1 are connected to the sub-array A1,1. Further, each row of the sub-array Ax, y has a sense amplifier control circuit SACy and a selection signal MS.
y, sense signals SANy, SAP1y and SAP2y are connected. For example, the sense amplifier control circuit SAC
1, selection signal MS1, and sense signals SAN1 and SAP
11, SAP21 is a sub-array A1,1, A2,1, ..., Am, 1
It is connected to the.

The selection signals MS1 to MSn are applied to the row decoder 18
The circuit of FIG. 1 is a sense amplifier control circuit SAC1 to SA.
Each is electrically connected to Cn. Similarly, sense signals SAN1 / SAP11 / SAP21 to SANn / SAP
1n / SAP2n are sense amplifier control circuits SAC1 ...
SACn for all rows of overdrive control circuit OVx, 1 ~
Each is electrically connected to OVx, n. The overdrive control circuit OVx, y is also connected to the VSS power supply line 30, the VDD power supply line 32, and the V1 power supply line 34. The sense amplifier control circuits SAC1 to SACn are also connected to the two sense amplifier enable lines SAE1 and SAE2. The VSS power supply line 30 and the VDD power supply line 32 are driven by the VSS pad 12d and the VDD pad 12c (FIG. 1), respectively, and the V1 power supply line 34 is the voltage circuit 20 (FIG. 2).
Driven by two sense amplifier enable lines SA
E1 and SAE2 are driven by a sense amplifier delay (SAD) circuit 35.

Referring to FIG. 4, SAD circuit 35 receives conventional sense amplifier enable signal SAEB and drives two sense amplifier enable lines SAE1 and SAE2. SAE1 signal is SAEB with minimal delay
Follow the signal. However, the SAE2 signal follows the SAEB signal with a significant delay introduced by the series of delay units 36. Each of the delay units 36 is composed of a plurality of capacitive loads and an inverter to delay the propagation of the SAEB signal.

Each of the remaining circuits, signal lines, sense amplifier regions and sub-arrays shown in FIG. 3 is the same. Therefore, in FIGS. 5 and 6 to be described later, only representative sense amplifier control circuits, signal lines, sense amplifier regions, and sub arrays will be described. Typical sense amplifier control circuit,
The description of the signal line, the sense amplifier region, and the sub-array is again a limitation only for facilitating the description. Accordingly, the following description is a further simplified version of the preferred embodiment, which simplification is intended to be illustrative and not limiting of the invention.

Referring to FIG. 5, the SAC circuit receives two sense amplifier enable lines SAE1 and SAE2 and signal MS as input, and three sense signals SAN, SAP1,
Drive SAP2. The select signal MS is used for memory cell selection and is in the active (H) state in the simplified version of the presently considered preferred embodiment. The SAN sense signal is active high and the sense signals SAP1 and SAP2 are active low. SA
The N signal is activated as soon as the SAE1 signal is activated. Similarly, the SAP1 signal is activated as soon as the SAE1 signal is activated.
However, when SAE2 signal becomes active, SAP1
The sense signal is deactivated and the SAP2 sense signal is activated. Therefore, the SAP1 sense signal is active only during the time that the SAE2 signal is delayed from the SAE1 signal.

Referring to FIG. 6, sub-array A includes a plurality of memory cells or "bits", designated B1-B9. The bits are aligned in rows and each row is activated by a word line. For example, the top row contains bits B1 to B3 and is activated by word line WL1, and the bottom row contains bits B7 to B9 and is activated by word line WL3.

Each of the bits is also connected to a bit line. The bit line extends vertically in the sub-array A, passes through the transfer gates 40 and 44, and is sense amplifier area SA.
To the individual sense amplifier circuits located at. For example, the bit line BL is connected to the bits B4 and B7, passes through the transfer gate 40, and reaches the sense amplifier circuit 42. Similarly, the bit line BLB is connected to the bit B1, passes through the transfer gate 44, and reaches the sense amplifier circuit 42. The sense amplifier circuit 42 includes a conventional latch section 46 and equalization section 48. The latch sections of all the sense amplifier circuits in the sense amplifier area SA are controlled by two latch signals SDN and SDP.
Similarly, all normalized sections are controlled by the signal BLEQ and all transfer gates are signal SHR.
Is controlled by

The latch signals SDN and SDP are driven by switch transistors whose sources are common, and these switch transistors have two P-type metal oxide semiconductor (PMOS) transistors 50 and 52 and one N-type metal oxide semiconductor ( NMOS) transistor 54 is included and is located in the overdrive control circuit OV. The PMOS transistor 50 is connected to the V1 power supply line 34 and SD.
It is connected between P latch signal line and its operation is S
It is controlled by the AP2 signal line. The PMOS transistor 52 is connected between the VDD power supply line 32 and the SDP latch signal line, and its operation is controlled by the SAP1 signal line. The NMOS transistor 54 is connected between the VSS power supply line 30 and the SDN latch signal line, and its operation is controlled by the SAN signal line.

Referring to FIGS. 5 to 7, the sensing operation is S
It is started by activating the AEB signal.
Immediately after the SAEB signal is activated, the SAD circuit 35 activates the SAE1 signal.
As a result, the SAC circuit will output the signals SAN and SAP1.
Both are activated and the overdrive period 60 is started. PMOS transistor 52 and NMOS
Transistor 54 is enabled and two latch signals SDP and SDN are connected to VDD and VSS, respectively, to activate them.

In response to the activation of the latch signals SDP and SDN, classification of the data signal on the bit line is started. However, due to the capacitive load on the bit line itself (capacitive load depending on the length of the bit line) and due to all the cells connected to it, the sense amplifier area of the bit line The part located in SA operates differently from the part located in sub-array A. For example, considering two bit lines BL and BLB, the portions of those bit lines located in the sense amplifier area SA are shown by timing diagrams BLSA and BLBSA. Sub-array A of bit lines BL and BLB
Is the timing diagram BLWL and BLB
Indicated by WL. Since the bit line portions represented by BLSA and BLBSA are close to the power supplies (VDD, VSS), the influence of the capacitive load is relatively small, so that the components can be sorted very quickly. However, since the bit line portions represented by BLWL and BLWL are relatively greatly affected by the capacitive load, the classification becomes slow.

During the overdrive period 60, the BLWL and BLSA bit lines reach the VARY voltage level and BLBWL
And held until the BLBSA bit line reaches the VSS voltage level. At that point, the SAC circuit disables the PMOS transistor 52 to cause SA
The P1 signal is made inactive, and the PMOS transistor 5
The SAP2 signal is activated by enabling 0. As a result, the normalization period 62 is started.
During the normalization period 62, the PMOS transistor 50 activates the signal SDP by connecting the latch signal SDP to the V1 power supply line. This normalization period 62 brings the signal on the bit line to the desired VARY voltage level. Then, in the equalization period 65, the signal on the bit line exactly reaches the precharge level (just half the level of VARY and VSS) 63 in response to the BLEQ signal.
Similarly, the BLEQ signal is the latch signals SDN and SD.
Equalize P so that their signals reach the precharge level 63 during the equalization period 65.

Referring also to FIG. 2, the normalization period 62 is augmented by the operation of the voltage circuit 20. Since the SDP latch signal line was previously connected to VDD, it raises the V1 voltage to the VDD voltage level. As a result, V1 voltage is VARY
It rises above the voltage VARY produced by the generator 22. Due to the voltage difference at the inputs of op amp OA1, op amp OA1 turns on transistor 24, shorting V1 to VSS. This discharges the capacitive load of V1 and makes V1 again equal to VARY. Further, the OP amplifier OA1 turns off the transistor 24 again, and the V1 voltage level stabilizes at the VARY voltage level.

The effect of lowering V1 to VSS is more remarkable in the bit line portion arranged in the sense amplifier region than in the bit line portion arranged in the sub-array. For example, the voltage level of the BLSA signal is V
It was at or near DD, but soon VAR
Pulled down to Y. However, the voltage level is VARY first
In the case of the BLWL signal that is close to the level of, the capacitive load of the memory cell connected to the bit line is high, and therefore the voltage substantially remains at that voltage level.

Although FIG. 7 shows a timing diagram for a typical sub-array A, in the preferred embodiment, the timing diagram for each sub-array is position dependent. For example, if sub-array A1,1 is taken as the row of the sub-array closest to the center of device 10 (FIG. 1), the waveform of its bit line is that the bit of sub-array A1, n belonging to the row of the sub-array farthest from the center of the device. It is different from the line waveform. This is because the load resistance and capacitance of the VDD and VSS power lines increases from the center of the device to the edges. As a result, the OV1,1 circuit provides more VDD and VSS power than the OV1, n circuit, which causes the signals on the bitlines of subarray A1,1 to be sorted faster than the signals on the bitlines of subarray A1, n.

Referring to FIG. 8, in the first embodiment, the overdrive period 64 is optimized for the sub-array A1,1. That is, in this embodiment, the overdrive period 64 is set to be just long enough that the signal level of the bit line BLWL of the sub-array A1,1 reaches the VARY level at the time point P1. However, in this embodiment, the bit line BLWL of the sub-array A1, n is
Signal level does not reach VARY level until time P2. As a result, this embodiment works well for subarray A1,1, but does not provide the full overdrive benefits for subarray A1, n.

Referring to FIG. 9, in the second embodiment,
Overdrive period 66 is optimized for sub-array A1, n. In this embodiment, the delay is just long enough that the level of the signal on the bit line BLWL of the sub-array A1, n reaches the level of VARY at time P3.
Furthermore, in this embodiment, the level of the signal on the bit line BLWL of the sub-array A1, i also immediately reaches the level of VARY, as shown at the time point P4. However, the signal overshoot of the bit line BLSA of the sub-array A1,1 is extremely high, and the signal overshoot of the bit line BLWL of the sub-array A1,1 is higher than the level of V1. As a result, it becomes difficult for the SAP21 signal to lower the signal levels of the bit lines BLSA and BLWL of the sub-array A1,1 during the normalization period (FIG. 7). However, as shown in FIG. 3, the capacitor C is positively coupled to the V1 power supply line and V1
If the voltage level of the power supply line is stabilized, the bit line BLSA
It is possible to quickly lower the level of the BLWL signal within a desired period.

With respect to the preferred embodiment, FIG.
Referring to the solid waveform, some benefits of the previous two embodiments have been realized by design considerations. First,
Referring also to FIGS. 3 and 4, the size of the SAE1 driver is larger than the size of the SAE2 driver. In addition, as shown in FIG. 11, the width L1 of the SAE1 signal line is made larger than the width L2 of the SAE2 signal line. In this way, the resistance of the SAE2 signal line is
It is made larger than the resistance of one signal line. As a result, S
The ^RC time constant (t ^RC ) for the AE2 signal line is SAE1.
Larger than the signal line. Therefore, in the sub-array A1,1, the SAE1 signal makes a quick transition, and the SAE1 signal
Two signals make a quick transition. As a result, sub-array A1,
The overdrive period 68 for 1 is relatively short, like the overdrive period 64 in FIG. But,
SAE2 driver is smaller than SAE1 driver,
Since the RC constant of the E2 signal line is larger than that of the SAE1 signal line, the SAE2 signal in the sub-arrays A1, n transits later than the SAE1 signal. As a result, the overdrive period 70 for the sub-arrays A1, n becomes relatively long, like the overdrive period 66 of FIG.

Referring also to FIG. 3, other embodiments can be used to adjust the duration of overdrive. For example, the line portions LP1, LP2, ..., Of the SAE2 signal
In LPn-1, as shown in FIG. 12, delay circuits dl1,
, dln-1 are arranged between the SAC circuits. As a result, the SAE2 signal in subarray A1, n transitions slower than the SAE2 signal in subarray A1,1 and the overdrive period 70 for subarray A1, n is relatively longer than the overdrive period 68 for subarray A1,1. . Also, the delay circuit can be used in combination with the above-described embodiment. It is also possible to provide a circuit for monitoring the voltage of the bit line and adjust the overdrive time corresponding to each sub-array.

Referring again to FIG. 10, the improvement in different lengths of overdrive periods 68 and 70 are illustrated by the solid and dashed waveforms. Dashed lines 72 and 74 indicate BLSA (A1,1) and BLWL (A1,
The waveform corresponding to 1) is shown. Solid lines 73 and 75 are the actual waveforms in the preferred embodiment, but in FIG.
It is similar to the waveforms corresponding to LSA (A1,1) and BLWL (A1,1). This is because the overdrive period 68 is shown in FIG.
Since it is approximately equal to the overdrive period 64 of the subarray A1,1 all the benefits of optimizing the overdrive period for the sub-array A1,1 are maintained. In addition, dashed lines 76 and 78 show waveforms corresponding to BLSA (A1, n) and BLWL (A1, n) in FIG. Solid line 7
7 and 79 are the actual waveforms in the preferred embodiment, but are similar to the waveforms corresponding to BLSA (A1, n) and BLWL (A1, n) in FIG. This is because the overdrive period 70 is approximately equal to the overdrive period 66 of FIG. 9, so all the benefits of optimizing the overdrive period for subarray A 1, n are maintained.

As described above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.

For example, one feature of the invention may be used and another feature may not be used. For example, another embodiment may be implemented to overdrive a low-going bit line with a voltage that exceeds VSS in a negative direction in a controlled manner. In addition, additional buffers, drivers,
Delay circuits and other circuits may also be added to the exemplary embodiments. Therefore, it is appropriate that the claims be interpreted broadly in a manner that does not depart from the scope of the invention.

[0037]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, it is possible to achieve quick signal separation by overdriving signals while maintaining the accuracy of the sense amplifier operation.

[Brief description of drawings]

FIG. 1 is a 256 Mbit DR which is an embodiment of the present invention.
It is a block diagram of AM.

FIG. 2 is a circuit diagram of a voltage source.

FIG. 3 is a block diagram of an array block of the 256 Mbit DRAM of FIG.

FIG. 4 is a circuit diagram of the sense amplifier delay unit of FIG.

5 is a circuit diagram of one sense amplifier control unit in FIG.

FIG. 6 is a circuit diagram of one sub-array of FIG.

FIG. 7 is a timing diagram of the circuits of FIGS. 4-6.

FIG. 8 is a timing diagram of a first embodiment of an overdrive circuit according to the present invention.

FIG. 9 is a timing diagram of a second embodiment of an overdrive circuit according to the present invention.

FIG. 10 is a timing diagram of a preferred embodiment of the overdrive circuit of the present invention.

FIG. 11 is a diagram showing an example of a preferred embodiment of an overdrive circuit of the present invention.

FIG. 12 is a diagram showing another example of the preferred embodiment of the overdrive circuit of the present invention.

[Explanation of symbols]

 10 DRAM (device) 12a, 12b Address pad 12c, 12d Power supply pad 14 Array block 16 Column decoder 18 Row decoder 20 Voltage circuit 22 VARY generator 24 Transistor A Sub-array B Memory cell (bit) BL, BLB Bit line SA Sense amplifier area SAC Sense amplifier control circuit SAD Sense amplifier delay circuit OV Overdrive control circuit WL Word line

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Takesada Akiba, Texas 75024, Preno, Preston Road 6900, # 3922 (72) Inventor Goro Tachikawa, Texas 75024, Preno, Preston Road 6900, # 3023 (72) Inventor Hugh McCaddams, Texas 75070, USA 75070, McKinney, RT 4 Box 55 (54) [Title of Invention] To drive data signal of semiconductor memory and circuit to desired level Device, a circuit for driving the first and second signals to a desired level, a dynamic random access memory structure, a method for driving a data signal to a desired level, and a first and second signal for a desired level. How to drive to the bell

Claims (40)

[Claims] 1. A pair of bit lines, a plurality of word lines, and a plurality of dynamic memory cells each coupled to one of the bit lines forming the bit line pair and one of the plurality of word lines. Of a PMOS transistor and a pair of NMOS transistors, each of the PMOS transistor pair and the NMOS transistor pair being coupled to a commonly coupled source and the bit line pair, respectively. A sense amplifier having a drain and a gate cross-coupled to the drain, a first power supply terminal, a second power supply terminal, a pair of the first power supply terminal and the PMOS transistor, and A first switch transistor coupled between the source and the second power supply terminal and the PMOS transistor pair; A second switch transistor coupled between the first power supply terminal and the second switch transistor, and a voltage for supplying the first power supply terminal with a first voltage lower than a second voltage supplied to the second power supply terminal. A semiconductor memory having a generator, wherein the sense amplifier, based on information about a memory cell selected from the plurality of dynamic memory cells, a high-side voltage and a low-side voltage with respect to the bit line pair. Providing a pair of complementary signals having a voltage such that the high side voltage is above the first voltage in response to the second switch transistor being enabled in a first period. The high-side voltage is raised in response to the first switch transistor being enabled in a second period subsequent to the first period, and thereby the high-side voltage is lowered. Te,
A semiconductor memory, wherein the high-side voltage is set to the first voltage. 2. The semiconductor memory according to claim 1, wherein
The semiconductor memory, wherein the voltage generator has a discharge circuit for decreasing the high-side voltage. 3. The semiconductor memory according to claim 2, wherein
Further comprising a third power supply terminal for receiving a third voltage, and a third switch transistor coupled between the third power supply terminal and the source of the pair of NMOS transistors, A semiconductor memory, wherein the low-side voltage is set to the third voltage in response to the third switch transistor being enabled in the first and second periods. 4. A first and second power supply terminal, each having a first end coupled to a corresponding one of the first and second power supply terminals, and each in the same direction as each other. Each of the extending first and second power supply lines, each of the first and second memory blocks includes a plurality of pairs of bit lines, a plurality of word lines, a plurality of dynamic memory cells, and a plurality of pairs of bits. A plurality of sense amplifiers each coupled to the line, each of the plurality of sense amplifiers having a pair of PMOS transistors and a pair of NMs.
An OS transistor, each pair of the PMOS and NMOS transistors has a source commonly coupled, a drain coupled to a corresponding pair of bit lines, and a gate cross-coupled to the drain. And a first switch coupled between a first portion of the first power supply line and the source of the pair of PMOS transistors of the first memory block. A transistor; a second switch transistor coupled between the second portion of the second power supply line and the source of the pair of PMOS transistors of the first memory block; and the first power supply line. A third switch coupled between a third portion of the second memory block and the source of the pair of PMOS transistors of the second memory block. A transistor, a fourth switch transistor coupled between the fourth portion of the second power supply line and the source of the pair of PMOS transistors of the second memory block, and the first power supply terminal And a voltage generator for providing a first voltage lower than a second voltage supplied to the second power supply terminal, wherein Is disposed between the third part of the first power supply line and the first power supply terminal, and the second part of the second power supply line is connected to the second power supply line. Of the sense amplifiers in the first memory block are selected from the plurality of dynamic memory cells in the first memory block. Memory cells Supplying a pair of first complementary signals having a high-side voltage and a low-side voltage to the corresponding bit line pair based on the information stored in the first bit line, The high side voltage of the pair of complementary signals is raised above the first voltage in response to the second switch transistor being enabled, and for a second time period following the first time period. , The high side voltage of the first pair of complementary signals is lowered in response to the first switch transistor being enabled, whereby the high side voltage is reduced to the first side. A semiconductor memory characterized by being set to a voltage. 5. The semiconductor memory according to claim 4, wherein each of the sense amplifiers of the second memory block is a memory cell selected from the plurality of dynamic memory cells of the second memory block. Providing a second complementary pair of signals having a high side voltage and a low side voltage to a corresponding pair of bit lines based on the stored information, and in a third period, the fourth complementary signal pair; In response to the switch transistor being enabled, the high side voltage of the second pair of complementary signals is raised, and the third switch transistor is turned on in a fourth period following the third period. In response to being enabled, the high side voltage of the second pair of complementary signals is continuously raised, thereby setting the high side voltage to the first voltage. A semiconductor memory characterized in that. 6. A data signal to a desired level comprising overdriving a data signal with an overdrive voltage for a first period and driving the data signal with a second voltage for a second period. A method of driving a data signal to a desired level, which comprises raising the data signal to a desired level with a second voltage. 7. A method of driving a data signal to a desired level according to claim 6, wherein the overdrive voltage exceeds the desired level. Method. 8. The method of driving a data signal of claim 6 to a desired level, wherein the first period is initiated by a first enable signal and the second period is a second enable. A method of driving a data signal to a desired level, which is characterized by being initiated by a signal. 9. A method for driving a data signal according to claim 8 to a desired level, wherein the data signal is used in an amplifier circuit and the first and second enable signals are generated by an enable circuit. A method for driving a data signal to a desired level, wherein the length of the first period depends on the relative position of the amplifier circuit with respect to the enable circuit. 10. A method of driving a first and a second signal to a desired level, comprising overdriving the first signal with an overdrive voltage during a first period and during a second period. Overdriving the second signal with the overdrive voltage; driving the first signal with a second voltage during a third period; and driving the second signal with a second period during a fourth period. Driving with a second voltage, wherein the second voltage raises the first and second signals to the desired level. How to drive to the desired level. 11. The method of driving the first and second signals of claim 10 to a desired level, wherein the overdrive voltage pulls the first signal above the desired level. And driving the first and second signals to a desired level. 12. A method of driving the first and second signals to a desired level according to claim 10, wherein the first and second periods are initiated by a first enable signal and a second Driving the first and second signals to a desired level, characterized in that the third and fourth periods are ended by the second enable signal. 13. A method for driving the first and second signals to a desired level according to claim 12, wherein the first and second signals are used in first and second signal circuits, The enable signal is generated by an enable signal circuit, the lengths of the first and second periods are dependent on a relative position of the first signal circuit with respect to the enable signal circuit, and the third and Driving the first and second signals to a desired level, characterized in that the length of the fourth period depends on the relative position of the second signal circuit with respect to the enable signal circuit. Method. 14. A method for driving the first and second signals to a desired level according to claim 12, wherein the first and second periods have different lengths.
And a method of driving the second signal to a desired level. 15. A method for driving the first and second signals to a desired level according to claim 14, wherein the first signal initiates the first and second time periods substantially simultaneously. Method of driving first and second signals to a desired level, characterized in that the second signal ends the second period after the second signal ends the first period. . 16. A method for driving the first and second signals to a desired level according to claim 15, wherein the first and second signals are used in first and second circuits, respectively. The first and the second circuits are characterized in that the time difference between the length of the first period and the length of the second period depends on the relative position of the first and second circuits. A method of driving the second signal to a desired level. 17. A method for driving the first and second signals to a desired level according to claim 12, wherein the second voltage is the first portion of the third and fourth periods. A method of driving a first and a second signal to a desired level which is less than the desired level and is equal to the desired level for the remainder of the third and fourth time periods. 18. An apparatus for driving a data signal of a circuit to a desired level, comprising means for overdriving the data signal with an overdrive voltage during a first period, and the data signal having a desired level. Means for driving the data signal with a second voltage during a second period to pull it down to a level, a device for driving a data signal of a circuit to a desired level. 19. An apparatus for driving a data signal of a circuit according to claim 18 to a desired level, said means for overdriving said data signal at said overdrive voltage said signal being said desired signal. A device for driving a data signal of a circuit to a desired level, which is characterized in that it is raised to a level higher than or equal to. 20. A device for driving a data signal of a circuit according to claim 18 to a desired level, further comprising a first enable signal for starting the first period and the first signal. Device for driving the data signal of the circuit to a desired level, the device having a second enable signal for terminating the period and the beginning of the second period. 21. An apparatus for driving the data signal of the circuit of claim 20 to a desired level, further comprising an enable circuit for generating the first and second enable signals, To drive the data signal of the circuit to a desired level, characterized in that the timing of the generation of the second enable signal is dependent on the distance between the position of the enable circuit and the position of the data circuit. Equipment. 22. A circuit for driving the first and second signals to a desired level, means for overdriving the first signal with an overdrive voltage during a first period; Means for overdriving the second signal with an overdrive voltage during a second period, means for driving the first signal with a second voltage during a third period, and a fourth period during Means for driving the second signal at the second voltage, the means for driving the second voltage pulling down the first and second signals to the desired level. Characterized by being
A circuit for driving the first and second signals to a desired level. 23. A circuit for driving the first and second signals of claim 22 to a desired level, wherein the means for overdriving with an overdrive voltage comprises the first and second signals. A circuit for driving a first and a second signal to a desired level, characterized in that it pulls the signal above the desired level. 24. A circuit for driving the first and second signals according to claim 22 to a desired level, further comprising: a first circuit for starting the first and second periods.
And the means for generating the second enable signal for ending the first and second periods and for starting the third and fourth periods. A circuit for driving the first and second signals to a desired level. 25. A circuit for driving the first and second signals of claim 24 to a desired level, said means for overdriving said first signal and said second signal. Are of the same circuit, and the length of the first period is longer than the length of the second period.
A circuit for driving the first and second signals to a desired level. 26. A circuit for driving the first and second signals according to claim 25 to a desired level, wherein the difference between the lengths of the first and second periods is the first Characterized in that the means for overdriving the signal and the means for overdriving the second signal are position dependent with respect to the means for generating the first enable signal. , A circuit for driving the first and second signals to a desired level. 27. A circuit for driving the first and second signals to a desired level according to claim 26, wherein the first signal causes the first and second periods to start at substantially the same time. Driving the first and second signals to a desired level, wherein the second signal ends the first period and then the second signal ends the second period. Circuit to do. 28. A circuit for driving the first and second signals of claim 27 to a desired level, the circuit comprising a time interval between the end of the first period and the second period. A circuit for driving the first and second signals to a desired level, the length of which is determined by the arrangement of the first and second signals. 29. A circuit for driving the first and second signals according to claim 24 to a desired level, wherein the second voltage is applied in the first portion of the third and fourth periods. Is smaller than the desired level, and the third and fourth
Circuit for driving the first and second signals to a desired level, characterized in that it is equal to the desired level for the remainder of the period. 30. A dynamic random access memory structure comprising: means for supplying a VDD voltage level; means for supplying a VSS voltage level; a voltage circuit for supplying a V1 voltage level; and a first voltage level A first bit line for passing a signal, a second bit line for passing a signal of a second voltage level, and a first bit line for driving the signal of the first voltage level to a V1 voltage level. A first sense amplifier circuit connected to the second bit line, a second sense amplifier circuit connected to the second bit line for driving the signal of the second voltage level to the V1 voltage level, and a control circuit. Means for overdriving the first sense amplifier circuit at the VDD voltage level during the first period, and overdriving the second sense amplifier circuit at the VDD voltage level during the second period. A control circuit having means for driving the first bit line at a variable voltage level during a third period, and means for driving the second bit line at a variable voltage level for a fourth period. A signal of the voltage level on the first and second bit lines is driven to a voltage level above the V1 voltage level during the first and second periods, and to a V1 voltage level during the third and fourth periods. A dynamic random access memory structure characterized by being driven. 31. The dynamic random access memory structure according to claim 30, wherein the control circuit further comprises a first for starting the first and second periods.
And an enable circuit for generating a second enable signal for ending the first and second periods and starting the third and fourth periods. Random access memory structure. 32. The dynamic random access memory structure according to claim 31, wherein, in the control circuit, each length of the first and third periods is relative to the enable circuit. Dynamic random access memory structure, wherein each length of the second and fourth periods depends on a relative position of the second sense amplifier circuit to the enable circuit. 33. The dynamic random access memory structure according to claim 32, wherein the control circuit has different lengths of the first and second periods. 34. The dynamic random access memory structure according to claim 33, wherein in the control circuit, the first signal starts the first and second periods at substantially the same time, and the second signal is A dynamic random access memory structure, wherein the second signal ends the second period after ending the first period. 35. The dynamic random access memory structure according to claim 34, wherein in the control circuit, the length of time between the end of the first period and the second period is the first and the second period. A dynamic random access memory structure characterized by being determined by the position of a second bit line. 36. The dynamic random access memory structure according to claim 31, wherein in the control circuit, the V in the first portion of the third and fourth periods.
1. A dynamic random access memory structure, wherein the voltage level is less than the desired level and is equal to the desired level for the remainder of the third and fourth time periods. 37. The semiconductor memory according to claim 1, wherein each of the plurality of pairs of bit lines has a first side to which the dynamic memory cell is coupled and a second side to which the drains of the pair of PMOS transistors are coupled. And a pair of switch transistors provided between a first side and a second side of the bit line pair, the pair of switch transistors being in an ON state during the first period. The semiconductor memory according to claim 1, wherein the voltage on the high side rises higher than the first voltage on the first side of the bit line pair. 38. The semiconductor memory according to claim 5, wherein the third period is longer than the first period. 39. The semiconductor memory according to claim 38, wherein start times of the first period and the third period are substantially equal to each other. 40. The semiconductor memory according to claim 39, wherein each bit line pair of the first and second memory blocks has a first side to which a dynamic memory cell is coupled and the pair of PMOS transistors of a sense amplifier. A pair of switch transistors provided between the first side and the second side of the bit line pair, wherein the pair of switch transistors are The first, second, third, and fourth periods are turned on, and the high-side voltage is on the first side of the bit line pair during the first, second, third, and fourth periods. A semiconductor memory characterized in that the voltage is set to be equal to or lower than the first voltage.